src/scoreboard/dependence_cell.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat, Repl
   4 from nmutil.latch import SRLatch
   5 from functools import reduce
   6 from operator import or_
   7
   8
   9 class DependencyRow(Elaboratable):
  10     """ implements 11.4.7 mitch alsup dependence cell, p27
  11         adjusted to be clock-sync'd on rising edge only.
  12         mitch design (as does 6600) requires alternating rising/falling clock
  13
  14         * SET mode: issue_i HI, go_i LO, reg_i HI - register is captured
  15                                                   - FWD is DISABLED (~issue_i)
  16                                                   - RSEL DISABLED
  17         * QRY mode: issue_i LO, go_i LO, haz_i HI - FWD is ASSERTED
  18                                          reg_i HI - ignored
  19         * GO mode : issue_i LO, go_i HI           - RSEL is ASSERTED
  20                                          haz_i HI - FWD still can be ASSERTED
  21
  22         FWD assertion (hazard protection) therefore still occurs in both
  23         Query and Go Modes, for this cycle, due to the cq register
  24
  25         GO mode works for one cycle, again due to the cq register capturing
  26         the latch output.  Without the cq register, the SR Latch (which is
  27         asynchronous) would be reset at the exact moment that GO was requested,
  28         and the RSEL would be garbage.
  29     """
  30     def __init__(self, n_reg, n_src):
  31         self.n_reg = n_reg
  32         self.n_src = n_src
  33         # arrays
  34         src = []
  35         rsel = []
  36         fwd = []
  37         for i in range(n_src):
  38             j = i + 1 # name numbering to match src1/src2
  39             src.append(Signal(n_reg, name="src%d" % j, reset_less=True))
  40             rsel.append(Signal(n_reg, name="src%d_rsel_o" % j, reset_less=True))
  41             fwd.append(Signal(n_reg, name="src%d_fwd_o" % j, reset_less=True))
  42
  43         # inputs
  44         self.dest_i = Signal(n_reg, reset_less=True)     # Dest in (top)
  45         self.src_i = Array(src)     # operands in (top)
  46         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  47
  48         self.rd_pend_i = Signal(n_reg, reset_less=True) # Read pend in (top)
  49         self.wr_pend_i = Signal(n_reg, reset_less=True) # Write pend in (top)
  50         self.v_rd_rsel_o = Signal(n_reg, reset_less=True) # Read pend out (bot)
  51         self.v_wr_rsel_o = Signal(n_reg, reset_less=True) # Write pend out (bot)
  52
  53         self.go_wr_i = Signal(reset_less=True) # Go Write in (left)
  54         self.go_rd_i = Signal(reset_less=True)  # Go Read in (left)
  55         self.go_die_i = Signal(reset_less=True) # Go Die in (left)
  56
  57         # for Register File Select Lines (vertical)
  58         self.dest_rsel_o = Signal(n_reg, reset_less=True)  # dest reg sel (bot)
  59         self.src_rsel_o = Array(rsel)   # src reg sel (bot)
  60         self.src2_rsel_o = Signal(n_reg, reset_less=True)  # src2 reg sel (bot)
  61
  62         # for Function Unit "forward progress" (horizontal)
  63         self.dest_fwd_o = Signal(n_reg, reset_less=True)   # dest FU fw (right)
  64         self.src_fwd_o = Array(fwd)    # src FU fw (right)
  65
  66     def elaborate(self, platform):
  67         m = Module()
  68         m.submodules.dest_c = dest_c = SRLatch(sync=False, llen=self.n_reg)
  69         src_c = []
  70         for i in range(self.n_src):
  71             src_l = SRLatch(sync=False, llen=self.n_reg)
  72             setattr(m.submodules, "src%d_c" % (i+1), src_l)
  73             src_c.append(src_l)
  74
  75         # connect go_rd / go_wr (dest->wr, src->rd)
  76         wr_die = Signal(reset_less=True)
  77         rd_die = Signal(reset_less=True)
  78         m.d.comb += wr_die.eq(self.go_wr_i | self.go_die_i)
  79         m.d.comb += rd_die.eq(self.go_rd_i | self.go_die_i)
  80         m.d.comb += dest_c.r.eq(Repl(wr_die, self.n_reg))
  81         for i in range(self.n_src):
  82             m.d.comb += src_c[i].r.eq(Repl(rd_die, self.n_reg))
  83
  84         # connect input reg bit (unary)
  85         i_ext = Repl(self.issue_i, self.n_reg)
  86         m.d.comb += dest_c.s.eq(i_ext & self.dest_i)
  87         for i in range(self.n_src):
  88             m.d.comb += src_c[i].s.eq(i_ext & self.src_i[i])
  89
  90         # connect up hazard checks: read-after-write and write-after-read
  91         m.d.comb += self.dest_fwd_o.eq(dest_c.q & self.rd_pend_i)
  92         for i in range(self.n_src):
  93             m.d.comb += self.src_fwd_o[i].eq(src_c[i].q & self.wr_pend_i)
  94
  95         # connect reg-sel outputs
  96         rd_ext = Repl(self.go_rd_i, self.n_reg)
  97         wr_ext = Repl(self.go_wr_i, self.n_reg)
  98         m.d.comb += self.dest_rsel_o.eq(dest_c.qlq & wr_ext)
  99         for i in range(self.n_src):
 100             m.d.comb += self.src_rsel_o[i].eq(src_c[i].qlq & rd_ext)
 101
 102         # to be accumulated to indicate if register is in use (globally)
 103         # after ORing, is fed back in to rd_pend_i / wr_pend_i
 104         src_q = []
 105         for i in range(self.n_src):
 106             src_q.append(src_c[i].qlq)
 107         m.d.comb += self.v_rd_rsel_o.eq(reduce(or_, src_q))
 108         m.d.comb += self.v_wr_rsel_o.eq(dest_c.qlq)
 109
 110         return m
 111
 112     def __iter__(self):
 113         yield self.dest_i
 114         yield from self.src_i
 115         yield self.rd_pend_i
 116         yield self.wr_pend_i
 117         yield self.issue_i
 118         yield self.go_wr_i
 119         yield self.go_rd_i
 120         yield self.go_die_i
 121         yield self.dest_rsel_o
 122         yield from self.src_rsel_o
 123         yield self.dest_fwd_o
 124         yield from self.src_fwd_o
 125
 126     def ports(self):
 127         return list(self)
 128
 129
 130 def dcell_sim(dut):
 131     yield dut.dest_i.eq(1)
 132     yield dut.issue_i.eq(1)
 133     yield
 134     yield dut.issue_i.eq(0)
 135     yield
 136     yield dut.src1_i.eq(1)
 137     yield dut.issue_i.eq(1)
 138     yield
 139     yield
 140     yield
 141     yield dut.issue_i.eq(0)
 142     yield
 143     yield dut.go_rd_i.eq(1)
 144     yield
 145     yield dut.go_rd_i.eq(0)
 146     yield
 147     yield dut.go_wr_i.eq(1)
 148     yield
 149     yield dut.go_wr_i.eq(0)
 150     yield
 151
 152 def test_dcell():
 153     dut = DependencyRow(4, 2)
 154     vl = rtlil.convert(dut, ports=dut.ports())
 155     with open("test_drow.il", "w") as f:
 156         f.write(vl)
 157
 158     run_simulation(dut, dcell_sim(dut), vcd_name='test_dcell.vcd')
 159
 160 if __name__ == '__main__':
 161     test_dcell()