src/scoreboard/fu_fu_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat, Const
   4
   5 #from nmutil.latch import SRLatch
   6 from .fu_dep_cell import FUDependenceCell
   7 from .fu_picker_vec import FU_Pick_Vec
   8
   9 """
  10
  11  6600 Function Unit Dependency Table Matrix inputs / outputs
  12  -----------------------------------------------------------
  13
  14 """
  15
  16 class FUFUDepMatrix(Elaboratable):
  17     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  18     """
  19     def __init__(self, n_fu_row, n_fu_col):
  20         self.n_fu_row = n_fu_row                  # Y (FU row#)   ^v
  21         self.n_fu_col = n_fu_col                # X (FU col #)  <>
  22         self.rd_pend_i = Signal(n_fu_row, reset_less=True) # Rd pending (left)
  23         self.wr_pend_i = Signal(n_fu_row, reset_less=True) # Wr pending (left)
  24         self.issue_i = Signal(n_fu_col, reset_less=True)    # Issue in (top)
  25
  26         self.go_wr_i = Signal(n_fu_row, reset_less=True) # Go Write in (left)
  27         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  28         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  29
  30         # for Function Unit Readable/Writable (horizontal)
  31         self.readable_o = Signal(n_fu_col, reset_less=True) # readable (bot)
  32         self.writable_o = Signal(n_fu_col, reset_less=True) # writable (bot)
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36
  37         # ---
  38         # matrix of dependency cells
  39         # ---
  40         dm = Array(FUDependenceCell(self.n_fu_row) \
  41                                             for f in range(self.n_fu_col))
  42         for x in range(self.n_fu_col):
  43                 setattr(m.submodules, "dm%d" % x, dm[x])
  44
  45         # ---
  46         # array of Function Unit Readable/Writable: row-length, horizontal
  47         # ---
  48         fur = Array(FU_Pick_Vec(self.n_fu_row) for r in range(self.n_fu_col))
  49         for x in range(self.n_fu_col):
  50             setattr(m.submodules, "fur_x%d" % (x), fur[x])
  51
  52         # ---
  53         # connect FU Readable/Writable vector
  54         # ---
  55         readable = []
  56         writable = []
  57         for x in range(self.n_fu_col):
  58             fu = fur[x]
  59             # accumulate Readable/Writable Vector outputs
  60             readable.append(fu.readable_o)
  61             writable.append(fu.writable_o)
  62
  63         # ... and output them from this module (horizontal, width=REGs)
  64         m.d.comb += self.readable_o.eq(Cat(*readable))
  65         m.d.comb += self.writable_o.eq(Cat(*writable))
  66
  67         # ---
  68         # connect FU Pending
  69         # ---
  70         for y in range(self.n_fu_row):
  71             fu = fur[y]
  72             rd_wait_o = []
  73             wr_wait_o = []
  74             for x in range(self.n_fu_col):
  75                 dc = dm[x]
  76                 # accumulate cell outputs rd/wr-pending
  77                 rd_wait_o.append(dc.rd_wait_o[y])
  78                 wr_wait_o.append(dc.wr_wait_o[y])
  79             # connect cell reg-select outputs to Reg Vector In
  80             m.d.comb += [fu.rd_pend_i.eq(Cat(*rd_wait_o)),
  81                          fu.wr_pend_i.eq(Cat(*wr_wait_o)),
  82                         ]
  83
  84         # ---
  85         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
  86         # ---
  87         for x in range(self.n_fu_col):
  88             dc = dm[x]
  89             issue_i = []
  90             for y in range(self.n_fu_row):
  91                 # accumulate cell inputs issue
  92                 issue_i.append(dc.issue_i[y])
  93             # wire up inputs from module to row cell inputs (Cat is gooood)
  94             m.d.comb += Cat(*issue_i).eq(self.issue_i)
  95
  96         # ---
  97         # connect Matrix go_rd_i/go_wr_i to module readable/writable
  98         # ---
  99         for y in range(self.n_fu_row):
 100             go_rd_i = []
 101             go_wr_i = []
 102             go_die_i = []
 103             for x in range(self.n_fu_col):
 104                 dc = dm[x]
 105                 # accumulate cell go_rd/go_wr
 106                 go_rd_i.append(dc.go_rd_i[y])
 107                 go_wr_i.append(dc.go_wr_i[y])
 108                 go_die_i.append(dc.go_die_i[y])
 109             # wire up inputs from module to row cell inputs (Cat is gooood)
 110             m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
 111                          Cat(*go_wr_i).eq(self.go_wr_i),
 112                          Cat(*go_die_i).eq(self.go_die_i),
 113                         ]
 114
 115
 116         # ---
 117         # connect Matrix pending
 118         # ---
 119         for y in range(self.n_fu_row):
 120             rd_pend_i = []
 121             wr_pend_i = []
 122             for x in range(self.n_fu_col):
 123                 dc = dm[x]
 124                 if x == y: # ignore hazards on the diagonal: self-against-self
 125                     dummyrd = Signal(reset_less=True)
 126                     dummywr = Signal(reset_less=True)
 127                     rd_pend_i.append(dummyrd)
 128                     wr_pend_i.append(dummywr)
 129                     continue
 130                 # accumulate cell rd_pend/wr_pend/go_rd/go_wr
 131                 rd_pend_i.append(dc.rd_pend_i[y])
 132                 wr_pend_i.append(dc.wr_pend_i[y])
 133             # wire up inputs from module to row cell inputs (Cat is gooood)
 134             m.d.comb += [Cat(*rd_pend_i).eq(self.rd_pend_i),
 135                          Cat(*wr_pend_i).eq(self.wr_pend_i),
 136                         ]
 137
 138         return m
 139
 140     def __iter__(self):
 141         yield self.rd_pend_i
 142         yield self.wr_pend_i
 143         yield self.issue_i
 144         yield self.go_wr_i
 145         yield self.go_rd_i
 146         yield self.readable_o
 147         yield self.writable_o
 148
 149     def ports(self):
 150         return list(self)
 151
 152 def d_matrix_sim(dut):
 153     """ XXX TODO
 154     """
 155     yield dut.dest_i.eq(1)
 156     yield dut.issue_i.eq(1)
 157     yield
 158     yield dut.issue_i.eq(0)
 159     yield
 160     yield dut.src1_i.eq(1)
 161     yield dut.issue_i.eq(1)
 162     yield
 163     yield dut.issue_i.eq(0)
 164     yield
 165     yield dut.go_rd_i.eq(1)
 166     yield
 167     yield dut.go_rd_i.eq(0)
 168     yield
 169     yield dut.go_wr_i.eq(1)
 170     yield
 171     yield dut.go_wr_i.eq(0)
 172     yield
 173
 174 def test_fu_fu_matrix():
 175     dut = FUFUDepMatrix(n_fu_row=3, n_fu_col=4)
 176     vl = rtlil.convert(dut, ports=dut.ports())
 177     with open("test_fu_fu_matrix.il", "w") as f:
 178         f.write(vl)
 179
 180     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_fu_matrix.vcd')
 181
 182 if __name__ == '__main__':
 183     test_fu_fu_matrix()