src/scoreboard/fu_reg_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat
   4
   5 from scoreboard.dependence_cell import DependencyRow
   6 from scoreboard.fu_wr_pending import FU_RW_Pend
   7 from scoreboard.reg_select import Reg_Rsv
   8 from scoreboard.global_pending import GlobalPending
   9
  10 """
  11
  12  6600 Dependency Table Matrix inputs / outputs
  13  ---------------------------------------------
  14
  15                 d s1 s2 i  d s1 s2 i  d s1 s2 i  d s1 s2 i
  16                 | |   | |  | |   | |  | |   | |  | |   | |
  17                 v v   v v  v v   v v  v v   v v  v v   v v
  18  go_rd/go_wr -> dm-r0-fu0  dm-r1-fu0  dm-r2-fu0  dm-r3-fu0 -> wr/rd-pend
  19  go_rd/go_wr -> dm-r0-fu1  dm-r1-fu1  dm-r2-fu1  dm-r3-fu1 -> wr/rd-pend
  20  go_rd/go_wr -> dm-r0-fu2  dm-r1-fu2  dm-r2-fu2  dm-r3-fu2 -> wr/rd-pend
  21                  |  |  |    |  |  |    |  |  |    |  |  |
  22                  v  v  v    v  v  v    v  v  v    v  v  v
  23                  d  s1 s2   d  s1 s2   d  s1 s2   d  s1 s2
  24                  reg sel    reg sel    reg sel    reg sel
  25
  26 """
  27
  28 class FURegDepMatrix(Elaboratable):
  29     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  30     """
  31     def __init__(self, n_fu_row, n_reg_col, n_src):
  32         self.n_src = n_src
  33         self.n_fu_row = nf = n_fu_row      # Y (FUs)   ^v
  34         self.n_reg_col = n_reg = n_reg_col   # X (Regs)  <>
  35
  36         # arrays
  37         src = []
  38         rsel = []
  39         for i in range(n_src):
  40             j = i + 1 # name numbering to match src1/src2
  41             src.append(Signal(n_reg, name="src%d" % j, reset_less=True))
  42             rsel.append(Signal(n_reg, name="src%d_rsel_o" % j, reset_less=True))
  43         pend = []
  44         for i in range(nf):
  45             j = i + 1 # name numbering to match src1/src2
  46             pend.append(Signal(nf, name="rd_src%d_pend_o" % j, reset_less=True))
  47
  48         self.dest_i = Signal(n_reg_col, reset_less=True)     # Dest in (top)
  49         self.src_i = Array(src)                              # oper in (top)
  50
  51         # Register "Global" vectors for determining RaW and WaR hazards
  52         self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top)
  53         self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top)
  54         self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
  55         self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
  56
  57         self.issue_i = Signal(n_fu_row, reset_less=True)  # Issue in (top)
  58         self.go_wr_i = Signal(n_fu_row, reset_less=True)  # Go Write in (left)
  59         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  60         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  61
  62         # for Register File Select Lines (horizontal), per-reg
  63         self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot)
  64         self.src_rsel_o = Array(rsel)                         # src reg (bot)
  65
  66         # for Function Unit "forward progress" (vertical), per-FU
  67         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
  68         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
  69         self.rd_src_pend_o = Array(pend) # src1 pending
  70
  71     def elaborate(self, platform):
  72         m = Module()
  73
  74         # ---
  75         # matrix of dependency cells
  76         # ---
  77         dm = Array(DependencyRow(self.n_reg_col, self.n_src) \
  78                     for r in range(self.n_fu_row))
  79         for fu in range(self.n_fu_row):
  80             setattr(m.submodules, "dr_fu%d" % fu, dm[fu])
  81
  82         # ---
  83         # array of Function Unit Pending vectors
  84         # ---
  85         fupend = Array(FU_RW_Pend(self.n_reg_col, self.n_src) \
  86                         for f in range(self.n_fu_row))
  87         for fu in range(self.n_fu_row):
  88             setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu])
  89
  90         # ---
  91         # array of Register Reservation vectors
  92         # ---
  93         regrsv = Array(Reg_Rsv(self.n_fu_row, self.n_src) \
  94                         for r in range(self.n_reg_col))
  95         for rn in range(self.n_reg_col):
  96             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
  97
  98         # ---
  99         # connect Function Unit vector
 100         # ---
 101         wr_pend = []
 102         rd_pend = []
 103         for fu in range(self.n_fu_row):
 104             dc = dm[fu]
 105             fup = fupend[fu]
 106             dest_fwd_o = []
 107             for rn in range(self.n_reg_col):
 108                 # accumulate cell fwd outputs for dest/src1/src2
 109                 dest_fwd_o.append(dc.dest_fwd_o[rn])
 110             # connect cell fwd outputs to FU Vector in [Cat is gooood]
 111             m.d.comb += [fup.dest_fwd_i.eq(Cat(*dest_fwd_o)),
 112                         ]
 113             # accumulate FU Vector outputs
 114             wr_pend.append(fup.reg_wr_pend_o)
 115             rd_pend.append(fup.reg_rd_pend_o)
 116
 117         # ... and output them from this module (vertical, width=FUs)
 118         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
 119         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 120
 121         # same for src
 122         for i in range(self.n_src):
 123             rd_src_pend = []
 124             for fu in range(self.n_fu_row):
 125                 dc = dm[fu]
 126                 fup = fupend[fu]
 127                 src_fwd_o = []
 128                 for rn in range(self.n_reg_col):
 129                     # accumulate cell fwd outputs for dest/src1/src2
 130                     src_fwd_o.append(dc.src_fwd_o[i][rn])
 131                 # connect cell fwd outputs to FU Vector in [Cat is gooood]
 132                 m.d.comb += [fup.src_fwd_i[i].eq(Cat(*src_fwd_o)),
 133                             ]
 134                 # accumulate FU Vector outputs
 135                 rd_src_pend.append(fup.reg_rd_src_pend_o[i])
 136             # ... and output them from this module (vertical, width=FUs)
 137             m.d.comb += self.rd_src_pend_o[i].eq(Cat(*rd_src_pend))
 138
 139         # ---
 140         # connect Reg Selection vector
 141         # ---
 142         dest_rsel = []
 143         for rn in range(self.n_reg_col):
 144             rsv = regrsv[rn]
 145             dest_rsel_o = []
 146             for fu in range(self.n_fu_row):
 147                 dc = dm[fu]
 148                 # accumulate cell reg-select outputs dest/src1/src2
 149                 dest_rsel_o.append(dc.dest_rsel_o[rn])
 150             # connect cell reg-select outputs to Reg Vector In
 151             m.d.comb += rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
 152
 153             # accumulate Reg-Sel Vector outputs
 154             dest_rsel.append(rsv.dest_rsel_o)
 155
 156         # ... and output them from this module (horizontal, width=REGs)
 157         m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
 158
 159         # same for src
 160         for i in range(self.n_src):
 161             src_rsel = []
 162             for rn in range(self.n_reg_col):
 163                 rsv = regrsv[rn]
 164                 src_rsel_o = []
 165                 for fu in range(self.n_fu_row):
 166                     dc = dm[fu]
 167                     # accumulate cell reg-select outputs dest/src1/src2
 168                     src_rsel_o.append(dc.src_rsel_o[i][rn])
 169                 # connect cell reg-select outputs to Reg Vector In
 170                 m.d.comb += rsv.src_rsel_i[i].eq(Cat(*src_rsel_o)),
 171                 # accumulate Reg-Sel Vector outputs
 172                 src_rsel.append(rsv.src_rsel_o[i])
 173
 174             # ... and output them from this module (horizontal, width=REGs)
 175             m.d.comb += self.src_rsel_o[i].eq(Cat(*src_rsel))
 176
 177         # ---
 178         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
 179         # ---
 180         for fu in range(self.n_fu_row):
 181             dc = dm[fu]
 182             # wire up inputs from module to row cell inputs (Cat is gooood)
 183             m.d.comb += [dc.dest_i.eq(self.dest_i),
 184                          dc.rd_pend_i.eq(self.rd_pend_i),
 185                          dc.wr_pend_i.eq(self.wr_pend_i),
 186                         ]
 187         # same for src
 188         for i in range(self.n_src):
 189             for fu in range(self.n_fu_row):
 190                 dc = dm[fu]
 191                 # wire up inputs from module to row cell inputs (Cat is gooood)
 192                 m.d.comb += dc.src_i[i].eq(self.src_i[i])
 193
 194         # accumulate rsel bits into read/write pending vectors.
 195         rd_pend_v = []
 196         wr_pend_v = []
 197         for fu in range(self.n_fu_row):
 198             dc = dm[fu]
 199             rd_pend_v.append(dc.v_rd_rsel_o)
 200             wr_pend_v.append(dc.v_wr_rsel_o)
 201         rd_v = GlobalPending(self.n_reg_col, rd_pend_v)
 202         wr_v = GlobalPending(self.n_reg_col, wr_pend_v)
 203         m.submodules.rd_v = rd_v
 204         m.submodules.wr_v = wr_v
 205
 206         m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o)
 207         m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o)
 208
 209         # ---
 210         # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
 211         # ---
 212         go_rd_i = []
 213         go_wr_i = []
 214         go_die_i = []
 215         issue_i = []
 216         for fu in range(self.n_fu_row):
 217             dc = dm[fu]
 218             # accumulate cell fwd outputs for dest/src1/src2
 219             go_rd_i.append(dc.go_rd_i)
 220             go_wr_i.append(dc.go_wr_i)
 221             go_die_i.append(dc.go_die_i)
 222             issue_i.append(dc.issue_i)
 223         # wire up inputs from module to row cell inputs (Cat is gooood)
 224         m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
 225                      Cat(*go_wr_i).eq(self.go_wr_i),
 226                      Cat(*go_die_i).eq(self.go_die_i),
 227                      Cat(*issue_i).eq(self.issue_i),
 228                     ]
 229
 230         return m
 231
 232     def __iter__(self):
 233         yield self.dest_i
 234         yield from self.src_i
 235         yield self.issue_i
 236         yield self.go_wr_i
 237         yield self.go_rd_i
 238         yield self.go_die_i
 239         yield self.dest_rsel_o
 240         yield from self.src_rsel_o
 241         yield self.wr_pend_o
 242         yield self.rd_pend_o
 243         yield self.wr_pend_i
 244         yield self.rd_pend_i
 245         yield self.v_wr_rsel_o
 246         yield self.v_rd_rsel_o
 247         yield from self.rd_src_pend_o
 248
 249     def ports(self):
 250         return list(self)
 251
 252 def d_matrix_sim(dut):
 253     """ XXX TODO
 254     """
 255     yield dut.dest_i.eq(1)
 256     yield dut.issue_i.eq(1)
 257     yield
 258     yield dut.issue_i.eq(0)
 259     yield
 260     yield dut.src1_i.eq(1)
 261     yield dut.issue_i.eq(1)
 262     yield
 263     yield dut.issue_i.eq(0)
 264     yield
 265     yield dut.go_rd_i.eq(1)
 266     yield
 267     yield dut.go_rd_i.eq(0)
 268     yield
 269     yield dut.go_wr_i.eq(1)
 270     yield
 271     yield dut.go_wr_i.eq(0)
 272     yield
 273
 274 def test_d_matrix():
 275     dut = FURegDepMatrix(n_fu_row=3, n_reg_col=4, n_src=2)
 276     vl = rtlil.convert(dut, ports=dut.ports())
 277     with open("test_fu_reg_matrix.il", "w") as f:
 278         f.write(vl)
 279
 280     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_reg_matrix.vcd')
 281
 282 if __name__ == '__main__':
 283     test_d_matrix()