src/scoreboard/ldst_dep_cell.py

   1 """ Mitch Alsup 6600-style LD/ST scoreboard Dependency Cell
   2
   3 Relevant bugreports:
   4 * http://bugs.libre-riscv.org/show_bug.cgi?id=81
   5
   6 """
   7
   8 from nmigen.compat.sim import run_simulation
   9 from nmigen.cli import verilog, rtlil
  10 from nmigen import Module, Signal, Repl, Elaboratable
  11 from nmutil.latch import SRLatch
  12
  13
  14 class LDSTDepCell(Elaboratable):
  15     """ implements 11.4.12 mitch alsup load/store dependence cell, p45
  16     """
  17     def __init__(self, n_ls=1):
  18         self.n_ls = n_ls
  19         # inputs
  20         self.load_i = Signal(n_ls, reset_less=True)     # load pend in (top)
  21         self.stor_i = Signal(n_ls, reset_less=True)     # store pend in (top)
  22         self.issue_i = Signal(reset_less=True)    # Issue in (top)
  23         self.go_die_i = Signal(reset_less=True)    # Issue in (top)
  24
  25         # load / store hit - basically connect these to go_wr from LD/STCompUnit
  26         # LD.go_wr -> load_hit_i, ST.go_wr -> stwd_hit_i.
  27         self.load_hit_i = Signal(n_ls, reset_less=True) # ld hit in (right)
  28         self.stwd_hit_i = Signal(n_ls, reset_less=True) # st w/ hit in (right)
  29
  30         # outputs (latched rd/wr pend)
  31         self.ld_hold_st_o = Signal(n_ls, reset_less=True) # ld holds st out (l)
  32         self.st_hold_ld_o = Signal(n_ls, reset_less=True) # st holds ld out (l)
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36         m.submodules.war_l = war_l = SRLatch(sync=False, llen=self.n_ls) # WaR
  37         m.submodules.raw_l = raw_l = SRLatch(sync=False, llen=self.n_ls) # RaW
  38
  39         # temporaries (repeat-extend)
  40         issue = Repl(self.issue_i, self.n_ls)
  41         die = Repl(self.go_die_i, self.n_ls)
  42
  43         # issue & store & load - used for both WAR and RAW Setting
  44         i_s_l = Signal(reset_less=True)
  45         m.d.comb += i_s_l.eq(issue & self.stor_i & self.load_i)
  46
  47         # write after read latch: loads block stores
  48         m.d.comb += war_l.s.eq(i_s_l)
  49         m.d.comb += war_l.r.eq(die | self.load_i) # reset on LD
  50
  51         # read after write latch: stores block loads
  52         m.d.comb += raw_l.s.eq(i_s_l)
  53         m.d.comb += raw_l.r.eq(die | self.stor_i) # reset on ST
  54
  55         # Hold results (read out horizontally, accumulate in OR fashion)
  56         m.d.comb += self.ld_hold_st_o.eq(war_l.qn & self.load_hit_i)
  57         m.d.comb += self.st_hold_ld_o.eq(raw_l.qn & self.stwd_hit_i)
  58
  59         return m
  60
  61     def __iter__(self):
  62         yield self.load_i
  63         yield self.stor_i
  64         yield self.issue_i
  65         yield self.load_hit_i
  66         yield self.stwd_hit_i
  67         yield self.ld_hold_st_o
  68         yield self.st_hold_ld_o
  69
  70     def ports(self):
  71         return list(self)
  72
  73
  74 def dcell_sim(dut):
  75     yield dut.dest_i.eq(1)
  76     yield dut.issue_i.eq(1)
  77     yield
  78     yield dut.issue_i.eq(0)
  79     yield
  80     yield dut.src1_i.eq(1)
  81     yield dut.issue_i.eq(1)
  82     yield
  83     yield dut.issue_i.eq(0)
  84     yield
  85     yield dut.go_rd_i.eq(1)
  86     yield
  87     yield dut.go_rd_i.eq(0)
  88     yield
  89     yield dut.go_wr_i.eq(1)
  90     yield
  91     yield dut.go_wr_i.eq(0)
  92     yield
  93
  94 def test_dcell():
  95     dut = LDSTDepCell()
  96     vl = rtlil.convert(dut, ports=dut.ports())
  97     with open("test_ldst_dcell.il", "w") as f:
  98         f.write(vl)
  99
 100     run_simulation(dut, dcell_sim(dut), vcd_name='test_ldst_dcell.vcd')
 101
 102 if __name__ == '__main__':
 103     test_dcell()