src/soc/bus/test/test_sram_wishbone.py

   1 """demonstration of nmigen-soc SRAM behind a wishbone bus
   2 Bugs:
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=382
   4 """
   5 from nmigen_soc.wishbone.sram import SRAM
   6 from nmigen import Memory, Signal, Module
   7
   8 memory = Memory(width=64, depth=16)
   9 sram = SRAM(memory=memory, granularity=16)
  10
  11 # valid wishbone signals include
  12 # sram.bus.adr
  13 # sram.bus.dat_w
  14 # sram.bus.dat_r
  15 # sram.bus.sel
  16 # sram.bus.cyc
  17 # sram.bus.stb
  18 # sram.bus.we
  19 # sram.bus.ack
  20
  21 # setup simulation
  22 from nmigen.back.pysim import Simulator, Delay, Settle
  23 m = Module()
  24 m.submodules.sram = sram
  25 sim = Simulator(m)
  26 sim.add_clock(1e-6)
  27
  28 def print_sig(sig, format=None):
  29     if format == None:
  30         print(f"{sig.__repr__()} = {(yield sig)}")
  31     if format == "h":
  32         print(f"{sig.__repr__()} = {hex((yield sig))}")
  33
  34 def process():
  35     # enable necessary signals for write
  36     for en in range(4):
  37         yield sram.bus.sel[en].eq(1)
  38     yield sram.bus.we.eq(1)
  39     yield sram.bus.cyc.eq(1)
  40     yield sram.bus.stb.eq(1)
  41
  42     # put data and address on bus
  43     yield sram.bus.adr.eq(0x4)
  44     yield sram.bus.dat_w.eq(0xdeadbeef)
  45     yield
  46
  47     # set necessary signal to read bus
  48     # at address 0
  49     yield sram.bus.we.eq(0)
  50     yield sram.bus.adr.eq(0)
  51     yield sram.bus.cyc.eq(1)
  52     yield sram.bus.stb.eq(1)
  53     yield
  54
  55     # see sync_behaviors.py
  56     # for why we need Settle()
  57     # debug print the bus address/data
  58     yield Settle()
  59     yield from print_sig(sram.bus.adr)
  60     yield from print_sig(sram.bus.dat_r, "h")
  61
  62     # check the result
  63     data = yield sram.bus.dat_r
  64     assert data == 0
  65
  66     # set necessary signal to read bus
  67     # at address 4
  68     yield sram.bus.we.eq(0)
  69     yield sram.bus.adr.eq(0x4)
  70     yield sram.bus.cyc.eq(1)
  71     yield sram.bus.stb.eq(1)
  72     yield
  73
  74     # see sync_behaviors.py
  75     # for why we need Settle()
  76     # debug print the bus address/data
  77     yield Settle()
  78     yield from print_sig(sram.bus.adr)
  79     yield from print_sig(sram.bus.dat_r, "h")
  80
  81     # check the result
  82     data = yield sram.bus.dat_r
  83     assert data == 0xdeadbeef
  84
  85     # disable signals
  86     yield sram.bus.cyc.eq(0)
  87     yield sram.bus.stb.eq(0)
  88     yield
  89
  90 sim_writer = sim.write_vcd(f"{__file__[:-3]}.vcd")
  91
  92 with sim_writer:
  93     sim.add_sync_process(process)
  94     sim.run()