src/soc/clock/dummypll.py

   1 """a Dummy PLL module to be replaced by a real one
   2 """
   3
   4 from nmigen import (Module, Signal, Elaboratable, Const, Cat)
   5 from nmigen.cli import rtlil
   6
   7 class DummyPLL(Elaboratable):
   8     def __init__(self):
   9         self.clk_24_i = Signal(name="ref", reset_less=True) # external incoming
  10         self.sel_a0_i = Signal(name="a0", reset_less=True) # PLL selection
  11         self.sel_a1_i = Signal(name="a1", reset_less=True) # PLL selection
  12         self.clk_pll_o = Signal(name="out", reset_less=True)  # output clock
  13         self.pll_18_o = Signal(name="div_out_test", reset_less=True)  # test out
  14         self.pll_ana_o = Signal(name="vco_test_ana", reset_less=True) # analog
  15
  16     def elaborate(self, platform):
  17         m = Module()
  18         m.d.comb += self.clk_pll_o.eq(self.clk_24_i) # just pass through
  19         # just get something, stops yosys destroying (optimising) these out
  20         with m.If((~self.sel_a0_i) & (~self.sel_a1_i)):
  21             m.d.comb += self.pll_ana_o.eq(self.clk_24_i)
  22             m.d.comb += self.pll_18_o.eq(~self.clk_24_i)
  23
  24         #self.attrs['blackbox'] = 1
  25
  26         return m
  27
  28     def ports(self):
  29         return [self.clk_24_i, self.sel_a0_i, self.sel_a1_i, self.clk_pll_o,
  30                 self.pll_18_o, self.pll_ana_o]
  31
  32
  33 if __name__ == '__main__':
  34     dut = DummyPLL()
  35
  36     vl = rtlil.convert(dut, ports=dut.ports())
  37     with open("test_dummy_pll.il", "w") as f:
  38         f.write(vl)
  39