src/soc/debug/test/test_jtag_tap_srv.py

   1 """DMI 2 JTAG test
   2
   3 based on Staf Verhaegen (Chips4Makers) wishbone TAP
   4 """
   5
   6 import sys
   7 from nmigen import (Module, Signal, Elaboratable, Const)
   8 from c4m.nmigen.jtag.tap import TAP, IOType
   9 from c4m.nmigen.jtag.bus import Interface as JTAGInterface
  10 from soc.debug.dmi import DMIInterface, DBGCore
  11 from soc.debug.test.dmi_sim import dmi_sim
  12 from soc.debug.jtag import JTAG
  13 from soc.debug.test.jtagremote import JTAGServer, JTAGClient
  14
  15 from nmigen_soc.wishbone.sram import SRAM
  16 from nmigen import Memory, Signal, Module
  17
  18 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
  19 from nmutil.util import wrap
  20 from soc.debug.jtagutils import (jtag_read_write_reg,
  21                                  jtag_srv, jtag_set_reset,
  22                                  jtag_set_ir, jtag_set_get_dr)
  23
  24 def test_pinset():
  25     return {
  26             # in, out, tri-out, tri-inout
  27             'test': ['io0-', 'io1+', 'io2>', 'io3*'],
  28            }
  29
  30
  31 # JTAG-ircodes for accessing DMI
  32 DMI_ADDR = 8
  33 DMI_READ = 9
  34 DMI_WRRD = 10
  35
  36 # JTAG-ircodes for accessing Wishbone
  37 WB_ADDR = 5
  38 WB_READ = 6
  39 WB_WRRD = 7
  40
  41 # JTAG boundary scan reg addresses
  42 BS_EXTEST = 0
  43 BS_INTEST = 0
  44 BS_SAMPLE = 2
  45 BS_PRELOAD = 2
  46
  47
  48 def jtag_sim(dut, srv_dut):
  49
  50     ####### JTAGy stuff (IDCODE) ######
  51
  52     # read idcode
  53     yield from jtag_set_reset(dut)
  54     idcode = yield from jtag_read_write_reg(dut, 0b1, 32)
  55     print ("idcode", hex(idcode))
  56     assert idcode == 0x18ff
  57
  58     ####### JTAG Boundary scan ######
  59
  60     bslen = dut.scan_len
  61     print ("scan len", bslen)
  62
  63     # sample test
  64     bs_actual = 0b100110
  65     yield srv_dut.ios[0].pad.i.eq(1)
  66     yield srv_dut.ios[1].core.o.eq(0)
  67     yield srv_dut.ios[2].core.o.eq(1)
  68     yield srv_dut.ios[2].core.oe.eq(1)
  69     yield srv_dut.ios[3].pad.i.eq(0)
  70     yield srv_dut.ios[3].core.o.eq(0)
  71     yield srv_dut.ios[3].core.oe.eq(1)
  72     yield
  73
  74     bs = yield from jtag_read_write_reg(dut, BS_SAMPLE, bslen, bs_actual)
  75     print ("bs scan", bin(bs))
  76     yield
  77
  78     print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
  79     print ("io1 core.o", (yield srv_dut.ios[1].core.o))
  80     print ("io2 core.o", (yield srv_dut.ios[2].core.o))
  81     print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
  82     print ("io3 core.i", (yield srv_dut.ios[3].core.i))
  83     print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
  84     print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
  85
  86     # extest
  87     ir_actual = yield from jtag_set_ir(dut, BS_EXTEST)
  88     print ("ir extest", bin(ir_actual))
  89     yield
  90
  91     print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
  92     print ("io1 core.o", (yield srv_dut.ios[1].core.o))
  93     print ("io2 core.o", (yield srv_dut.ios[2].core.o))
  94     print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
  95     print ("io3 core.i", (yield srv_dut.ios[3].core.i))
  96     print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
  97     print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
  98
  99     # set pins
 100     bs_actual = 0b1011001
 101     yield srv_dut.ios[0].pad.i.eq(0)
 102     yield srv_dut.ios[1].core.o.eq(1)
 103     yield srv_dut.ios[2].core.o.eq(0)
 104     yield srv_dut.ios[2].core.oe.eq(0)
 105     yield srv_dut.ios[3].pad.i.eq(1)
 106     yield srv_dut.ios[3].core.o.eq(1)
 107     yield srv_dut.ios[3].core.oe.eq(0)
 108     yield
 109
 110     bs = yield from jtag_set_get_dr(dut, bslen, bs_actual)
 111     print ("bs scan", bin(bs))
 112     yield
 113
 114     print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
 115     print ("io1 core.o", (yield srv_dut.ios[1].core.o))
 116     print ("io2 core.o", (yield srv_dut.ios[2].core.o))
 117     print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
 118     print ("io3 core.i", (yield srv_dut.ios[3].core.i))
 119     print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
 120     print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
 121
 122     # reset
 123     yield from jtag_set_reset(dut)
 124     print ("bs reset")
 125     yield
 126
 127     print ("io0 pad.i", (yield srv_dut.ios[0].pad.i))
 128     print ("io1 core.o", (yield srv_dut.ios[1].core.o))
 129     print ("io2 core.o", (yield srv_dut.ios[2].core.o))
 130     print ("io2 core.oe", (yield srv_dut.ios[2].core.oe))
 131     print ("io3 core.i", (yield srv_dut.ios[3].core.i))
 132     print ("io3 pad.o", (yield srv_dut.ios[3].pad.o))
 133     print ("io3 pad.oe", (yield srv_dut.ios[3].pad.oe))
 134
 135     ####### JTAG to DMI ######
 136
 137     # write DMI address
 138     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.CTRL)
 139
 140     # read DMI CTRL register
 141     status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
 142     print ("dmi ctrl status", hex(status))
 143     assert status == 4
 144
 145     # write DMI address
 146     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, 0)
 147
 148     # write DMI CTRL register
 149     status = yield from jtag_read_write_reg(dut, DMI_WRRD, 64, 0b101)
 150     print ("dmi ctrl status", hex(status))
 151     assert status == 4 # returned old value (nice! cool feature!)
 152
 153     # write DMI address
 154     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.CTRL)
 155
 156     # read DMI CTRL register
 157     status = yield from jtag_read_write_reg(dut, DMI_READ, 64)
 158     print ("dmi ctrl status", hex(status))
 159     assert status == 0
 160
 161     # write DMI MSR address
 162     yield from jtag_read_write_reg(dut, DMI_ADDR, 8, DBGCore.MSR)
 163
 164     # read DMI MSR register
 165     msr = yield from jtag_read_write_reg(dut, DMI_READ, 64)
 166     print ("dmi msr", hex(msr))
 167     assert msr == 0xdeadbeef
 168
 169     ####### JTAG to Wishbone ######
 170
 171     # write Wishbone address
 172     yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
 173
 174     # write/read wishbone data
 175     data = yield from jtag_read_write_reg(dut, WB_WRRD, 64, 0xfeef)
 176     print ("wb write", hex(data))
 177
 178     # write Wishbone address
 179     yield from jtag_read_write_reg(dut, WB_ADDR, 64, 0x18)
 180
 181     # write/read wishbone data
 182     data = yield from jtag_read_write_reg(dut, WB_READ, 64, 0)
 183     print ("wb read", hex(data))
 184
 185     ####### done - tell dmi_sim to stop (otherwise it won't) ########
 186
 187     srv_dut.stop = True
 188     print ("jtag sim stopping")
 189
 190
 191 if __name__ == '__main__':
 192     dut = JTAG(test_pinset(), wb_data_wid=64)
 193     dut.stop = False
 194
 195     # rather than the client access the JTAG bus directly
 196     # create an alternative that the client sets
 197     class Dummy: pass
 198     cdut = Dummy()
 199     cdut.cbus = JTAGInterface()
 200
 201     # set up client-server on port 44843-something
 202     dut.s = JTAGServer()
 203     if len(sys.argv) != 2 or sys.argv[1] != 'server':
 204         cdut.c = JTAGClient()
 205         dut.s.get_connection()
 206     else:
 207         dut.s.get_connection(None) # block waiting for connection
 208
 209     # take copy of ir_width and scan_len
 210     cdut._ir_width = dut._ir_width
 211     cdut.scan_len = dut.scan_len
 212
 213     memory = Memory(width=64, depth=16)
 214     sram = SRAM(memory=memory, bus=dut.wb)
 215
 216     m = Module()
 217     m.submodules.ast = dut
 218     m.submodules.sram = sram
 219
 220     sim = Simulator(m)
 221     sim.add_clock(1e-6, domain="sync")      # standard clock
 222
 223     sim.add_sync_process(wrap(jtag_srv(dut))) # jtag server
 224     if len(sys.argv) != 2 or sys.argv[1] != 'server':
 225         sim.add_sync_process(wrap(jtag_sim(cdut, dut))) # actual jtag tester
 226     else:
 227         print ("running server only as requested, use openocd remote to test")
 228     sim.add_sync_process(wrap(dmi_sim(dut)))  # handles (pretends to be) DMI
 229
 230     with sim.write_vcd("dmi2jtag_test_srv.vcd"):
 231         sim.run()