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[soc.git] / src / soc / decoder / isa / caller.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2020 Michael Nolan
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=424
14 """
15
16 from nmigen.back.pysim import Settle
17 from functools import wraps
18 from copy import copy
19 from soc.decoder.orderedset import OrderedSet
20 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
21 selectconcat)
22 from soc.decoder.power_enums import (spr_dict, spr_byname, XER_bits,
23 insns, MicrOp, In1Sel, In2Sel, In3Sel,
24 OutSel, CROutSel)
25
26 from soc.decoder.power_enums import SPR as DEC_SPR
27
28 from soc.decoder.helpers import exts, gtu, ltu, undefined
29 from soc.consts import PIb, MSRb # big-endian (PowerISA versions)
30 from soc.decoder.power_svp64 import SVP64RM, decode_extra
31
32 from collections import namedtuple
33 import math
34 import sys
35
36 instruction_info = namedtuple('instruction_info',
37 'func read_regs uninit_regs write_regs ' +
38 'special_regs op_fields form asmregs')
39
40 special_sprs = {
41 'LR': 8,
42 'CTR': 9,
43 'TAR': 815,
44 'XER': 1,
45 'VRSAVE': 256}
46
47
48 def swap_order(x, nbytes):
49 x = x.to_bytes(nbytes, byteorder='little')
50 x = int.from_bytes(x, byteorder='big', signed=False)
51 return x
52
53
54 REG_SORT_ORDER = {
55 # TODO (lkcl): adjust other registers that should be in a particular order
56 # probably CA, CA32, and CR
57 "RT": 0,
58 "RA": 0,
59 "RB": 0,
60 "RS": 0,
61 "CR": 0,
62 "LR": 0,
63 "CTR": 0,
64 "TAR": 0,
65 "CA": 0,
66 "CA32": 0,
67 "MSR": 0,
68
69 "overflow": 1,
70 }
71
72
73 def create_args(reglist, extra=None):
74 retval = list(OrderedSet(reglist))
75 retval.sort(key=lambda reg: REG_SORT_ORDER[reg])
76 if extra is not None:
77 return [extra] + retval
78 return retval
79
80
81 # very quick, TODO move to SelectableInt utils later
82 def genmask(shift, size):
83 res = SelectableInt(0, size)
84 for i in range(size):
85 if i < shift:
86 res[size-1-i] = SelectableInt(1, 1)
87 return res
88
89 """
90 Get Root Page
91
92 //Accessing 2nd double word of partition table (pate1)
93 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
94 // PTCR Layout
95 // ====================================================
96 // -----------------------------------------------
97 // | /// | PATB | /// | PATS |
98 // -----------------------------------------------
99 // 0 4 51 52 58 59 63
100 // PATB[4:51] holds the base address of the Partition Table,
101 // right shifted by 12 bits.
102 // This is because the address of the Partition base is
103 // 4k aligned. Hence, the lower 12bits, which are always
104 // 0 are ommitted from the PTCR.
105 //
106 // Thus, The Partition Table Base is obtained by (PATB << 12)
107 //
108 // PATS represents the partition table size right-shifted by 12 bits.
109 // The minimal size of the partition table is 4k.
110 // Thus partition table size = (1 << PATS + 12).
111 //
112 // Partition Table
113 // ====================================================
114 // 0 PATE0 63 PATE1 127
115 // |----------------------|----------------------|
116 // | | |
117 // |----------------------|----------------------|
118 // | | |
119 // |----------------------|----------------------|
120 // | | | <-- effLPID
121 // |----------------------|----------------------|
122 // .
123 // .
124 // .
125 // |----------------------|----------------------|
126 // | | |
127 // |----------------------|----------------------|
128 //
129 // The effective LPID forms the index into the Partition Table.
130 //
131 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
132 // corresponding to that partition.
133 //
134 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
135 //
136 // PATE0 Layout
137 // -----------------------------------------------
138 // |1|RTS1|/| RPDB | RTS2 | RPDS |
139 // -----------------------------------------------
140 // 0 1 2 3 4 55 56 58 59 63
141 //
142 // HR[0] : For Radix Page table, first bit should be 1.
143 // RTS1[1:2] : Gives one fragment of the Radix treesize
144 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
145 // RTS = (RTS1 << 3 + RTS2) + 31.
146 //
147 // RPDB[4:55] = Root Page Directory Base.
148 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
149 // Thus, Root page directory size = 1 << (RPDS + 3).
150 // Note: RPDS >= 5.
151 //
152 // PATE1 Layout
153 // -----------------------------------------------
154 // |///| PRTB | // | PRTS |
155 // -----------------------------------------------
156 // 0 3 4 51 52 58 59 63
157 //
158 // PRTB[4:51] = Process Table Base. This is aligned to size.
159 // PRTS[59: 63] = Process Table Size right shifted by 12.
160 // Minimal size of the process table is 4k.
161 // Process Table Size = (1 << PRTS + 12).
162 // Note: PRTS <= 24.
163 //
164 // Computing the size aligned Process Table Base:
165 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
166 // Thus, the lower 12+PRTS bits of table_base will
167 // be zero.
168
169
170 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
171 //
172 // Process Table
173 // ==========================
174 // 0 PRTE0 63 PRTE1 127
175 // |----------------------|----------------------|
176 // | | |
177 // |----------------------|----------------------|
178 // | | |
179 // |----------------------|----------------------|
180 // | | | <-- effPID
181 // |----------------------|----------------------|
182 // .
183 // .
184 // .
185 // |----------------------|----------------------|
186 // | | |
187 // |----------------------|----------------------|
188 //
189 // The effective Process id (PID) forms the index into the Process Table.
190 //
191 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
192 // corresponding to that process
193 //
194 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
195 //
196 // PRTE0 Layout
197 // -----------------------------------------------
198 // |/|RTS1|/| RPDB | RTS2 | RPDS |
199 // -----------------------------------------------
200 // 0 1 2 3 4 55 56 58 59 63
201 //
202 // RTS1[1:2] : Gives one fragment of the Radix treesize
203 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
204 // RTS = (RTS1 << 3 + RTS2) << 31,
205 // since minimal Radix Tree size is 4G.
206 //
207 // RPDB = Root Page Directory Base.
208 // RPDS = Root Page Directory Size right shifted by 3.
209 // Thus, Root page directory size = RPDS << 3.
210 // Note: RPDS >= 5.
211 //
212 // PRTE1 Layout
213 // -----------------------------------------------
214 // | /// |
215 // -----------------------------------------------
216 // 0 63
217 // All bits are reserved.
218
219
220 """
221
222 # see qemu/target/ppc/mmu-radix64.c for reference
223 class RADIX:
224 def __init__(self, mem, caller):
225 self.mem = mem
226 self.caller = caller
227
228 # cached page table stuff
229 self.pgtbl0 = 0
230 self.pt0_valid = False
231 self.pgtbl3 = 0
232 self.pt3_valid = False
233
234 def __call__(self,*args, **kwargs):
235 print("TODO: implement RADIX.__call__()")
236 print(args)
237 print(kwargs)
238 return None
239
240 def ld(self, address, width=8, swap=True, check_in_mem=False):
241 print("RADIX: ld from addr 0x%x width %d" % (address, width))
242 dsisr = self.caller.spr[DEC_SPR.DSISR.value]
243 dar = self.caller.spr[DEC_SPR.DAR.value]
244 pidr = self.caller.spr[DEC_SPR.PIDR.value]
245 prtbl = self.caller.spr[DEC_SPR.PRTBL.value]
246
247 pte = self._walk_tree()
248 # use pte to caclculate phys address
249 return self.mem.ld(address, width, swap, check_in_mem)
250
251 # XXX set SPRs on error
252
253 # TODO implement
254 def st(self, addr, v, width=8, swap=True):
255 print("RADIX: st to addr 0x%x width %d data %x" % (addr, width, v))
256 dsisr = self.caller.spr[DEC_SPR.DSISR.value]
257 dar = self.caller.spr[DEC_SPR.DAR.value]
258 pidr = self.caller.spr[DEC_SPR.PIDR.value]
259 prtbl = self.caller.spr[DEC_SPR.PRTBL.value]
260
261 # use pte to caclculate phys address (addr)
262 return self.mem.st(addr, v, width, swap)
263
264 # XXX set SPRs on error
265
266 def memassign(self, addr, sz, val):
267 print("memassign", addr, sz, val)
268 self.st(addr.value, val.value, sz, swap=False)
269
270 def _next_level(self):
271 return True
272 ## DSISR_R_BADCONFIG
273 ## read_entry
274 ## DSISR_NOPTE
275 ## Prepare for next iteration
276
277 def _walk_tree(self):
278 """walk tree
279
280 // vaddr 64 Bit
281 // vaddr |-----------------------------------------------------|
282 // | Unused | Used |
283 // |-----------|-----------------------------------------|
284 // | 0000000 | usefulBits = X bits (typically 52) |
285 // |-----------|-----------------------------------------|
286 // | |<--Cursize---->| |
287 // | | Index | |
288 // | | into Page | |
289 // | | Directory | |
290 // |-----------------------------------------------------|
291 // | |
292 // V |
293 // PDE |---------------------------| |
294 // |V|L|//| NLB |///|NLS| |
295 // |---------------------------| |
296 // PDE = Page Directory Entry |
297 // [0] = V = Valid Bit |
298 // [1] = L = Leaf bit. If 0, then |
299 // [4:55] = NLB = Next Level Base |
300 // right shifted by 8 |
301 // [59:63] = NLS = Next Level Size |
302 // | NLS >= 5 |
303 // | V
304 // | |--------------------------|
305 // | | usfulBits = X-Cursize |
306 // | |--------------------------|
307 // |---------------------><--NLS-->| |
308 // | Index | |
309 // | into | |
310 // | PDE | |
311 // |--------------------------|
312 // |
313 // If the next PDE obtained by |
314 // (NLB << 8 + 8 * index) is a |
315 // nonleaf, then repeat the above. |
316 // |
317 // If the next PDE is a leaf, |
318 // then Leaf PDE structure is as |
319 // follows |
320 // |
321 // |
322 // Leaf PDE |
323 // |------------------------------| |----------------|
324 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
325 // |------------------------------| |----------------|
326 // [0] = V = Valid Bit |
327 // [1] = L = Leaf Bit = 1 if leaf |
328 // PDE |
329 // [2] = Sw = Sw bit 0. |
330 // [7:51] = RPN = Real Page Number, V
331 // real_page = RPN << 12 -------------> Logical OR
332 // [52:54] = Sw Bits 1:3 |
333 // [55] = R = Reference |
334 // [56] = C = Change V
335 // [58:59] = Att = Physical Address
336 // 0b00 = Normal Memory
337 // 0b01 = SAO
338 // 0b10 = Non Idenmpotent
339 // 0b11 = Tolerant I/O
340 // [60:63] = Encoded Access
341 // Authority
342 //
343 """
344 # walk tree starts on prtbl
345 while True:
346 ret = self._next_level()
347 if ret: return ret
348
349 def _decode_prte(self, data):
350 """PRTE0 Layout
351 -----------------------------------------------
352 |/|RTS1|/| RPDB | RTS2 | RPDS |
353 -----------------------------------------------
354 0 1 2 3 4 55 56 58 59 63
355 """
356 # note that SelectableInt does big-endian! so the indices
357 # below *directly* match the spec, unlike microwatt which
358 # has to turn them around (to LE)
359 zero = SelectableInt(0, 1)
360 rts = selectconcat(zero,
361 data[56:59], # RTS2
362 data[1:3], # RTS1
363 )
364 masksize = data[59:64] # RPDS
365 mbits = selectconcat(zero, masksize)
366 pgbase = selectconcat(data[8:56], # part of RPDB
367 SelectableInt(0, 16),)
368
369 return (rts, mbits, pgbase)
370
371 def _segment_check(self, addr, mbits, shift):
372 """checks segment valid
373 mbits := '0' & r.mask_size;
374 v.shift := r.shift + (31 - 12) - mbits;
375 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
376 if r.addr(63) /= r.addr(62) or nonzero = '1' then
377 v.state := RADIX_FINISH;
378 v.segerror := '1';
379 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
380 v.state := RADIX_FINISH;
381 v.badtree := '1';
382 else
383 v.state := RADIX_LOOKUP;
384 """
385 # note that SelectableInt does big-endian! so the indices
386 # below *directly* match the spec, unlike microwatt which
387 # has to turn them around (to LE)
388 mask = genmask(shift, 44)
389 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
390 print ("RADIX _segment_check nonzero", bin(nonzero.value))
391 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
392 if addr[0] != addr[1] or nonzero == 1:
393 return "segerror"
394 limit = shift + (31 - 12)
395 if mbits < 5 or mbits > 16 or mbits > limit:
396 return "badtree"
397 new_shift = shift + (31 - 12) - mbits
398 return new_shift
399
400 def _check_perms(self):
401 """check page permissions
402 -- test leaf bit
403 if data(62) = '1' then
404 -- check permissions and RC bits
405 perm_ok := '0';
406 if r.priv = '1' or data(3) = '0' then
407 if r.iside = '0' then
408 perm_ok := data(1) or (data(2) and not r.store);
409 else
410 -- no IAMR, so no KUEP support for now
411 -- deny execute permission if cache inhibited
412 perm_ok := data(0) and not data(5);
413 end if;
414 end if;
415 rc_ok := data(8) and (data(7) or not r.store);
416 if perm_ok = '1' and rc_ok = '1' then
417 v.state := RADIX_LOAD_TLB;
418 else
419 v.state := RADIX_FINISH;
420 v.perm_err := not perm_ok;
421 -- permission error takes precedence over RC error
422 v.rc_error := perm_ok;
423 end if;
424 """
425
426 def _get_prtable_addr(self, shift, prtbl, addr, pid):
427 """
428 if r.addr(63) = '1' then
429 effpid := x"00000000";
430 else
431 effpid := r.pid;
432 end if;
433 x"00" & r.prtbl(55 downto 36) &
434 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
435 (effpid(31 downto 8) and finalmask(23 downto 0))) &
436 effpid(7 downto 0) & "0000";
437 """
438 finalmask = genmask(shift, 44)
439 finalmask24 = finalmask[20:44]
440 if addr[0].value == 1:
441 effpid = SelectableInt(0, 32)
442 else:
443 effpid = self.pid[32:64] # TODO, check on this
444 zero16 = SelectableInt(0, 16)
445 zero4 = SelectableInt(0, 4)
446 rts = selectconcat(zero16,
447 prtbl[8:28], #
448 (prtbl[28:52] & ~finalmask24) | #
449 (effpid[0:24] & finalmask24), #
450 effpid[24:32],
451 zero4
452 )
453 def _get_pgtable_addr(self):
454 """
455 x"00" & r.pgbase(55 downto 19) &
456 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
457 "000";
458 """
459
460 def _get_pte(self):
461 """
462 x"00" &
463 ((r.pde(55 downto 12) and not finalmask) or
464 (r.addr(55 downto 12) and finalmask))
465 & r.pde(11 downto 0);
466 """
467
468
469 class Mem:
470
471 def __init__(self, row_bytes=8, initial_mem=None):
472 self.mem = {}
473 self.bytes_per_word = row_bytes
474 self.word_log2 = math.ceil(math.log2(row_bytes))
475 print("Sim-Mem", initial_mem, self.bytes_per_word, self.word_log2)
476 if not initial_mem:
477 return
478
479 # different types of memory data structures recognised (for convenience)
480 if isinstance(initial_mem, list):
481 initial_mem = (0, initial_mem)
482 if isinstance(initial_mem, tuple):
483 startaddr, mem = initial_mem
484 initial_mem = {}
485 for i, val in enumerate(mem):
486 initial_mem[startaddr + row_bytes*i] = (val, row_bytes)
487
488 for addr, (val, width) in initial_mem.items():
489 #val = swap_order(val, width)
490 self.st(addr, val, width, swap=False)
491
492 def _get_shifter_mask(self, wid, remainder):
493 shifter = ((self.bytes_per_word - wid) - remainder) * \
494 8 # bits per byte
495 # XXX https://bugs.libre-soc.org/show_bug.cgi?id=377
496 # BE/LE mode?
497 shifter = remainder * 8
498 mask = (1 << (wid * 8)) - 1
499 print("width,rem,shift,mask", wid, remainder, hex(shifter), hex(mask))
500 return shifter, mask
501
502 # TODO: Implement ld/st of lesser width
503 def ld(self, address, width=8, swap=True, check_in_mem=False):
504 print("ld from addr 0x{:x} width {:d}".format(address, width))
505 remainder = address & (self.bytes_per_word - 1)
506 address = address >> self.word_log2
507 assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
508 if address in self.mem:
509 val = self.mem[address]
510 elif check_in_mem:
511 return None
512 else:
513 val = 0
514 print("mem @ 0x{:x} rem {:d} : 0x{:x}".format(address, remainder, val))
515
516 if width != self.bytes_per_word:
517 shifter, mask = self._get_shifter_mask(width, remainder)
518 print("masking", hex(val), hex(mask << shifter), shifter)
519 val = val & (mask << shifter)
520 val >>= shifter
521 if swap:
522 val = swap_order(val, width)
523 print("Read 0x{:x} from addr 0x{:x}".format(val, address))
524 return val
525
526 def st(self, addr, v, width=8, swap=True):
527 staddr = addr
528 remainder = addr & (self.bytes_per_word - 1)
529 addr = addr >> self.word_log2
530 print("Writing 0x{:x} to ST 0x{:x} "
531 "memaddr 0x{:x}/{:x}".format(v, staddr, addr, remainder, swap))
532 assert remainder & (width - 1) == 0, "Unaligned access unsupported!"
533 if swap:
534 v = swap_order(v, width)
535 if width != self.bytes_per_word:
536 if addr in self.mem:
537 val = self.mem[addr]
538 else:
539 val = 0
540 shifter, mask = self._get_shifter_mask(width, remainder)
541 val &= ~(mask << shifter)
542 val |= v << shifter
543 self.mem[addr] = val
544 else:
545 self.mem[addr] = v
546 print("mem @ 0x{:x}: 0x{:x}".format(addr, self.mem[addr]))
547
548 def __call__(self, addr, sz):
549 val = self.ld(addr.value, sz, swap=False)
550 print("memread", addr, sz, val)
551 return SelectableInt(val, sz*8)
552
553 def memassign(self, addr, sz, val):
554 print("memassign", addr, sz, val)
555 self.st(addr.value, val.value, sz, swap=False)
556
557
558 class GPR(dict):
559 def __init__(self, decoder, isacaller, svstate, regfile):
560 dict.__init__(self)
561 self.sd = decoder
562 self.isacaller = isacaller
563 self.svstate = svstate
564 for i in range(32):
565 self[i] = SelectableInt(regfile[i], 64)
566
567 def __call__(self, ridx):
568 return self[ridx]
569
570 def set_form(self, form):
571 self.form = form
572
573 def getz(self, rnum):
574 # rnum = rnum.value # only SelectableInt allowed
575 print("GPR getzero", rnum)
576 if rnum == 0:
577 return SelectableInt(0, 64)
578 return self[rnum]
579
580 def _get_regnum(self, attr):
581 getform = self.sd.sigforms[self.form]
582 rnum = getattr(getform, attr)
583 return rnum
584
585 def ___getitem__(self, attr):
586 """ XXX currently not used
587 """
588 rnum = self._get_regnum(attr)
589 offs = self.svstate.srcstep
590 print("GPR getitem", attr, rnum, "srcoffs", offs)
591 return self.regfile[rnum]
592
593 def dump(self):
594 for i in range(0, len(self), 8):
595 s = []
596 for j in range(8):
597 s.append("%08x" % self[i+j].value)
598 s = ' '.join(s)
599 print("reg", "%2d" % i, s)
600
601
602 class PC:
603 def __init__(self, pc_init=0):
604 self.CIA = SelectableInt(pc_init, 64)
605 self.NIA = self.CIA + SelectableInt(4, 64) # only true for v3.0B!
606
607 def update_nia(self, is_svp64):
608 increment = 8 if is_svp64 else 4
609 self.NIA = self.CIA + SelectableInt(increment, 64)
610
611 def update(self, namespace, is_svp64):
612 """updates the program counter (PC) by 4 if v3.0B mode or 8 if SVP64
613 """
614 self.CIA = namespace['NIA'].narrow(64)
615 self.update_nia(is_svp64)
616 namespace['CIA'] = self.CIA
617 namespace['NIA'] = self.NIA
618
619
620 # Simple-V: see https://libre-soc.org/openpower/sv
621 class SVP64State:
622 def __init__(self, init=0):
623 self.spr = SelectableInt(init, 32)
624 # fields of SVSTATE, see https://libre-soc.org/openpower/sv/sprs/
625 self.maxvl = FieldSelectableInt(self.spr, tuple(range(0,7)))
626 self.vl = FieldSelectableInt(self.spr, tuple(range(7,14)))
627 self.srcstep = FieldSelectableInt(self.spr, tuple(range(14,21)))
628 self.dststep = FieldSelectableInt(self.spr, tuple(range(21,28)))
629 self.subvl = FieldSelectableInt(self.spr, tuple(range(28,30)))
630 self.svstep = FieldSelectableInt(self.spr, tuple(range(30,32)))
631
632
633 # SVP64 ReMap field
634 class SVP64RMFields:
635 def __init__(self, init=0):
636 self.spr = SelectableInt(init, 24)
637 # SVP64 RM fields: see https://libre-soc.org/openpower/sv/svp64/
638 self.mmode = FieldSelectableInt(self.spr, [0])
639 self.mask = FieldSelectableInt(self.spr, tuple(range(1,4)))
640 self.elwidth = FieldSelectableInt(self.spr, tuple(range(4,6)))
641 self.ewsrc = FieldSelectableInt(self.spr, tuple(range(6,8)))
642 self.subvl = FieldSelectableInt(self.spr, tuple(range(8,10)))
643 self.extra = FieldSelectableInt(self.spr, tuple(range(10,19)))
644 self.mode = FieldSelectableInt(self.spr, tuple(range(19,24)))
645 # these cover the same extra field, split into parts as EXTRA2
646 self.extra2 = list(range(4))
647 self.extra2[0] = FieldSelectableInt(self.spr, tuple(range(10,12)))
648 self.extra2[1] = FieldSelectableInt(self.spr, tuple(range(12,14)))
649 self.extra2[2] = FieldSelectableInt(self.spr, tuple(range(14,16)))
650 self.extra2[3] = FieldSelectableInt(self.spr, tuple(range(16,18)))
651 self.smask = FieldSelectableInt(self.spr, tuple(range(16,19)))
652 # and here as well, but EXTRA3
653 self.extra3 = list(range(3))
654 self.extra3[0] = FieldSelectableInt(self.spr, tuple(range(10,13)))
655 self.extra3[1] = FieldSelectableInt(self.spr, tuple(range(13,16)))
656 self.extra3[2] = FieldSelectableInt(self.spr, tuple(range(16,19)))
657
658
659 SVP64RM_MMODE_SIZE = len(SVP64RMFields().mmode.br)
660 SVP64RM_MASK_SIZE = len(SVP64RMFields().mask.br)
661 SVP64RM_ELWIDTH_SIZE = len(SVP64RMFields().elwidth.br)
662 SVP64RM_EWSRC_SIZE = len(SVP64RMFields().ewsrc.br)
663 SVP64RM_SUBVL_SIZE = len(SVP64RMFields().subvl.br)
664 SVP64RM_EXTRA2_SPEC_SIZE = len(SVP64RMFields().extra2[0].br)
665 SVP64RM_EXTRA3_SPEC_SIZE = len(SVP64RMFields().extra3[0].br)
666 SVP64RM_SMASK_SIZE = len(SVP64RMFields().smask.br)
667 SVP64RM_MODE_SIZE = len(SVP64RMFields().mode.br)
668
669
670 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
671 class SVP64PrefixFields:
672 def __init__(self):
673 self.insn = SelectableInt(0, 32)
674 # 6 bit major opcode EXT001, 2 bits "identifying" (7, 9), 24 SV ReMap
675 self.major = FieldSelectableInt(self.insn, tuple(range(0,6)))
676 self.pid = FieldSelectableInt(self.insn, (7, 9)) # must be 0b11
677 rmfields = [6, 8] + list(range(10,32)) # SVP64 24-bit RM (ReMap)
678 self.rm = FieldSelectableInt(self.insn, rmfields)
679
680
681 SV64P_MAJOR_SIZE = len(SVP64PrefixFields().major.br)
682 SV64P_PID_SIZE = len(SVP64PrefixFields().pid.br)
683 SV64P_RM_SIZE = len(SVP64PrefixFields().rm.br)
684
685
686 class SPR(dict):
687 def __init__(self, dec2, initial_sprs={}):
688 self.sd = dec2
689 dict.__init__(self)
690 for key, v in initial_sprs.items():
691 if isinstance(key, SelectableInt):
692 key = key.value
693 key = special_sprs.get(key, key)
694 if isinstance(key, int):
695 info = spr_dict[key]
696 else:
697 info = spr_byname[key]
698 if not isinstance(v, SelectableInt):
699 v = SelectableInt(v, info.length)
700 self[key] = v
701
702 def __getitem__(self, key):
703 print("get spr", key)
704 print("dict", self.items())
705 # if key in special_sprs get the special spr, otherwise return key
706 if isinstance(key, SelectableInt):
707 key = key.value
708 if isinstance(key, int):
709 key = spr_dict[key].SPR
710 key = special_sprs.get(key, key)
711 if key == 'HSRR0': # HACK!
712 key = 'SRR0'
713 if key == 'HSRR1': # HACK!
714 key = 'SRR1'
715 if key in self:
716 res = dict.__getitem__(self, key)
717 else:
718 if isinstance(key, int):
719 info = spr_dict[key]
720 else:
721 info = spr_byname[key]
722 dict.__setitem__(self, key, SelectableInt(0, info.length))
723 res = dict.__getitem__(self, key)
724 print("spr returning", key, res)
725 return res
726
727 def __setitem__(self, key, value):
728 if isinstance(key, SelectableInt):
729 key = key.value
730 if isinstance(key, int):
731 key = spr_dict[key].SPR
732 print("spr key", key)
733 key = special_sprs.get(key, key)
734 if key == 'HSRR0': # HACK!
735 self.__setitem__('SRR0', value)
736 if key == 'HSRR1': # HACK!
737 self.__setitem__('SRR1', value)
738 print("setting spr", key, value)
739 dict.__setitem__(self, key, value)
740
741 def __call__(self, ridx):
742 return self[ridx]
743
744 def get_pdecode_idx_in(dec2, name):
745 op = dec2.dec.op
746 in1_sel = yield op.in1_sel
747 in2_sel = yield op.in2_sel
748 in3_sel = yield op.in3_sel
749 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
750 in1 = yield dec2.e.read_reg1.data
751 in2 = yield dec2.e.read_reg2.data
752 in3 = yield dec2.e.read_reg3.data
753 in1_isvec = yield dec2.in1_isvec
754 in2_isvec = yield dec2.in2_isvec
755 in3_isvec = yield dec2.in3_isvec
756 print ("get_pdecode_idx", in1_sel, In1Sel.RA.value, in1, in1_isvec)
757 # identify which regnames map to in1/2/3
758 if name == 'RA':
759 if (in1_sel == In1Sel.RA.value or
760 (in1_sel == In1Sel.RA_OR_ZERO.value and in1 != 0)):
761 return in1, in1_isvec
762 if in1_sel == In1Sel.RA_OR_ZERO.value:
763 return in1, in1_isvec
764 elif name == 'RB':
765 if in2_sel == In2Sel.RB.value:
766 return in2, in2_isvec
767 if in3_sel == In3Sel.RB.value:
768 return in3, in3_isvec
769 # XXX TODO, RC doesn't exist yet!
770 elif name == 'RC':
771 assert False, "RC does not exist yet"
772 elif name == 'RS':
773 if in1_sel == In1Sel.RS.value:
774 return in1, in1_isvec
775 if in2_sel == In2Sel.RS.value:
776 return in2, in2_isvec
777 if in3_sel == In3Sel.RS.value:
778 return in3, in3_isvec
779 return None, False
780
781
782 def get_pdecode_cr_out(dec2, name):
783 op = dec2.dec.op
784 out_sel = yield op.cr_out
785 out_bitfield = yield dec2.dec_cr_out.cr_bitfield.data
786 sv_cr_out = yield op.sv_cr_out
787 spec = yield dec2.crout_svdec.spec
788 sv_override = yield dec2.dec_cr_out.sv_override
789 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
790 out = yield dec2.e.write_cr.data
791 o_isvec = yield dec2.o_isvec
792 print ("get_pdecode_cr_out", out_sel, CROutSel.CR0.value, out, o_isvec)
793 print (" sv_cr_out", sv_cr_out)
794 print (" cr_bf", out_bitfield)
795 print (" spec", spec)
796 print (" override", sv_override)
797 # identify which regnames map to out / o2
798 if name == 'CR0':
799 if out_sel == CROutSel.CR0.value:
800 return out, o_isvec
801 print ("get_pdecode_idx_out not found", name)
802 return None, False
803
804
805 def get_pdecode_idx_out(dec2, name):
806 op = dec2.dec.op
807 out_sel = yield op.out_sel
808 # get the IN1/2/3 from the decoder (includes SVP64 remap and isvec)
809 out = yield dec2.e.write_reg.data
810 o_isvec = yield dec2.o_isvec
811 print ("get_pdecode_idx_out", out_sel, OutSel.RA.value, out, o_isvec)
812 # identify which regnames map to out / o2
813 if name == 'RA':
814 if out_sel == OutSel.RA.value:
815 return out, o_isvec
816 elif name == 'RT':
817 if out_sel == OutSel.RT.value:
818 return out, o_isvec
819 print ("get_pdecode_idx_out not found", name)
820 return None, False
821
822
823 # XXX TODO
824 def get_pdecode_idx_out2(dec2, name):
825 op = dec2.dec.op
826 print ("TODO: get_pdecode_idx_out2", name)
827 return None, False
828
829
830 class ISACaller:
831 # decoder2 - an instance of power_decoder2
832 # regfile - a list of initial values for the registers
833 # initial_{etc} - initial values for SPRs, Condition Register, Mem, MSR
834 # respect_pc - tracks the program counter. requires initial_insns
835 def __init__(self, decoder2, regfile, initial_sprs=None, initial_cr=0,
836 initial_mem=None, initial_msr=0,
837 initial_svstate=0,
838 initial_insns=None, respect_pc=False,
839 disassembly=None,
840 initial_pc=0,
841 bigendian=False,
842 mmu=False):
843
844 self.bigendian = bigendian
845 self.halted = False
846 self.is_svp64_mode = False
847 self.respect_pc = respect_pc
848 if initial_sprs is None:
849 initial_sprs = {}
850 if initial_mem is None:
851 initial_mem = {}
852 if initial_insns is None:
853 initial_insns = {}
854 assert self.respect_pc == False, "instructions required to honor pc"
855
856 print("ISACaller insns", respect_pc, initial_insns, disassembly)
857 print("ISACaller initial_msr", initial_msr)
858
859 # "fake program counter" mode (for unit testing)
860 self.fake_pc = 0
861 disasm_start = 0
862 if not respect_pc:
863 if isinstance(initial_mem, tuple):
864 self.fake_pc = initial_mem[0]
865 disasm_start = self.fake_pc
866 else:
867 disasm_start = initial_pc
868
869 # disassembly: we need this for now (not given from the decoder)
870 self.disassembly = {}
871 if disassembly:
872 for i, code in enumerate(disassembly):
873 self.disassembly[i*4 + disasm_start] = code
874
875 # set up registers, instruction memory, data memory, PC, SPRs, MSR
876 self.svp64rm = SVP64RM()
877 if isinstance(initial_svstate, int):
878 initial_svstate = SVP64State(initial_svstate)
879 self.svstate = initial_svstate
880 self.gpr = GPR(decoder2, self, self.svstate, regfile)
881 self.mem = Mem(row_bytes=8, initial_mem=initial_mem)
882 if mmu:
883 self.mem = RADIX(self.mem, self)
884 self.imem = Mem(row_bytes=4, initial_mem=initial_insns)
885 self.pc = PC()
886 self.spr = SPR(decoder2, initial_sprs)
887 self.msr = SelectableInt(initial_msr, 64) # underlying reg
888
889 # TODO, needed here:
890 # FPR (same as GPR except for FP nums)
891 # 4.2.2 p124 FPSCR (definitely "separate" - not in SPR)
892 # note that mffs, mcrfs, mtfsf "manage" this FPSCR
893 # 2.3.1 CR (and sub-fields CR0..CR6 - CR0 SO comes from XER.SO)
894 # note that mfocrf, mfcr, mtcr, mtocrf, mcrxrx "manage" CRs
895 # -- Done
896 # 2.3.2 LR (actually SPR #8) -- Done
897 # 2.3.3 CTR (actually SPR #9) -- Done
898 # 2.3.4 TAR (actually SPR #815)
899 # 3.2.2 p45 XER (actually SPR #1) -- Done
900 # 3.2.3 p46 p232 VRSAVE (actually SPR #256)
901
902 # create CR then allow portions of it to be "selectable" (below)
903 #rev_cr = int('{:016b}'.format(initial_cr)[::-1], 2)
904 self.cr = SelectableInt(initial_cr, 64) # underlying reg
905 #self.cr = FieldSelectableInt(self._cr, list(range(32, 64)))
906
907 # "undefined", just set to variable-bit-width int (use exts "max")
908 #self.undefined = SelectableInt(0, 256) # TODO, not hard-code 256!
909
910 self.namespace = {}
911 self.namespace.update(self.spr)
912 self.namespace.update({'GPR': self.gpr,
913 'MEM': self.mem,
914 'SPR': self.spr,
915 'memassign': self.memassign,
916 'NIA': self.pc.NIA,
917 'CIA': self.pc.CIA,
918 'CR': self.cr,
919 'MSR': self.msr,
920 'undefined': undefined,
921 'mode_is_64bit': True,
922 'SO': XER_bits['SO']
923 })
924
925 # update pc to requested start point
926 self.set_pc(initial_pc)
927
928 # field-selectable versions of Condition Register TODO check bitranges?
929 self.crl = []
930 for i in range(8):
931 bits = tuple(range(i*4+32, (i+1)*4+32)) # errr... maybe?
932 _cr = FieldSelectableInt(self.cr, bits)
933 self.crl.append(_cr)
934 self.namespace["CR%d" % i] = _cr
935
936 self.decoder = decoder2.dec
937 self.dec2 = decoder2
938
939 def TRAP(self, trap_addr=0x700, trap_bit=PIb.TRAP):
940 print("TRAP:", hex(trap_addr), hex(self.namespace['MSR'].value))
941 # store CIA(+4?) in SRR0, set NIA to 0x700
942 # store MSR in SRR1, set MSR to um errr something, have to check spec
943 self.spr['SRR0'].value = self.pc.CIA.value
944 self.spr['SRR1'].value = self.namespace['MSR'].value
945 self.trap_nia = SelectableInt(trap_addr, 64)
946 self.spr['SRR1'][trap_bit] = 1 # change *copy* of MSR in SRR1
947
948 # set exception bits. TODO: this should, based on the address
949 # in figure 66 p1065 V3.0B and the table figure 65 p1063 set these
950 # bits appropriately. however it turns out that *for now* in all
951 # cases (all trap_addrs) the exact same thing is needed.
952 self.msr[MSRb.IR] = 0
953 self.msr[MSRb.DR] = 0
954 self.msr[MSRb.FE0] = 0
955 self.msr[MSRb.FE1] = 0
956 self.msr[MSRb.EE] = 0
957 self.msr[MSRb.RI] = 0
958 self.msr[MSRb.SF] = 1
959 self.msr[MSRb.TM] = 0
960 self.msr[MSRb.VEC] = 0
961 self.msr[MSRb.VSX] = 0
962 self.msr[MSRb.PR] = 0
963 self.msr[MSRb.FP] = 0
964 self.msr[MSRb.PMM] = 0
965 self.msr[MSRb.TEs] = 0
966 self.msr[MSRb.TEe] = 0
967 self.msr[MSRb.UND] = 0
968 self.msr[MSRb.LE] = 1
969
970 def memassign(self, ea, sz, val):
971 self.mem.memassign(ea, sz, val)
972
973 def prep_namespace(self, formname, op_fields):
974 # TODO: get field names from form in decoder*1* (not decoder2)
975 # decoder2 is hand-created, and decoder1.sigform is auto-generated
976 # from spec
977 # then "yield" fields only from op_fields rather than hard-coded
978 # list, here.
979 fields = self.decoder.sigforms[formname]
980 for name in op_fields:
981 if name == 'spr':
982 sig = getattr(fields, name.upper())
983 else:
984 sig = getattr(fields, name)
985 val = yield sig
986 # these are all opcode fields involved in index-selection of CR,
987 # and need to do "standard" arithmetic. CR[BA+32] for example
988 # would, if using SelectableInt, only be 5-bit.
989 if name in ['BF', 'BFA', 'BC', 'BA', 'BB', 'BT', 'BI']:
990 self.namespace[name] = val
991 else:
992 self.namespace[name] = SelectableInt(val, sig.width)
993
994 self.namespace['XER'] = self.spr['XER']
995 self.namespace['CA'] = self.spr['XER'][XER_bits['CA']].value
996 self.namespace['CA32'] = self.spr['XER'][XER_bits['CA32']].value
997
998 def handle_carry_(self, inputs, outputs, already_done):
999 inv_a = yield self.dec2.e.do.invert_in
1000 if inv_a:
1001 inputs[0] = ~inputs[0]
1002
1003 imm_ok = yield self.dec2.e.do.imm_data.ok
1004 if imm_ok:
1005 imm = yield self.dec2.e.do.imm_data.data
1006 inputs.append(SelectableInt(imm, 64))
1007 assert len(outputs) >= 1
1008 print("outputs", repr(outputs))
1009 if isinstance(outputs, list) or isinstance(outputs, tuple):
1010 output = outputs[0]
1011 else:
1012 output = outputs
1013 gts = []
1014 for x in inputs:
1015 print("gt input", x, output)
1016 gt = (gtu(x, output))
1017 gts.append(gt)
1018 print(gts)
1019 cy = 1 if any(gts) else 0
1020 print("CA", cy, gts)
1021 if not (1 & already_done):
1022 self.spr['XER'][XER_bits['CA']] = cy
1023
1024 print("inputs", already_done, inputs)
1025 # 32 bit carry
1026 # ARGH... different for OP_ADD... *sigh*...
1027 op = yield self.dec2.e.do.insn_type
1028 if op == MicrOp.OP_ADD.value:
1029 res32 = (output.value & (1 << 32)) != 0
1030 a32 = (inputs[0].value & (1 << 32)) != 0
1031 if len(inputs) >= 2:
1032 b32 = (inputs[1].value & (1 << 32)) != 0
1033 else:
1034 b32 = False
1035 cy32 = res32 ^ a32 ^ b32
1036 print("CA32 ADD", cy32)
1037 else:
1038 gts = []
1039 for x in inputs:
1040 print("input", x, output)
1041 print(" x[32:64]", x, x[32:64])
1042 print(" o[32:64]", output, output[32:64])
1043 gt = (gtu(x[32:64], output[32:64])) == SelectableInt(1, 1)
1044 gts.append(gt)
1045 cy32 = 1 if any(gts) else 0
1046 print("CA32", cy32, gts)
1047 if not (2 & already_done):
1048 self.spr['XER'][XER_bits['CA32']] = cy32
1049
1050 def handle_overflow(self, inputs, outputs, div_overflow):
1051 if hasattr(self.dec2.e.do, "invert_in"):
1052 inv_a = yield self.dec2.e.do.invert_in
1053 if inv_a:
1054 inputs[0] = ~inputs[0]
1055
1056 imm_ok = yield self.dec2.e.do.imm_data.ok
1057 if imm_ok:
1058 imm = yield self.dec2.e.do.imm_data.data
1059 inputs.append(SelectableInt(imm, 64))
1060 assert len(outputs) >= 1
1061 print("handle_overflow", inputs, outputs, div_overflow)
1062 if len(inputs) < 2 and div_overflow is None:
1063 return
1064
1065 # div overflow is different: it's returned by the pseudo-code
1066 # because it's more complex than can be done by analysing the output
1067 if div_overflow is not None:
1068 ov, ov32 = div_overflow, div_overflow
1069 # arithmetic overflow can be done by analysing the input and output
1070 elif len(inputs) >= 2:
1071 output = outputs[0]
1072
1073 # OV (64-bit)
1074 input_sgn = [exts(x.value, x.bits) < 0 for x in inputs]
1075 output_sgn = exts(output.value, output.bits) < 0
1076 ov = 1 if input_sgn[0] == input_sgn[1] and \
1077 output_sgn != input_sgn[0] else 0
1078
1079 # OV (32-bit)
1080 input32_sgn = [exts(x.value, 32) < 0 for x in inputs]
1081 output32_sgn = exts(output.value, 32) < 0
1082 ov32 = 1 if input32_sgn[0] == input32_sgn[1] and \
1083 output32_sgn != input32_sgn[0] else 0
1084
1085 self.spr['XER'][XER_bits['OV']] = ov
1086 self.spr['XER'][XER_bits['OV32']] = ov32
1087 so = self.spr['XER'][XER_bits['SO']]
1088 so = so | ov
1089 self.spr['XER'][XER_bits['SO']] = so
1090
1091 def handle_comparison(self, outputs, cr_idx=0):
1092 out = outputs[0]
1093 assert isinstance(out, SelectableInt), \
1094 "out zero not a SelectableInt %s" % repr(outputs)
1095 print("handle_comparison", out.bits, hex(out.value))
1096 # TODO - XXX *processor* in 32-bit mode
1097 # https://bugs.libre-soc.org/show_bug.cgi?id=424
1098 # if is_32bit:
1099 # o32 = exts(out.value, 32)
1100 # print ("handle_comparison exts 32 bit", hex(o32))
1101 out = exts(out.value, out.bits)
1102 print("handle_comparison exts", hex(out))
1103 zero = SelectableInt(out == 0, 1)
1104 positive = SelectableInt(out > 0, 1)
1105 negative = SelectableInt(out < 0, 1)
1106 SO = self.spr['XER'][XER_bits['SO']]
1107 print("handle_comparison SO", SO)
1108 cr_field = selectconcat(negative, positive, zero, SO)
1109 self.crl[cr_idx].eq(cr_field)
1110
1111 def set_pc(self, pc_val):
1112 self.namespace['NIA'] = SelectableInt(pc_val, 64)
1113 self.pc.update(self.namespace, self.is_svp64_mode)
1114
1115 def setup_one(self):
1116 """set up one instruction
1117 """
1118 if self.respect_pc:
1119 pc = self.pc.CIA.value
1120 else:
1121 pc = self.fake_pc
1122 self._pc = pc
1123 ins = self.imem.ld(pc, 4, False, True)
1124 if ins is None:
1125 raise KeyError("no instruction at 0x%x" % pc)
1126 print("setup: 0x%x 0x%x %s" % (pc, ins & 0xffffffff, bin(ins)))
1127 print("CIA NIA", self.respect_pc, self.pc.CIA.value, self.pc.NIA.value)
1128
1129 yield self.dec2.sv_rm.eq(0)
1130 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff)
1131 yield self.dec2.dec.bigendian.eq(self.bigendian)
1132 yield self.dec2.state.msr.eq(self.msr.value)
1133 yield self.dec2.state.pc.eq(pc)
1134 yield self.dec2.state.svstate.eq(self.svstate.spr.value)
1135
1136 # SVP64. first, check if the opcode is EXT001, and SVP64 id bits set
1137 yield Settle()
1138 opcode = yield self.dec2.dec.opcode_in
1139 pfx = SVP64PrefixFields() # TODO should probably use SVP64PrefixDecoder
1140 pfx.insn.value = opcode
1141 major = pfx.major.asint(msb0=True) # MSB0 inversion
1142 print ("prefix test: opcode:", major, bin(major),
1143 pfx.insn[7] == 0b1, pfx.insn[9] == 0b1)
1144 self.is_svp64_mode = ((major == 0b000001) and
1145 pfx.insn[7].value == 0b1 and
1146 pfx.insn[9].value == 0b1)
1147 self.pc.update_nia(self.is_svp64_mode)
1148 self.namespace['NIA'] = self.pc.NIA
1149 if not self.is_svp64_mode:
1150 return
1151
1152 # in SVP64 mode. decode/print out svp64 prefix, get v3.0B instruction
1153 print ("svp64.rm", bin(pfx.rm.asint(msb0=True)))
1154 print (" svstate.vl", self.svstate.vl.asint(msb0=True))
1155 print (" svstate.mvl", self.svstate.maxvl.asint(msb0=True))
1156 sv_rm = pfx.rm.asint(msb0=True)
1157 ins = self.imem.ld(pc+4, 4, False, True)
1158 print(" svsetup: 0x%x 0x%x %s" % (pc+4, ins & 0xffffffff, bin(ins)))
1159 yield self.dec2.dec.raw_opcode_in.eq(ins & 0xffffffff) # v3.0B suffix
1160 yield self.dec2.sv_rm.eq(sv_rm) # svp64 prefix
1161 yield Settle()
1162
1163 def execute_one(self):
1164 """execute one instruction
1165 """
1166 # get the disassembly code for this instruction
1167 if self.is_svp64_mode:
1168 code = self.disassembly[self._pc+4]
1169 print(" svp64 sim-execute", hex(self._pc), code)
1170 else:
1171 code = self.disassembly[self._pc]
1172 print("sim-execute", hex(self._pc), code)
1173 opname = code.split(' ')[0]
1174 yield from self.call(opname)
1175
1176 # don't use this except in special circumstances
1177 if not self.respect_pc:
1178 self.fake_pc += 4
1179
1180 print("execute one, CIA NIA", self.pc.CIA.value, self.pc.NIA.value)
1181
1182 def get_assembly_name(self):
1183 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
1184 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
1185 dec_insn = yield self.dec2.e.do.insn
1186 asmcode = yield self.dec2.dec.op.asmcode
1187 print("get assembly name asmcode", asmcode, hex(dec_insn))
1188 asmop = insns.get(asmcode, None)
1189 int_op = yield self.dec2.dec.op.internal_op
1190
1191 # sigh reconstruct the assembly instruction name
1192 if hasattr(self.dec2.e.do, "oe"):
1193 ov_en = yield self.dec2.e.do.oe.oe
1194 ov_ok = yield self.dec2.e.do.oe.ok
1195 else:
1196 ov_en = False
1197 ov_ok = False
1198 if hasattr(self.dec2.e.do, "rc"):
1199 rc_en = yield self.dec2.e.do.rc.rc
1200 rc_ok = yield self.dec2.e.do.rc.ok
1201 else:
1202 rc_en = False
1203 rc_ok = False
1204 # grrrr have to special-case MUL op (see DecodeOE)
1205 print("ov %d en %d rc %d en %d op %d" %
1206 (ov_ok, ov_en, rc_ok, rc_en, int_op))
1207 if int_op in [MicrOp.OP_MUL_H64.value, MicrOp.OP_MUL_H32.value]:
1208 print("mul op")
1209 if rc_en & rc_ok:
1210 asmop += "."
1211 else:
1212 if not asmop.endswith("."): # don't add "." to "andis."
1213 if rc_en & rc_ok:
1214 asmop += "."
1215 if hasattr(self.dec2.e.do, "lk"):
1216 lk = yield self.dec2.e.do.lk
1217 if lk:
1218 asmop += "l"
1219 print("int_op", int_op)
1220 if int_op in [MicrOp.OP_B.value, MicrOp.OP_BC.value]:
1221 AA = yield self.dec2.dec.fields.FormI.AA[0:-1]
1222 print("AA", AA)
1223 if AA:
1224 asmop += "a"
1225 spr_msb = yield from self.get_spr_msb()
1226 if int_op == MicrOp.OP_MFCR.value:
1227 if spr_msb:
1228 asmop = 'mfocrf'
1229 else:
1230 asmop = 'mfcr'
1231 # XXX TODO: for whatever weird reason this doesn't work
1232 # https://bugs.libre-soc.org/show_bug.cgi?id=390
1233 if int_op == MicrOp.OP_MTCRF.value:
1234 if spr_msb:
1235 asmop = 'mtocrf'
1236 else:
1237 asmop = 'mtcrf'
1238 return asmop
1239
1240 def get_spr_msb(self):
1241 dec_insn = yield self.dec2.e.do.insn
1242 return dec_insn & (1 << 20) != 0 # sigh - XFF.spr[-1]?
1243
1244 def call(self, name):
1245 """call(opcode) - the primary execution point for instructions
1246 """
1247 name = name.strip() # remove spaces if not already done so
1248 if self.halted:
1249 print("halted - not executing", name)
1250 return
1251
1252 # TODO, asmregs is from the spec, e.g. add RT,RA,RB
1253 # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
1254 asmop = yield from self.get_assembly_name()
1255 print("call", name, asmop)
1256
1257 # check privileged
1258 int_op = yield self.dec2.dec.op.internal_op
1259 spr_msb = yield from self.get_spr_msb()
1260
1261 instr_is_privileged = False
1262 if int_op in [MicrOp.OP_ATTN.value,
1263 MicrOp.OP_MFMSR.value,
1264 MicrOp.OP_MTMSR.value,
1265 MicrOp.OP_MTMSRD.value,
1266 # TODO: OP_TLBIE
1267 MicrOp.OP_RFID.value]:
1268 instr_is_privileged = True
1269 if int_op in [MicrOp.OP_MFSPR.value,
1270 MicrOp.OP_MTSPR.value] and spr_msb:
1271 instr_is_privileged = True
1272
1273 print("is priv", instr_is_privileged, hex(self.msr.value),
1274 self.msr[MSRb.PR])
1275 # check MSR priv bit and whether op is privileged: if so, throw trap
1276 if instr_is_privileged and self.msr[MSRb.PR] == 1:
1277 self.TRAP(0x700, PIb.PRIV)
1278 self.namespace['NIA'] = self.trap_nia
1279 self.pc.update(self.namespace, self.is_svp64_mode)
1280 return
1281
1282 # check halted condition
1283 if name == 'attn':
1284 self.halted = True
1285 return
1286
1287 # check illegal instruction
1288 illegal = False
1289 if name not in ['mtcrf', 'mtocrf']:
1290 illegal = name != asmop
1291
1292 if illegal:
1293 print("illegal", name, asmop)
1294 self.TRAP(0x700, PIb.ILLEG)
1295 self.namespace['NIA'] = self.trap_nia
1296 self.pc.update(self.namespace, self.is_svp64_mode)
1297 print("name %s != %s - calling ILLEGAL trap, PC: %x" %
1298 (name, asmop, self.pc.CIA.value))
1299 return
1300
1301 info = self.instrs[name]
1302 yield from self.prep_namespace(info.form, info.op_fields)
1303
1304 # preserve order of register names
1305 input_names = create_args(list(info.read_regs) +
1306 list(info.uninit_regs))
1307 print(input_names)
1308
1309 # get SVP64 entry for the current instruction
1310 sv_rm = self.svp64rm.instrs.get(name)
1311 if sv_rm is not None:
1312 dest_cr, src_cr, src_byname, dest_byname = decode_extra(sv_rm)
1313 else:
1314 dest_cr, src_cr, src_byname, dest_byname = False, False, {}, {}
1315 print ("sv rm", sv_rm, dest_cr, src_cr, src_byname, dest_byname)
1316
1317 # get SVSTATE srcstep. TODO: dststep (twin predication)
1318 srcstep = self.svstate.srcstep.asint(msb0=True)
1319 vl = self.svstate.vl.asint(msb0=True)
1320 mvl = self.svstate.maxvl.asint(msb0=True)
1321
1322 # VL=0 in SVP64 mode means "do nothing: skip instruction"
1323 if self.is_svp64_mode and vl == 0:
1324 self.pc.update(self.namespace, self.is_svp64_mode)
1325 print("end of call", self.namespace['CIA'], self.namespace['NIA'])
1326 return
1327
1328 # main input registers (RT, RA ...)
1329 inputs = []
1330 for name in input_names:
1331 # using PowerDecoder2, first, find the decoder index.
1332 # (mapping name RA RB RC RS to in1, in2, in3)
1333 regnum, is_vec = yield from get_pdecode_idx_in(self.dec2, name)
1334 if regnum is None:
1335 # doing this is not part of svp64, it's because output
1336 # registers, to be modified, need to be in the namespace.
1337 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2, name)
1338 # here's where we go "vector". TODO: zero-testing (RA_IS_ZERO)
1339 # XXX already done by PowerDecoder2, now
1340 #if is_vec:
1341 # regnum += srcstep # TODO, elwidth overrides
1342
1343 # in case getting the register number is needed, _RA, _RB
1344 regname = "_" + name
1345 self.namespace[regname] = regnum
1346 print('reading reg %s %d' % (name, regnum), is_vec)
1347 reg_val = self.gpr(regnum)
1348 inputs.append(reg_val)
1349
1350 # "special" registers
1351 for special in info.special_regs:
1352 if special in special_sprs:
1353 inputs.append(self.spr[special])
1354 else:
1355 inputs.append(self.namespace[special])
1356
1357 # clear trap (trap) NIA
1358 self.trap_nia = None
1359
1360 print("inputs", inputs)
1361 results = info.func(self, *inputs)
1362 print("results", results)
1363
1364 # "inject" decorator takes namespace from function locals: we need to
1365 # overwrite NIA being overwritten (sigh)
1366 if self.trap_nia is not None:
1367 self.namespace['NIA'] = self.trap_nia
1368
1369 print("after func", self.namespace['CIA'], self.namespace['NIA'])
1370
1371 # detect if CA/CA32 already in outputs (sra*, basically)
1372 already_done = 0
1373 if info.write_regs:
1374 output_names = create_args(info.write_regs)
1375 for name in output_names:
1376 if name == 'CA':
1377 already_done |= 1
1378 if name == 'CA32':
1379 already_done |= 2
1380
1381 print("carry already done?", bin(already_done))
1382 if hasattr(self.dec2.e.do, "output_carry"):
1383 carry_en = yield self.dec2.e.do.output_carry
1384 else:
1385 carry_en = False
1386 if carry_en:
1387 yield from self.handle_carry_(inputs, results, already_done)
1388
1389 # detect if overflow was in return result
1390 overflow = None
1391 if info.write_regs:
1392 for name, output in zip(output_names, results):
1393 if name == 'overflow':
1394 overflow = output
1395
1396 if hasattr(self.dec2.e.do, "oe"):
1397 ov_en = yield self.dec2.e.do.oe.oe
1398 ov_ok = yield self.dec2.e.do.oe.ok
1399 else:
1400 ov_en = False
1401 ov_ok = False
1402 print("internal overflow", overflow, ov_en, ov_ok)
1403 if ov_en & ov_ok:
1404 yield from self.handle_overflow(inputs, results, overflow)
1405
1406 if hasattr(self.dec2.e.do, "rc"):
1407 rc_en = yield self.dec2.e.do.rc.rc
1408 else:
1409 rc_en = False
1410 if rc_en:
1411 regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
1412 self.handle_comparison(results, regnum)
1413
1414 # any modified return results?
1415 if info.write_regs:
1416 for name, output in zip(output_names, results):
1417 if name == 'overflow': # ignore, done already (above)
1418 continue
1419 if isinstance(output, int):
1420 output = SelectableInt(output, 256)
1421 if name in ['CA', 'CA32']:
1422 if carry_en:
1423 print("writing %s to XER" % name, output)
1424 self.spr['XER'][XER_bits[name]] = output.value
1425 else:
1426 print("NOT writing %s to XER" % name, output)
1427 elif name in info.special_regs:
1428 print('writing special %s' % name, output, special_sprs)
1429 if name in special_sprs:
1430 self.spr[name] = output
1431 else:
1432 self.namespace[name].eq(output)
1433 if name == 'MSR':
1434 print('msr written', hex(self.msr.value))
1435 else:
1436 regnum, is_vec = yield from get_pdecode_idx_out(self.dec2,
1437 name)
1438 if regnum is None:
1439 # temporary hack for not having 2nd output
1440 regnum = yield getattr(self.decoder, name)
1441 is_vec = False
1442 print('writing reg %d %s' % (regnum, str(output)), is_vec)
1443 if output.bits > 64:
1444 output = SelectableInt(output.value, 64)
1445 self.gpr[regnum] = output
1446
1447 # check if it is the SVSTATE.src/dest step that needs incrementing
1448 # this is our Sub-Program-Counter loop from 0 to VL-1
1449 if self.is_svp64_mode:
1450 # XXX twin predication TODO
1451 vl = self.svstate.vl.asint(msb0=True)
1452 mvl = self.svstate.maxvl.asint(msb0=True)
1453 srcstep = self.svstate.srcstep.asint(msb0=True)
1454 print (" svstate.vl", vl)
1455 print (" svstate.mvl", mvl)
1456 print (" svstate.srcstep", srcstep)
1457 # check if srcstep needs incrementing by one, stop PC advancing
1458 # svp64 loop can end early if the dest is scalar
1459 svp64_dest_vector = not (yield self.dec2.no_out_vec)
1460 if svp64_dest_vector and srcstep != vl-1:
1461 self.svstate.srcstep += SelectableInt(1, 7)
1462 self.pc.NIA.value = self.pc.CIA.value
1463 self.namespace['NIA'] = self.pc.NIA
1464 print("end of sub-pc call", self.namespace['CIA'],
1465 self.namespace['NIA'])
1466 return # DO NOT allow PC to update whilst Sub-PC loop running
1467 # reset to zero
1468 self.svstate.srcstep[0:7] = 0
1469 print (" svstate.srcstep loop end (PC to update)")
1470 self.pc.update_nia(self.is_svp64_mode)
1471 self.namespace['NIA'] = self.pc.NIA
1472
1473 # UPDATE program counter
1474 self.pc.update(self.namespace, self.is_svp64_mode)
1475 print("end of call", self.namespace['CIA'], self.namespace['NIA'])
1476
1477
1478 def inject():
1479 """Decorator factory.
1480
1481 this decorator will "inject" variables into the function's namespace,
1482 from the *dictionary* in self.namespace. it therefore becomes possible
1483 to make it look like a whole stack of variables which would otherwise
1484 need "self." inserted in front of them (*and* for those variables to be
1485 added to the instance) "appear" in the function.
1486
1487 "self.namespace['SI']" for example becomes accessible as just "SI" but
1488 *only* inside the function, when decorated.
1489 """
1490 def variable_injector(func):
1491 @wraps(func)
1492 def decorator(*args, **kwargs):
1493 try:
1494 func_globals = func.__globals__ # Python 2.6+
1495 except AttributeError:
1496 func_globals = func.func_globals # Earlier versions.
1497
1498 context = args[0].namespace # variables to be injected
1499 saved_values = func_globals.copy() # Shallow copy of dict.
1500 func_globals.update(context)
1501 result = func(*args, **kwargs)
1502 print("globals after", func_globals['CIA'], func_globals['NIA'])
1503 print("args[0]", args[0].namespace['CIA'],
1504 args[0].namespace['NIA'])
1505 args[0].namespace = func_globals
1506 #exec (func.__code__, func_globals)
1507
1508 # finally:
1509 # func_globals = saved_values # Undo changes.
1510
1511 return result
1512
1513 return decorator
1514
1515 return variable_injector
1516
1517
1518 # very quick test of maskgen function (TODO, move to util later)
1519 if __name__ == '__main__':
1520 shift = SelectableInt(5, 6)
1521 mask = genmask(shift, 43)
1522 print (" mask", bin(mask.value))
1523
1524 mem = Mem(row_bytes=8)
1525 mem = RADIX(mem, None)
1526 # -----------------------------------------------
1527 # |/|RTS1|/| RPDB | RTS2 | RPDS |
1528 # -----------------------------------------------
1529 # |0|1 2|3|4 55|56 58|59 63|
1530 data = SelectableInt(0, 64)
1531 data[1:3] = 0b01
1532 data[56:59] = 0b11
1533 data[59:64] = 0b01101 # mask
1534 data[55] = 1
1535 (rts, mbits, pgbase) = mem._decode_prte(data)
1536 print (" rts", bin(rts.value), rts.bits)
1537 print (" mbits", bin(mbits.value), mbits.bits)
1538 print (" pgbase", hex(pgbase.value), pgbase.bits)
1539 addr = SelectableInt(0x1000, 64)
1540 check = mem._segment_check(addr, mbits, shift)
1541 print (" segment check", check)