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[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26 import unittest
27
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift, size):
30 res = SelectableInt(0, size)
31 for i in range(size):
32 if i < shift:
33 res[size-1-i] = SelectableInt(1, 1)
34 return res
35
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
41
42 def rpte_valid(r):
43 return bool(r[0])
44
45 def rpte_leaf(r):
46 return bool(r[1])
47
48 ## Shift address bits 61--12 right by 0--47 bits and
49 ## supply the least significant 16 bits of the result.
50 def addrshift(addr,shift):
51 x = addr.value >> shift.value
52 return SelectableInt(x,16)
53
54 def NLB(x):
55 """
56 Next Level Base
57 right shifted by 8
58 """
59 return x[4:55]
60
61 def NLS(x):
62 """
63 Next Level Size
64 NLS >= 5
65 """
66 return x[59:63]
67
68 """
69 Get Root Page
70
71 //Accessing 2nd double word of partition table (pate1)
72 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
73 // PTCR Layout
74 // ====================================================
75 // -----------------------------------------------
76 // | /// | PATB | /// | PATS |
77 // -----------------------------------------------
78 // 0 4 51 52 58 59 63
79 // PATB[4:51] holds the base address of the Partition Table,
80 // right shifted by 12 bits.
81 // This is because the address of the Partition base is
82 // 4k aligned. Hence, the lower 12bits, which are always
83 // 0 are ommitted from the PTCR.
84 //
85 // Thus, The Partition Table Base is obtained by (PATB << 12)
86 //
87 // PATS represents the partition table size right-shifted by 12 bits.
88 // The minimal size of the partition table is 4k.
89 // Thus partition table size = (1 << PATS + 12).
90 //
91 // Partition Table
92 // ====================================================
93 // 0 PATE0 63 PATE1 127
94 // |----------------------|----------------------|
95 // | | |
96 // |----------------------|----------------------|
97 // | | |
98 // |----------------------|----------------------|
99 // | | | <-- effLPID
100 // |----------------------|----------------------|
101 // .
102 // .
103 // .
104 // |----------------------|----------------------|
105 // | | |
106 // |----------------------|----------------------|
107 //
108 // The effective LPID forms the index into the Partition Table.
109 //
110 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
111 // corresponding to that partition.
112 //
113 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
114 //
115 // PATE0 Layout
116 // -----------------------------------------------
117 // |1|RTS1|/| RPDB | RTS2 | RPDS |
118 // -----------------------------------------------
119 // 0 1 2 3 4 55 56 58 59 63
120 //
121 // HR[0] : For Radix Page table, first bit should be 1.
122 // RTS1[1:2] : Gives one fragment of the Radix treesize
123 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
124 // RTS = (RTS1 << 3 + RTS2) + 31.
125 //
126 // RPDB[4:55] = Root Page Directory Base.
127 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
128 // Thus, Root page directory size = 1 << (RPDS + 3).
129 // Note: RPDS >= 5.
130 //
131 // PATE1 Layout
132 // -----------------------------------------------
133 // |///| PRTB | // | PRTS |
134 // -----------------------------------------------
135 // 0 3 4 51 52 58 59 63
136 //
137 // PRTB[4:51] = Process Table Base. This is aligned to size.
138 // PRTS[59: 63] = Process Table Size right shifted by 12.
139 // Minimal size of the process table is 4k.
140 // Process Table Size = (1 << PRTS + 12).
141 // Note: PRTS <= 24.
142 //
143 // Computing the size aligned Process Table Base:
144 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
145 // Thus, the lower 12+PRTS bits of table_base will
146 // be zero.
147
148
149 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
150 //
151 // Process Table
152 // ==========================
153 // 0 PRTE0 63 PRTE1 127
154 // |----------------------|----------------------|
155 // | | |
156 // |----------------------|----------------------|
157 // | | |
158 // |----------------------|----------------------|
159 // | | | <-- effPID
160 // |----------------------|----------------------|
161 // .
162 // .
163 // .
164 // |----------------------|----------------------|
165 // | | |
166 // |----------------------|----------------------|
167 //
168 // The effective Process id (PID) forms the index into the Process Table.
169 //
170 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
171 // corresponding to that process
172 //
173 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
174 //
175 // PRTE0 Layout
176 // -----------------------------------------------
177 // |/|RTS1|/| RPDB | RTS2 | RPDS |
178 // -----------------------------------------------
179 // 0 1 2 3 4 55 56 58 59 63
180 //
181 // RTS1[1:2] : Gives one fragment of the Radix treesize
182 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
183 // RTS = (RTS1 << 3 + RTS2) << 31,
184 // since minimal Radix Tree size is 4G.
185 //
186 // RPDB = Root Page Directory Base.
187 // RPDS = Root Page Directory Size right shifted by 3.
188 // Thus, Root page directory size = RPDS << 3.
189 // Note: RPDS >= 5.
190 //
191 // PRTE1 Layout
192 // -----------------------------------------------
193 // | /// |
194 // -----------------------------------------------
195 // 0 63
196 // All bits are reserved.
197
198
199 """
200
201 testmem = {
202
203 0x10000: # PARTITION_TABLE_2 (not implemented yet)
204 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
205 0x800000000100000b,
206
207 0x30000: # RADIX_ROOT_PTE
208 # V = 1 L = 0 NLB = 0x400 NLS = 9
209 0x8000000000040009,
210 0x40000: # RADIX_SECOND_LEVEL
211 # V = 1 L = 1 SW = 0 RPN = 0
212 # R = 1 C = 1 ATT = 0 EAA 0x7
213 0xc000000000000187,
214
215 0x1000000: # PROCESS_TABLE_3
216 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
217 0x40000000000300ad,
218 }
219
220 # this one has a 2nd level RADIX with a RPN of 0x5000
221 testmem2 = {
222
223 0x10000: # PARTITION_TABLE_2 (not implemented yet)
224 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
225 0x800000000100000b,
226
227 0x30000: # RADIX_ROOT_PTE
228 # V = 1 L = 0 NLB = 0x400 NLS = 9
229 0x8000000000040009,
230 0x40000: # RADIX_SECOND_LEVEL
231 # V = 1 L = 1 SW = 0 RPN = 0x5000
232 # R = 1 C = 1 ATT = 0 EAA 0x7
233 0xc000000005000187,
234
235 0x1000000: # PROCESS_TABLE_3
236 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
237 0x40000000000300ad,
238 }
239
240
241 testresult = """
242 prtbl = 1000000
243 DCACHE GET 1000000 PROCESS_TABLE_3
244 DCACHE GET 30000 RADIX_ROOT_PTE V = 1 L = 0
245 DCACHE GET 40000 RADIX_SECOND_LEVEL V = 1 L = 1
246 DCACHE GET 10000 PARTITION_TABLE_2
247 translated done 1 err 0 badtree 0 addr 40000 pte 0
248 """
249
250 # see qemu/target/ppc/mmu-radix64.c for reference
251 class RADIX:
252 def __init__(self, mem, caller):
253 self.mem = mem
254 self.caller = caller
255 if caller is not None:
256 self.dsisr = self.caller.spr["DSISR"]
257 self.dar = self.caller.spr["DAR"]
258 self.pidr = self.caller.spr["PIDR"]
259 self.prtbl = self.caller.spr["PRTBL"]
260 self.msr = self.caller.msr
261
262 # cached page table stuff
263 self.pgtbl0 = 0
264 self.pt0_valid = False
265 self.pgtbl3 = 0
266 self.pt3_valid = False
267
268 def __call__(self, addr, sz):
269 val = self.ld(addr.value, sz, swap=False)
270 print("RADIX memread", addr, sz, val)
271 return SelectableInt(val, sz*8)
272
273 def ld(self, address, width=8, swap=True, check_in_mem=False,
274 instr_fetch=False):
275 print("RADIX: ld from addr 0x%x width %d" % (address, width))
276
277 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
278 if instr_fetch:
279 mode = 'EXECUTE'
280 else:
281 mode = 'LOAD'
282 addr = SelectableInt(address, 64)
283 (shift, mbits, pgbase) = self._decode_prte(addr)
284 #shift = SelectableInt(0, 32)
285
286 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
287
288 # use pte to load from phys address
289 return self.mem.ld(pte.value, width, swap, check_in_mem)
290
291 # XXX set SPRs on error
292
293 # TODO implement
294 def st(self, address, v, width=8, swap=True):
295 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
296
297 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
298 mode = 'STORE'
299 addr = SelectableInt(address, 64)
300 (shift, mbits, pgbase) = self._decode_prte(addr)
301 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
302
303 # use pte to store at phys address
304 return self.mem.st(pte.value, v, width, swap)
305
306 # XXX set SPRs on error
307
308 def memassign(self, addr, sz, val):
309 print("memassign", addr, sz, val)
310 self.st(addr.value, val.value, sz, swap=False)
311
312 def _next_level(self, addr, entry_width, swap, check_in_mem):
313 # implement read access to mmu mem here
314
315 # DO NOT perform byte-swapping: load 8 bytes (that's the entry size)
316 value = self.mem.ld(addr.value, 8, False, check_in_mem)
317 assert(value is not None, "address lookup %x not found" % addr.value)
318
319 print("addr", hex(addr.value))
320 data = SelectableInt(value, 64) # convert to SelectableInt
321 print("value", hex(value))
322 # index += 1
323 return data;
324
325 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
326 """walk tree
327
328 // vaddr 64 Bit
329 // vaddr |-----------------------------------------------------|
330 // | Unused | Used |
331 // |-----------|-----------------------------------------|
332 // | 0000000 | usefulBits = X bits (typically 52) |
333 // |-----------|-----------------------------------------|
334 // | |<--Cursize---->| |
335 // | | Index | |
336 // | | into Page | |
337 // | | Directory | |
338 // |-----------------------------------------------------|
339 // | |
340 // V |
341 // PDE |---------------------------| |
342 // |V|L|//| NLB |///|NLS| |
343 // |---------------------------| |
344 // PDE = Page Directory Entry |
345 // [0] = V = Valid Bit |
346 // [1] = L = Leaf bit. If 0, then |
347 // [4:55] = NLB = Next Level Base |
348 // right shifted by 8 |
349 // [59:63] = NLS = Next Level Size |
350 // | NLS >= 5 |
351 // | V
352 // | |--------------------------|
353 // | | usfulBits = X-Cursize |
354 // | |--------------------------|
355 // |---------------------><--NLS-->| |
356 // | Index | |
357 // | into | |
358 // | PDE | |
359 // |--------------------------|
360 // |
361 // If the next PDE obtained by |
362 // (NLB << 8 + 8 * index) is a |
363 // nonleaf, then repeat the above. |
364 // |
365 // If the next PDE is a leaf, |
366 // then Leaf PDE structure is as |
367 // follows |
368 // |
369 // |
370 // Leaf PDE |
371 // |------------------------------| |----------------|
372 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
373 // |------------------------------| |----------------|
374 // [0] = V = Valid Bit |
375 // [1] = L = Leaf Bit = 1 if leaf |
376 // PDE |
377 // [2] = Sw = Sw bit 0. |
378 // [7:51] = RPN = Real Page Number, V
379 // real_page = RPN << 12 -------------> Logical OR
380 // [52:54] = Sw Bits 1:3 |
381 // [55] = R = Reference |
382 // [56] = C = Change V
383 // [58:59] = Att = Physical Address
384 // 0b00 = Normal Memory
385 // 0b01 = SAO
386 // 0b10 = Non Idenmpotent
387 // 0b11 = Tolerant I/O
388 // [60:63] = Encoded Access
389 // Authority
390 //
391 """
392 # get sprs
393 print("_walk_tree")
394 pidr = self.caller.spr["PIDR"]
395 prtbl = self.caller.spr["PRTBL"]
396 print(pidr)
397 print(prtbl)
398 p = addr[55:63]
399 print("last 8 bits ----------")
400 print
401
402 # get address of root entry
403 shift = selectconcat(SelectableInt(0,1), prtbl[58:63]) # TODO verify
404 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
405 print("starting with prtable, addr_next",addr_next)
406
407 assert(addr_next.bits == 64)
408 assert(addr_next.value == 0x1000000) #TODO
409
410 # read an entry from prtable
411 swap = False
412 check_in_mem = False
413 entry_width = 8
414 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
415 print("pr_table",data)
416 pgtbl = data # this is cached in microwatt (as v.pgtbl3 / v.pgtbl0)
417
418 # rts = shift = unsigned('0' & data(62 downto 61) & data(7 downto 5));
419 shift = selectconcat(SelectableInt(0,1), data[1:3], data[55:58])
420 assert(shift.bits==6) # variable rts : unsigned(5 downto 0);
421 print("shift",shift)
422
423 # mbits := unsigned('0' & data(4 downto 0));
424 mbits = selectconcat(SelectableInt(0,1), data[58:63])
425 assert(mbits.bits==6) #variable mbits : unsigned(5 downto 0);
426
427 # WIP
428 if mbits==0:
429 return "invalid"
430
431 # mask_size := mbits(4 downto 0);
432 mask_size = mbits[0:5];
433 assert(mask_size.bits==5)
434 print("before segment check ==========")
435 print("mask_size:",bin(mask_size.value))
436 print("mbits:",bin(mbits.value))
437
438 print("calling segment_check")
439
440 mbits = selectconcat(SelectableInt(0,1), mask_size)
441 shift = self._segment_check(addr, mbits, shift)
442 print("shift",shift)
443
444 # v.pgbase := pgtbl(55 downto 8) & x"00";
445 leftzeros = SelectableInt(0,15)
446 pgbase = selectconcat(leftzeros,pgtbl[8:55],SelectableInt(0,2))
447
448 addrsh = addrshift(addr,shift)
449 print("addrsh",addrsh)
450
451 # TODO verify
452 addr_next = self._get_pgtable_addr(mask_size, pgbase, addrsh)
453 print("DONE addr_next",addr_next)
454
455 # wrong '0b000000011000000000'
456 # right '0b110000000000000000'
457 assert(addr_next==0x30000)
458
459 # walk tree starts on prtbl
460 while True:
461 print("nextlevel----------------------------")
462 # read an entry
463 swap = False
464 check_in_mem = False
465 entry_width = 8
466
467 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
468 valid = rpte_valid(data)
469 leaf = rpte_leaf(data)
470
471 print(" valid, leaf", valid, leaf)
472 if not valid:
473 return "invalid" # TODO: return error
474 if leaf:
475 print ("is leaf, checking perms")
476 ok = self._check_perms(data, priv, mode)
477 if ok == True: # data was ok, found phys address, return it?
478 paddr = self._get_pte(addrsh, addr, data)
479 print (" phys addr", hex(paddr.value))
480 return paddr
481 return ok # return the error code
482 else:
483 newlookup = self._new_lookup(data, shift)
484 if newlookup == 'badtree':
485 return newlookup
486 shift, mask, pgbase = newlookup
487 print (" next level", shift, mask, pgbase)
488 shift = SelectableInt(shift.value,16) #THIS is wrong !!!
489 print("calling _get_pgtable_addr")
490 print(mask) #SelectableInt(value=0x9, bits=4)
491 print(pgbase) #SelectableInt(value=0x40000, bits=56)
492 print(shift) #SelectableInt(value=0x4, bits=16) #FIXME
493 pgbase = SelectableInt(pgbase.value, 64)
494 addrsh = addrshift(addr,shift)
495 addr_next = self._get_pgtable_addr(mask, pgbase, addrsh)
496 print("addr_next",addr_next)
497 print("addrsh",addrsh)
498
499 def _new_lookup(self, data, shift):
500 """
501 mbits := unsigned('0' & data(4 downto 0));
502 if mbits < 5 or mbits > 16 or mbits > r.shift then
503 v.state := RADIX_FINISH;
504 v.badtree := '1'; -- throw error
505 else
506 v.shift := v.shift - mbits;
507 v.mask_size := mbits(4 downto 0);
508 v.pgbase := data(55 downto 8) & x"00"; NLB?
509 v.state := RADIX_LOOKUP; --> next level
510 end if;
511 """
512 mbits = data[59:64]
513 print("mbits=", mbits)
514 if mbits < 5 or mbits > 16: #fixme compare with r.shift
515 print("badtree")
516 return "badtree"
517 # reduce shift (has to be done at same bitwidth)
518 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
519 mask_size = mbits[1:5] # get 4 LSBs
520 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
521 return shift, mask_size, pgbase
522
523 def _decode_prte(self, data):
524 """PRTE0 Layout
525 -----------------------------------------------
526 |/|RTS1|/| RPDB | RTS2 | RPDS |
527 -----------------------------------------------
528 0 1 2 3 4 55 56 58 59 63
529 """
530 # note that SelectableInt does big-endian! so the indices
531 # below *directly* match the spec, unlike microwatt which
532 # has to turn them around (to LE)
533 zero = SelectableInt(0, 1)
534 rts = selectconcat(zero,
535 data[56:59], # RTS2
536 data[1:3], # RTS1
537 )
538 masksize = data[59:64] # RPDS
539 mbits = selectconcat(zero, masksize)
540 pgbase = selectconcat(data[8:56], # part of RPDB
541 SelectableInt(0, 16),)
542
543 return (rts, mbits, pgbase)
544
545 def _segment_check(self, addr, mbits, shift):
546 """checks segment valid
547 mbits := '0' & r.mask_size;
548 v.shift := r.shift + (31 - 12) - mbits;
549 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
550 if r.addr(63) /= r.addr(62) or nonzero = '1' then
551 v.state := RADIX_FINISH;
552 v.segerror := '1';
553 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
554 v.state := RADIX_FINISH;
555 v.badtree := '1';
556 else
557 v.state := RADIX_LOOKUP;
558 """
559 # note that SelectableInt does big-endian! so the indices
560 # below *directly* match the spec, unlike microwatt which
561 # has to turn them around (to LE)
562 mask = genmask(shift, 44)
563 nonzero = addr[2:33] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
564 print ("RADIX _segment_check nonzero", bin(nonzero.value))
565 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
566 if addr[0] != addr[1] or nonzero != 0:
567 return "segerror"
568 limit = shift + (31 - 12)
569 if mbits.value < 5 or mbits.value > 16 or mbits.value > limit.value:
570 return "badtree mbits="+str(mbits.value)+" limit="+str(limit.value)
571 new_shift = shift + (31 - 12) - mbits
572 # TODO verify that returned result is correct
573 return new_shift
574
575 def _check_perms(self, data, priv, mode):
576 """check page permissions
577 // Leaf PDE |
578 // |------------------------------| |----------------|
579 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
580 // |------------------------------| |----------------|
581 // [0] = V = Valid Bit |
582 // [1] = L = Leaf Bit = 1 if leaf |
583 // PDE |
584 // [2] = Sw = Sw bit 0. |
585 // [7:51] = RPN = Real Page Number, V
586 // real_page = RPN << 12 -------------> Logical OR
587 // [52:54] = Sw Bits 1:3 |
588 // [55] = R = Reference |
589 // [56] = C = Change V
590 // [58:59] = Att = Physical Address
591 // 0b00 = Normal Memory
592 // 0b01 = SAO
593 // 0b10 = Non Idenmpotent
594 // 0b11 = Tolerant I/O
595 // [60:63] = Encoded Access
596 // Authority
597 //
598 -- test leaf bit
599 -- check permissions and RC bits
600 perm_ok := '0';
601 if r.priv = '1' or data(3) = '0' then
602 if r.iside = '0' then
603 perm_ok := data(1) or (data(2) and not r.store);
604 else
605 -- no IAMR, so no KUEP support for now
606 -- deny execute permission if cache inhibited
607 perm_ok := data(0) and not data(5);
608 end if;
609 end if;
610 rc_ok := data(8) and (data(7) or not r.store);
611 if perm_ok = '1' and rc_ok = '1' then
612 v.state := RADIX_LOAD_TLB;
613 else
614 v.state := RADIX_FINISH;
615 v.perm_err := not perm_ok;
616 -- permission error takes precedence over RC error
617 v.rc_error := perm_ok;
618 end if;
619 """
620 # decode mode into something that matches microwatt equivalent code
621 instr_fetch, store = 0, 0
622 if mode == 'STORE':
623 store = 1
624 if mode == 'EXECUTE':
625 inst_fetch = 1
626
627 # check permissions and RC bits
628 perm_ok = 0
629 if priv == 1 or data[60] == 0:
630 if instr_fetch == 0:
631 perm_ok = data[62] | (data[61] & (store == 0))
632 # no IAMR, so no KUEP support for now
633 # deny execute permission if cache inhibited
634 perm_ok = data[63] & ~data[58]
635 rc_ok = data[55] & (data[56] | (store == 0))
636 if perm_ok == 1 and rc_ok == 1:
637 return True
638
639 return "perm_err" if perm_ok == 0 else "rc_err"
640
641 def _get_prtable_addr(self, shift, prtbl, addr, pid):
642 """
643 if r.addr(63) = '1' then
644 effpid := x"00000000";
645 else
646 effpid := r.pid;
647 end if;
648 x"00" & r.prtbl(55 downto 36) &
649 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
650 (effpid(31 downto 8) and finalmask(23 downto 0))) &
651 effpid(7 downto 0) & "0000";
652 """
653 print ("_get_prtable_addr", shift, prtbl, addr, pid)
654 finalmask = genmask(shift, 44)
655 finalmask24 = finalmask[20:44]
656 if addr[0].value == 1:
657 effpid = SelectableInt(0, 32)
658 else:
659 effpid = pid #self.pid # TODO, check on this
660 zero8 = SelectableInt(0, 8)
661 zero4 = SelectableInt(0, 4)
662 res = selectconcat(zero8,
663 prtbl[8:28], #
664 (prtbl[28:52] & ~finalmask24) | #
665 (effpid[0:24] & finalmask24), #
666 effpid[24:32],
667 zero4
668 )
669 return res
670
671 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
672 """
673 x"00" & r.pgbase(55 downto 19) &
674 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
675 "000";
676 """
677 mask16 = genmask(mask_size+5, 16)
678 zero8 = SelectableInt(0, 8)
679 zero3 = SelectableInt(0, 3)
680 res = selectconcat(zero8,
681 pgbase[8:45], #
682 (pgbase[45:61] & ~mask16) | #
683 (addrsh & mask16), #
684 zero3
685 )
686 return res
687
688 def _get_pte(self, shift, addr, pde):
689 """
690 x"00" &
691 ((r.pde(55 downto 12) and not finalmask) or
692 (r.addr(55 downto 12) and finalmask))
693 & r.pde(11 downto 0);
694 """
695 shift.value = 12
696 finalmask = genmask(shift, 44)
697 zero8 = SelectableInt(0, 8)
698 rpn = pde[8:52] # RPN = Real Page Number
699 abits = addr[8:52] # non-masked address bits
700 print(" get_pte RPN", hex(rpn.value))
701 print(" abits", hex(abits.value))
702 print(" shift", shift.value)
703 print(" finalmask", bin(finalmask.value))
704 res = selectconcat(zero8,
705 (rpn & ~finalmask) | #
706 (abits & finalmask), #
707 addr[52:64],
708 )
709 return res
710
711 class TestRadixMMU(unittest.TestCase):
712
713 def test_genmask(self):
714 shift = SelectableInt(5, 6)
715 mask = genmask(shift, 43)
716 print (" mask", bin(mask.value))
717
718 self.assertEqual(mask.value, 0b11111, "mask should be 5 1s")
719
720 def test_get_pgtable_addr(self):
721
722 mem = None
723 caller = None
724 dut = RADIX(mem, caller)
725
726 mask_size=4
727 pgbase = SelectableInt(0,64)
728 addrsh = SelectableInt(0,16)
729 ret = dut._get_pgtable_addr(mask_size, pgbase, addrsh)
730 print("ret=", ret)
731 self.assertEqual(ret, 0, "pgtbl_addr should be 0")
732
733 def test_walk_tree_1(self):
734
735 # test address as in
736 # https://github.com/power-gem5/gem5/blob/gem5-experimental/src/arch/power/radix_walk_example.txt#L65
737 testaddr = 0x1000
738 expected = 0x1000
739
740 # starting prtbl
741 prtbl = 0x1000000
742
743 # set up dummy minimal ISACaller
744 spr = {'DSISR': SelectableInt(0, 64),
745 'DAR': SelectableInt(0, 64),
746 'PIDR': SelectableInt(0, 64),
747 'PRTBL': SelectableInt(prtbl, 64)
748 }
749 # set problem state == 0 (other unit tests, set to 1)
750 msr = SelectableInt(0, 64)
751 msr[MSRb.PR] = 0
752 class ISACaller: pass
753 caller = ISACaller()
754 caller.spr = spr
755 caller.msr = msr
756
757 shift = SelectableInt(5, 6)
758 mask = genmask(shift, 43)
759 print (" mask", bin(mask.value))
760
761 mem = Mem(row_bytes=8, initial_mem=testmem)
762 mem = RADIX(mem, caller)
763 # -----------------------------------------------
764 # |/|RTS1|/| RPDB | RTS2 | RPDS |
765 # -----------------------------------------------
766 # |0|1 2|3|4 55|56 58|59 63|
767 data = SelectableInt(0, 64)
768 data[1:3] = 0b01
769 data[56:59] = 0b11
770 data[59:64] = 0b01101 # mask
771 data[55] = 1
772 (rts, mbits, pgbase) = mem._decode_prte(data)
773 print (" rts", bin(rts.value), rts.bits)
774 print (" mbits", bin(mbits.value), mbits.bits)
775 print (" pgbase", hex(pgbase.value), pgbase.bits)
776 addr = SelectableInt(0x1000, 64)
777 check = mem._segment_check(addr, mbits, shift)
778 print (" segment check", check)
779
780 print("walking tree")
781 addr = SelectableInt(testaddr,64)
782 # pgbase = None
783 mode = None
784 #mbits = None
785 shift = rts
786 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
787 print(" walking tree result", result)
788 print("should be", testresult)
789 self.assertEqual(result.value, expected,
790 "expected 0x%x got 0x%x" % (expected,
791 result.value))
792
793
794 def test_walk_tree_2(self):
795
796 # test address slightly different
797 testaddr = 0x1101
798 expected = 0x5001101
799
800 # starting prtbl
801 prtbl = 0x1000000
802
803 # set up dummy minimal ISACaller
804 spr = {'DSISR': SelectableInt(0, 64),
805 'DAR': SelectableInt(0, 64),
806 'PIDR': SelectableInt(0, 64),
807 'PRTBL': SelectableInt(prtbl, 64)
808 }
809 # set problem state == 0 (other unit tests, set to 1)
810 msr = SelectableInt(0, 64)
811 msr[MSRb.PR] = 0
812 class ISACaller: pass
813 caller = ISACaller()
814 caller.spr = spr
815 caller.msr = msr
816
817 shift = SelectableInt(5, 6)
818 mask = genmask(shift, 43)
819 print (" mask", bin(mask.value))
820
821 mem = Mem(row_bytes=8, initial_mem=testmem2)
822 mem = RADIX(mem, caller)
823 # -----------------------------------------------
824 # |/|RTS1|/| RPDB | RTS2 | RPDS |
825 # -----------------------------------------------
826 # |0|1 2|3|4 55|56 58|59 63|
827 data = SelectableInt(0, 64)
828 data[1:3] = 0b01
829 data[56:59] = 0b11
830 data[59:64] = 0b01101 # mask
831 data[55] = 1
832 (rts, mbits, pgbase) = mem._decode_prte(data)
833 print (" rts", bin(rts.value), rts.bits)
834 print (" mbits", bin(mbits.value), mbits.bits)
835 print (" pgbase", hex(pgbase.value), pgbase.bits)
836 addr = SelectableInt(0x1000, 64)
837 check = mem._segment_check(addr, mbits, shift)
838 print (" segment check", check)
839
840 print("walking tree")
841 addr = SelectableInt(testaddr,64)
842 # pgbase = None
843 mode = None
844 #mbits = None
845 shift = rts
846 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
847 print(" walking tree result", result)
848 print("should be", testresult)
849 self.assertEqual(result.value, expected,
850 "expected 0x%x got 0x%x" % (expected,
851 result.value))
852
853
854 if __name__ == '__main__':
855 unittest.main()