80c8febd64436d7a7c864a078a8a0cd9f4282c05
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
16 from nmigen
.back
.pysim
import Settle
18 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
20 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
21 from soc
.decoder
.isa
.mem
import Mem
22 from soc
.consts
import MSRb
# big-endian (PowerISA versions)
28 # very quick, TODO move to SelectableInt utils later
29 def genmask(shift
, size
):
30 res
= SelectableInt(0, size
)
33 res
[size
-1-i
] = SelectableInt(1, 1)
36 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
37 # MSB is indexed **LOWEST** (sigh)
38 # from gem5 radixwalk.hh
39 # Bitfield<63> valid; 64 - (63 + 1) = 0
40 # Bitfield<62> leaf; 64 - (62 + 1) = 1
65 //Accessing 2nd double word of partition table (pate1)
66 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
68 // ====================================================
69 // -----------------------------------------------
70 // | /// | PATB | /// | PATS |
71 // -----------------------------------------------
73 // PATB[4:51] holds the base address of the Partition Table,
74 // right shifted by 12 bits.
75 // This is because the address of the Partition base is
76 // 4k aligned. Hence, the lower 12bits, which are always
77 // 0 are ommitted from the PTCR.
79 // Thus, The Partition Table Base is obtained by (PATB << 12)
81 // PATS represents the partition table size right-shifted by 12 bits.
82 // The minimal size of the partition table is 4k.
83 // Thus partition table size = (1 << PATS + 12).
86 // ====================================================
87 // 0 PATE0 63 PATE1 127
88 // |----------------------|----------------------|
90 // |----------------------|----------------------|
92 // |----------------------|----------------------|
94 // |----------------------|----------------------|
98 // |----------------------|----------------------|
100 // |----------------------|----------------------|
102 // The effective LPID forms the index into the Partition Table.
104 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
105 // corresponding to that partition.
107 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
110 // -----------------------------------------------
111 // |1|RTS1|/| RPDB | RTS2 | RPDS |
112 // -----------------------------------------------
113 // 0 1 2 3 4 55 56 58 59 63
115 // HR[0] : For Radix Page table, first bit should be 1.
116 // RTS1[1:2] : Gives one fragment of the Radix treesize
117 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
118 // RTS = (RTS1 << 3 + RTS2) + 31.
120 // RPDB[4:55] = Root Page Directory Base.
121 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
122 // Thus, Root page directory size = 1 << (RPDS + 3).
126 // -----------------------------------------------
127 // |///| PRTB | // | PRTS |
128 // -----------------------------------------------
129 // 0 3 4 51 52 58 59 63
131 // PRTB[4:51] = Process Table Base. This is aligned to size.
132 // PRTS[59: 63] = Process Table Size right shifted by 12.
133 // Minimal size of the process table is 4k.
134 // Process Table Size = (1 << PRTS + 12).
137 // Computing the size aligned Process Table Base:
138 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
139 // Thus, the lower 12+PRTS bits of table_base will
143 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
146 // ==========================
147 // 0 PRTE0 63 PRTE1 127
148 // |----------------------|----------------------|
150 // |----------------------|----------------------|
152 // |----------------------|----------------------|
154 // |----------------------|----------------------|
158 // |----------------------|----------------------|
160 // |----------------------|----------------------|
162 // The effective Process id (PID) forms the index into the Process Table.
164 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
165 // corresponding to that process
167 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
170 // -----------------------------------------------
171 // |/|RTS1|/| RPDB | RTS2 | RPDS |
172 // -----------------------------------------------
173 // 0 1 2 3 4 55 56 58 59 63
175 // RTS1[1:2] : Gives one fragment of the Radix treesize
176 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
177 // RTS = (RTS1 << 3 + RTS2) << 31,
178 // since minimal Radix Tree size is 4G.
180 // RPDB = Root Page Directory Base.
181 // RPDS = Root Page Directory Size right shifted by 3.
182 // Thus, Root page directory size = RPDS << 3.
186 // -----------------------------------------------
188 // -----------------------------------------------
190 // All bits are reserved.
198 0x10000: # PARTITION_TABLE_2 (not implemented yet)
199 # PATB_GR=1 PRTB=0x1000 PRTS=0xb
202 0x30000: # RADIX_ROOT_PTE
203 # V = 1 L = 0 NLB = 0x400 NLS = 9
205 ######## 0x4000000 #### wrong address calculated by _get_pgtable_addr
206 0x40000: # RADIX_SECOND_LEVEL
207 # V = 1 L = 1 SW = 0 RPN = 0
208 # R = 1 C = 1 ATT = 0 EAA 0x7
211 0x1000000: # PROCESS_TABLE_3
212 # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
218 # see qemu/target/ppc/mmu-radix64.c for reference
220 def __init__(self
, mem
, caller
):
224 self
.dsisr
= self
.caller
.spr
["DSISR"]
225 self
.dar
= self
.caller
.spr
["DAR"]
226 self
.pidr
= self
.caller
.spr
["PIDR"]
227 self
.prtbl
= self
.caller
.spr
["PRTBL"]
228 self
.msr
= self
.caller
.msr
230 # cached page table stuff
232 self
.pt0_valid
= False
234 self
.pt3_valid
= False
236 def __call__(self
, addr
, sz
):
237 val
= self
.ld(addr
.value
, sz
, swap
=False)
238 print("RADIX memread", addr
, sz
, val
)
239 return SelectableInt(val
, sz
*8)
241 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False,
243 print("RADIX: ld from addr 0x%x width %d" % (address
, width
))
245 priv
= ~
(self
.msr(MSR_PR
).value
) # problem-state ==> privileged
250 addr
= SelectableInt(address
, 64)
251 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
252 #shift = SelectableInt(0, 32)
254 pte
= self
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
, priv
)
255 # use pte to caclculate phys address
256 return self
.mem
.ld(address
, width
, swap
, check_in_mem
)
258 # XXX set SPRs on error
261 def st(self
, address
, v
, width
=8, swap
=True):
262 print("RADIX: st to addr 0x%x width %d data %x" % (address
, width
, v
))
264 priv
= ~
(self
.msr(MSR_PR
).value
) # problem-state ==> privileged
266 addr
= SelectableInt(address
, 64)
267 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
268 pte
= self
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
, priv
)
270 # use pte to caclculate phys address (addr)
271 return self
.mem
.st(addr
.value
, v
, width
, swap
)
273 # XXX set SPRs on error
275 def memassign(self
, addr
, sz
, val
):
276 print("memassign", addr
, sz
, val
)
277 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
279 def _next_level(self
, addr
, entry_width
, swap
, check_in_mem
):
280 # implement read access to mmu mem here
283 if addr
.value
in testmem
:
284 value
= testmem
[addr
.value
]
288 ##value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
289 print("addr", hex(addr
.value
))
290 data
= SelectableInt(value
, 64) # convert to SelectableInt
291 print("value", hex(value
))
295 def _walk_tree(self
, addr
, pgbase
, mode
, mbits
, shift
, priv
=1):
299 // vaddr |-----------------------------------------------------|
301 // |-----------|-----------------------------------------|
302 // | 0000000 | usefulBits = X bits (typically 52) |
303 // |-----------|-----------------------------------------|
304 // | |<--Cursize---->| |
308 // |-----------------------------------------------------|
311 // PDE |---------------------------| |
312 // |V|L|//| NLB |///|NLS| |
313 // |---------------------------| |
314 // PDE = Page Directory Entry |
315 // [0] = V = Valid Bit |
316 // [1] = L = Leaf bit. If 0, then |
317 // [4:55] = NLB = Next Level Base |
318 // right shifted by 8 |
319 // [59:63] = NLS = Next Level Size |
322 // | |--------------------------|
323 // | | usfulBits = X-Cursize |
324 // | |--------------------------|
325 // |---------------------><--NLS-->| |
329 // |--------------------------|
331 // If the next PDE obtained by |
332 // (NLB << 8 + 8 * index) is a |
333 // nonleaf, then repeat the above. |
335 // If the next PDE is a leaf, |
336 // then Leaf PDE structure is as |
341 // |------------------------------| |----------------|
342 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
343 // |------------------------------| |----------------|
344 // [0] = V = Valid Bit |
345 // [1] = L = Leaf Bit = 1 if leaf |
347 // [2] = Sw = Sw bit 0. |
348 // [7:51] = RPN = Real Page Number, V
349 // real_page = RPN << 12 -------------> Logical OR
350 // [52:54] = Sw Bits 1:3 |
351 // [55] = R = Reference |
352 // [56] = C = Change V
353 // [58:59] = Att = Physical Address
354 // 0b00 = Normal Memory
356 // 0b10 = Non Idenmpotent
357 // 0b11 = Tolerant I/O
358 // [60:63] = Encoded Access
364 pidr
= self
.caller
.spr
["PIDR"]
365 prtbl
= self
.caller
.spr
["PRTBL"]
369 print("last 8 bits ----------")
372 # get address of root entry
373 addr_next
= self
._get
_prtable
_addr
(shift
, prtbl
, addr
, pidr
)
375 addr_next
= SelectableInt(0x30000,64) # radix root for testing
377 # walk tree starts on prtbl
379 print("nextlevel----------------------------")
385 data
= self
._next
_level
(addr_next
, entry_width
, swap
, check_in_mem
)
386 valid
= rpte_valid(data
)
387 leaf
= rpte_leaf(data
)
389 print(" valid, leaf", valid
, leaf
)
391 return "invalid" # TODO: return error
393 ok
= self
._check
_perms
(data
, priv
, mode
)
394 if ok
== True: # data was ok, found phys address, return it?
396 return ok
# return the error code
398 newlookup
= self
._new
_lookup
(data
, mbits
, shift
)
399 if newlookup
== 'badtree':
401 shift
, mask
, pgbase
= newlookup
402 print (" next level", shift
, mask
, pgbase
)
403 shift
= SelectableInt(shift
.value
,16) #THIS is wrong !!!
404 print("calling _get_pgtable_addr")
405 print(mask
) #SelectableInt(value=0x9, bits=4)
406 print(pgbase
) #SelectableInt(value=0x40000, bits=56)
407 print(shift
) #SelectableInt(value=0x4, bits=16) #FIXME
408 pgbase
= SelectableInt(pgbase
.value
,64)
409 addr_next
= self
._get
_pgtable
_addr
(mask
, pgbase
, shift
)
410 assert(addr_next
== 0x40000)
411 return "TODO verify next level"
413 def _new_lookup(self
, data
, mbits
, shift
):
415 mbits := unsigned('0' & data(4 downto 0));
416 if mbits < 5 or mbits > 16 or mbits > r.shift then
417 v.state := RADIX_FINISH;
418 v.badtree := '1'; -- throw error
420 v.shift := v.shift - mbits;
421 v.mask_size := mbits(4 downto 0);
422 v.pgbase := data(55 downto 8) & x"00"; NLB?
423 v.state := RADIX_LOOKUP; --> next level
427 print("mbits=", mbits
)
428 if mbits
< 5 or mbits
> 16: #fixme compare with r.shift
431 # reduce shift (has to be done at same bitwidth)
432 shift
= shift
- selectconcat(SelectableInt(0, 1), mbits
)
433 mask_size
= mbits
[1:5] # get 4 LSBs
434 pgbase
= selectconcat(data
[8:56], SelectableInt(0, 8)) # shift up 8
435 return shift
, mask_size
, pgbase
437 def _decode_prte(self
, data
):
439 -----------------------------------------------
440 |/|RTS1|/| RPDB | RTS2 | RPDS |
441 -----------------------------------------------
442 0 1 2 3 4 55 56 58 59 63
444 # note that SelectableInt does big-endian! so the indices
445 # below *directly* match the spec, unlike microwatt which
446 # has to turn them around (to LE)
447 zero
= SelectableInt(0, 1)
448 rts
= selectconcat(zero
,
452 masksize
= data
[59:64] # RPDS
453 mbits
= selectconcat(zero
, masksize
)
454 pgbase
= selectconcat(data
[8:56], # part of RPDB
455 SelectableInt(0, 16),)
457 return (rts
, mbits
, pgbase
)
459 def _segment_check(self
, addr
, mbits
, shift
):
460 """checks segment valid
461 mbits := '0' & r.mask_size;
462 v.shift := r.shift + (31 - 12) - mbits;
463 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
464 if r.addr(63) /= r.addr(62) or nonzero = '1' then
465 v.state := RADIX_FINISH;
467 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
468 v.state := RADIX_FINISH;
471 v.state := RADIX_LOOKUP;
473 # note that SelectableInt does big-endian! so the indices
474 # below *directly* match the spec, unlike microwatt which
475 # has to turn them around (to LE)
476 mask
= genmask(shift
, 44)
477 nonzero
= addr
[1:32] & mask
[13:44] # mask 31 LSBs (BE numbered 13:44)
478 print ("RADIX _segment_check nonzero", bin(nonzero
.value
))
479 print ("RADIX _segment_check addr[0-1]", addr
[0].value
, addr
[1].value
)
480 if addr
[0] != addr
[1] or nonzero
== 1:
482 limit
= shift
+ (31 - 12)
483 if mbits
< 5 or mbits
> 16 or mbits
> limit
:
485 new_shift
= shift
+ (31 - 12) - mbits
488 def _check_perms(self
, data
, priv
, mode
):
489 """check page permissions
491 // |------------------------------| |----------------|
492 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
493 // |------------------------------| |----------------|
494 // [0] = V = Valid Bit |
495 // [1] = L = Leaf Bit = 1 if leaf |
497 // [2] = Sw = Sw bit 0. |
498 // [7:51] = RPN = Real Page Number, V
499 // real_page = RPN << 12 -------------> Logical OR
500 // [52:54] = Sw Bits 1:3 |
501 // [55] = R = Reference |
502 // [56] = C = Change V
503 // [58:59] = Att = Physical Address
504 // 0b00 = Normal Memory
506 // 0b10 = Non Idenmpotent
507 // 0b11 = Tolerant I/O
508 // [60:63] = Encoded Access
512 -- check permissions and RC bits
514 if r.priv = '1' or data(3) = '0' then
515 if r.iside = '0' then
516 perm_ok := data(1) or (data(2) and not r.store);
518 -- no IAMR, so no KUEP support for now
519 -- deny execute permission if cache inhibited
520 perm_ok := data(0) and not data(5);
523 rc_ok := data(8) and (data(7) or not r.store);
524 if perm_ok = '1' and rc_ok = '1' then
525 v.state := RADIX_LOAD_TLB;
527 v.state := RADIX_FINISH;
528 v.perm_err := not perm_ok;
529 -- permission error takes precedence over RC error
530 v.rc_error := perm_ok;
533 # decode mode into something that matches microwatt equivalent code
534 instr_fetch
, store
= 0, 0
537 if mode
== 'EXECUTE':
540 # check permissions and RC bits
542 if priv
== 1 or data
[60] == 0:
544 perm_ok
= data
[62] |
(data
[61] & (store
== 0))
545 # no IAMR, so no KUEP support for now
546 # deny execute permission if cache inhibited
547 perm_ok
= data
[63] & ~data
[58]
548 rc_ok
= data
[55] & (data
[56] |
(store
== 0))
549 if perm_ok
== 1 and rc_ok
== 1:
552 return "perm_err" if perm_ok
== 0 else "rc_err"
554 def _get_prtable_addr(self
, shift
, prtbl
, addr
, pid
):
556 if r.addr(63) = '1' then
557 effpid := x"00000000";
561 x"00" & r.prtbl(55 downto 36) &
562 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
563 (effpid(31 downto 8) and finalmask(23 downto 0))) &
564 effpid(7 downto 0) & "0000";
566 print ("_get_prtable_addr_", shift
, prtbl
, addr
, pid
)
567 finalmask
= genmask(shift
, 44)
568 finalmask24
= finalmask
[20:44]
569 if addr
[0].value
== 1:
570 effpid
= SelectableInt(0, 32)
572 effpid
= pid
#self.pid # TODO, check on this
573 zero16
= SelectableInt(0, 16)
574 zero4
= SelectableInt(0, 4)
575 res
= selectconcat(zero16
,
577 (prtbl
[28:52] & ~finalmask24
) |
#
578 (effpid
[0:24] & finalmask24
), #
584 def _get_pgtable_addr(self
, mask_size
, pgbase
, addrsh
):
586 x"00" & r.pgbase(55 downto 19) &
587 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
590 mask16
= genmask(mask_size
+5, 16)
591 zero8
= SelectableInt(0, 8)
592 zero3
= SelectableInt(0, 3)
593 res
= selectconcat(zero8
,
595 (pgbase
[45:61] & ~mask16
) |
#
601 def _get_pte(self
, shift
, addr
, pde
):
604 ((r.pde(55 downto 12) and not finalmask) or
605 (r.addr(55 downto 12) and finalmask))
606 & r.pde(11 downto 0);
608 finalmask
= genmask(shift
, 44)
609 zero8
= SelectableInt(0, 8)
610 res
= selectconcat(zero8
,
611 (pde
[8:52] & ~finalmask
) |
#
612 (addr
[8:52] & finalmask
), #
618 class TestRadixMMU(unittest
.TestCase
):
620 def test_genmask(self
):
621 shift
= SelectableInt(5, 6)
622 mask
= genmask(shift
, 43)
623 print (" mask", bin(mask
.value
))
625 self
.assertEqual(sum([1, 2, 3]), 6, "Should be 6")
627 def test_get_pgtable_addr(self
):
631 dut
= RADIX(mem
, caller
)
634 pgbase
= SelectableInt(0,64)
635 addrsh
= SelectableInt(0,16)
636 ret
= dut
._get
_pgtable
_addr
(mask_size
, pgbase
, addrsh
)
640 def test_walk_tree(self
):
641 # set up dummy minimal ISACaller
642 spr
= {'DSISR': SelectableInt(0, 64),
643 'DAR': SelectableInt(0, 64),
644 'PIDR': SelectableInt(0, 64),
645 'PRTBL': SelectableInt(0, 64)
647 # set problem state == 0 (other unit tests, set to 1)
648 msr
= SelectableInt(0, 64)
650 class ISACaller
: pass
655 shift
= SelectableInt(5, 6)
656 mask
= genmask(shift
, 43)
657 print (" mask", bin(mask
.value
))
659 mem
= Mem(row_bytes
=8)
660 mem
= RADIX(mem
, caller
)
661 # -----------------------------------------------
662 # |/|RTS1|/| RPDB | RTS2 | RPDS |
663 # -----------------------------------------------
664 # |0|1 2|3|4 55|56 58|59 63|
665 data
= SelectableInt(0, 64)
668 data
[59:64] = 0b01101 # mask
670 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
671 print (" rts", bin(rts
.value
), rts
.bits
)
672 print (" mbits", bin(mbits
.value
), mbits
.bits
)
673 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
674 addr
= SelectableInt(0x1000, 64)
675 check
= mem
._segment
_check
(addr
, mbits
, shift
)
676 print (" segment check", check
)
678 print("walking tree")
679 addr
= SelectableInt(testaddr
,64)
684 result
= mem
._walk
_tree
(addr
, pgbase
, mode
, mbits
, shift
)
685 print(" walking tree result", result
)
688 if __name__
== '__main__':