cdd51edb97344aba34f7cb4a0265d97cf66656f9
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
16 from nmigen
.back
.pysim
import Settle
18 from soc
.decoder
.selectable_int
import (FieldSelectableInt
, SelectableInt
,
20 from soc
.decoder
.helpers
import exts
, gtu
, ltu
, undefined
21 from soc
.decoder
.isa
.mem
import Mem
26 # very quick, TODO move to SelectableInt utils later
27 def genmask(shift
, size
):
28 res
= SelectableInt(0, size
)
31 res
[size
-1-i
] = SelectableInt(1, 1)
37 //Accessing 2nd double word of partition table (pate1)
38 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
40 // ====================================================
41 // -----------------------------------------------
42 // | /// | PATB | /// | PATS |
43 // -----------------------------------------------
45 // PATB[4:51] holds the base address of the Partition Table,
46 // right shifted by 12 bits.
47 // This is because the address of the Partition base is
48 // 4k aligned. Hence, the lower 12bits, which are always
49 // 0 are ommitted from the PTCR.
51 // Thus, The Partition Table Base is obtained by (PATB << 12)
53 // PATS represents the partition table size right-shifted by 12 bits.
54 // The minimal size of the partition table is 4k.
55 // Thus partition table size = (1 << PATS + 12).
58 // ====================================================
59 // 0 PATE0 63 PATE1 127
60 // |----------------------|----------------------|
62 // |----------------------|----------------------|
64 // |----------------------|----------------------|
66 // |----------------------|----------------------|
70 // |----------------------|----------------------|
72 // |----------------------|----------------------|
74 // The effective LPID forms the index into the Partition Table.
76 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
77 // corresponding to that partition.
79 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
82 // -----------------------------------------------
83 // |1|RTS1|/| RPDB | RTS2 | RPDS |
84 // -----------------------------------------------
85 // 0 1 2 3 4 55 56 58 59 63
87 // HR[0] : For Radix Page table, first bit should be 1.
88 // RTS1[1:2] : Gives one fragment of the Radix treesize
89 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
90 // RTS = (RTS1 << 3 + RTS2) + 31.
92 // RPDB[4:55] = Root Page Directory Base.
93 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
94 // Thus, Root page directory size = 1 << (RPDS + 3).
98 // -----------------------------------------------
99 // |///| PRTB | // | PRTS |
100 // -----------------------------------------------
101 // 0 3 4 51 52 58 59 63
103 // PRTB[4:51] = Process Table Base. This is aligned to size.
104 // PRTS[59: 63] = Process Table Size right shifted by 12.
105 // Minimal size of the process table is 4k.
106 // Process Table Size = (1 << PRTS + 12).
109 // Computing the size aligned Process Table Base:
110 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
111 // Thus, the lower 12+PRTS bits of table_base will
115 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
118 // ==========================
119 // 0 PRTE0 63 PRTE1 127
120 // |----------------------|----------------------|
122 // |----------------------|----------------------|
124 // |----------------------|----------------------|
126 // |----------------------|----------------------|
130 // |----------------------|----------------------|
132 // |----------------------|----------------------|
134 // The effective Process id (PID) forms the index into the Process Table.
136 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
137 // corresponding to that process
139 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
142 // -----------------------------------------------
143 // |/|RTS1|/| RPDB | RTS2 | RPDS |
144 // -----------------------------------------------
145 // 0 1 2 3 4 55 56 58 59 63
147 // RTS1[1:2] : Gives one fragment of the Radix treesize
148 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
149 // RTS = (RTS1 << 3 + RTS2) << 31,
150 // since minimal Radix Tree size is 4G.
152 // RPDB = Root Page Directory Base.
153 // RPDS = Root Page Directory Size right shifted by 3.
154 // Thus, Root page directory size = RPDS << 3.
158 // -----------------------------------------------
160 // -----------------------------------------------
162 // All bits are reserved.
167 # see qemu/target/ppc/mmu-radix64.c for reference
169 def __init__(self
, mem
, caller
):
173 self
.dsisr
= self
.caller
.spr
["DSISR"]
174 self
.dar
= self
.caller
.spr
["DAR"]
175 self
.pidr
= self
.caller
.spr
["PIDR"]
176 self
.prtbl
= self
.caller
.spr
["PRTBL"]
178 # cached page table stuff
180 self
.pt0_valid
= False
182 self
.pt3_valid
= False
184 def __call__(self
, addr
, sz
):
185 val
= self
.ld(addr
.value
, sz
, swap
=False)
186 print("RADIX memread", addr
, sz
, val
)
187 return SelectableInt(val
, sz
*8)
189 def ld(self
, address
, width
=8, swap
=True, check_in_mem
=False):
190 print("RADIX: ld from addr 0x%x width %d" % (address
, width
))
192 addr
= SelectableInt(address
, 64)
193 (shift
, mbits
, pgbase
) = self
._decode
_prte
(addr
)
194 #shift = SelectableInt(0, 32)
196 pte
= self
._walk
_tree
(address
,shift
)
197 # use pte to caclculate phys address
198 return self
.mem
.ld(address
, width
, swap
, check_in_mem
)
200 # XXX set SPRs on error
203 def st(self
, addr
, v
, width
=8, swap
=True):
204 print("RADIX: st to addr 0x%x width %d data %x" % (addr
, width
, v
))
206 shift
= SelectableInt(0, 32)
207 pte
= self
._walk
_tree
(addr
,shift
)
209 # use pte to caclculate phys address (addr)
210 return self
.mem
.st(addr
, v
, width
, swap
)
212 # XXX set SPRs on error
214 def memassign(self
, addr
, sz
, val
):
215 print("memassign", addr
, sz
, val
)
216 self
.st(addr
.value
, val
.value
, sz
, swap
=False)
218 def _next_level(self
):
223 ## Prepare for next iteration
225 def _walk_tree(self
, addr
, shift
):
229 // vaddr |-----------------------------------------------------|
231 // |-----------|-----------------------------------------|
232 // | 0000000 | usefulBits = X bits (typically 52) |
233 // |-----------|-----------------------------------------|
234 // | |<--Cursize---->| |
238 // |-----------------------------------------------------|
241 // PDE |---------------------------| |
242 // |V|L|//| NLB |///|NLS| |
243 // |---------------------------| |
244 // PDE = Page Directory Entry |
245 // [0] = V = Valid Bit |
246 // [1] = L = Leaf bit. If 0, then |
247 // [4:55] = NLB = Next Level Base |
248 // right shifted by 8 |
249 // [59:63] = NLS = Next Level Size |
252 // | |--------------------------|
253 // | | usfulBits = X-Cursize |
254 // | |--------------------------|
255 // |---------------------><--NLS-->| |
259 // |--------------------------|
261 // If the next PDE obtained by |
262 // (NLB << 8 + 8 * index) is a |
263 // nonleaf, then repeat the above. |
265 // If the next PDE is a leaf, |
266 // then Leaf PDE structure is as |
271 // |------------------------------| |----------------|
272 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
273 // |------------------------------| |----------------|
274 // [0] = V = Valid Bit |
275 // [1] = L = Leaf Bit = 1 if leaf |
277 // [2] = Sw = Sw bit 0. |
278 // [7:51] = RPN = Real Page Number, V
279 // real_page = RPN << 12 -------------> Logical OR
280 // [52:54] = Sw Bits 1:3 |
281 // [55] = R = Reference |
282 // [56] = C = Change V
283 // [58:59] = Att = Physical Address
284 // 0b00 = Normal Memory
286 // 0b10 = Non Idenmpotent
287 // 0b11 = Tolerant I/O
288 // [60:63] = Encoded Access
294 pidr
= self
.caller
.spr
["PIDR"]
295 prtbl
= self
.caller
.spr
["PRTBL"]
298 #prtable_addr = self._get_prtable_addr(shift, prtbl, addr, pidr)
299 #print("prtable_addr",prtable_addr)
301 # TODO read root entry from process table first
303 # walk tree starts on prtbl
305 ret
= self
._next
_level
()
308 def _decode_prte(self
, data
):
310 -----------------------------------------------
311 |/|RTS1|/| RPDB | RTS2 | RPDS |
312 -----------------------------------------------
313 0 1 2 3 4 55 56 58 59 63
315 # note that SelectableInt does big-endian! so the indices
316 # below *directly* match the spec, unlike microwatt which
317 # has to turn them around (to LE)
318 zero
= SelectableInt(0, 1)
319 rts
= selectconcat(zero
,
323 masksize
= data
[59:64] # RPDS
324 mbits
= selectconcat(zero
, masksize
)
325 pgbase
= selectconcat(data
[8:56], # part of RPDB
326 SelectableInt(0, 16),)
328 return (rts
, mbits
, pgbase
)
330 def _segment_check(self
, addr
, mbits
, shift
):
331 """checks segment valid
332 mbits := '0' & r.mask_size;
333 v.shift := r.shift + (31 - 12) - mbits;
334 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
335 if r.addr(63) /= r.addr(62) or nonzero = '1' then
336 v.state := RADIX_FINISH;
338 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
339 v.state := RADIX_FINISH;
342 v.state := RADIX_LOOKUP;
344 # note that SelectableInt does big-endian! so the indices
345 # below *directly* match the spec, unlike microwatt which
346 # has to turn them around (to LE)
347 mask
= genmask(shift
, 44)
348 nonzero
= addr
[1:32] & mask
[13:44] # mask 31 LSBs (BE numbered 13:44)
349 print ("RADIX _segment_check nonzero", bin(nonzero
.value
))
350 print ("RADIX _segment_check addr[0-1]", addr
[0].value
, addr
[1].value
)
351 if addr
[0] != addr
[1] or nonzero
== 1:
353 limit
= shift
+ (31 - 12)
354 if mbits
< 5 or mbits
> 16 or mbits
> limit
:
356 new_shift
= shift
+ (31 - 12) - mbits
359 def _check_perms(self
, data
, priv
, iside
, store
):
360 """check page permissions
362 // |------------------------------| |----------------|
363 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
364 // |------------------------------| |----------------|
365 // [0] = V = Valid Bit |
366 // [1] = L = Leaf Bit = 1 if leaf |
368 // [2] = Sw = Sw bit 0. |
369 // [7:51] = RPN = Real Page Number, V
370 // real_page = RPN << 12 -------------> Logical OR
371 // [52:54] = Sw Bits 1:3 |
372 // [55] = R = Reference |
373 // [56] = C = Change V
374 // [58:59] = Att = Physical Address
375 // 0b00 = Normal Memory
377 // 0b10 = Non Idenmpotent
378 // 0b11 = Tolerant I/O
379 // [60:63] = Encoded Access
383 -- check permissions and RC bits
385 if r.priv = '1' or data(3) = '0' then
386 if r.iside = '0' then
387 perm_ok := data(1) or (data(2) and not r.store);
389 -- no IAMR, so no KUEP support for now
390 -- deny execute permission if cache inhibited
391 perm_ok := data(0) and not data(5);
394 rc_ok := data(8) and (data(7) or not r.store);
395 if perm_ok = '1' and rc_ok = '1' then
396 v.state := RADIX_LOAD_TLB;
398 v.state := RADIX_FINISH;
399 v.perm_err := not perm_ok;
400 -- permission error takes precedence over RC error
401 v.rc_error := perm_ok;
404 # check permissions and RC bits
406 if priv
== 1 or data
[60] == 0:
408 perm_ok
= data
[62] |
(data
[61] & (store
== 0))
409 # no IAMR, so no KUEP support for now
410 # deny execute permission if cache inhibited
411 perm_ok
= data
[63] & ~data
[58]
412 rc_ok
= data
[55] & (data
[56] |
(store
== 0))
413 if perm_ok
== 1 and rc_ok
== 1:
415 return "perm_err" if perm_ok
== 0 else "rc_err"
417 def _get_prtable_addr(self
, shift
, prtbl
, addr
, pid
):
419 if r.addr(63) = '1' then
420 effpid := x"00000000";
424 x"00" & r.prtbl(55 downto 36) &
425 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
426 (effpid(31 downto 8) and finalmask(23 downto 0))) &
427 effpid(7 downto 0) & "0000";
429 finalmask
= genmask(shift
, 44)
430 finalmask24
= finalmask
[20:44]
431 if addr
[0].value
== 1:
432 effpid
= SelectableInt(0, 32)
434 effpid
= self
.pid
[32:64] # TODO, check on this
435 zero16
= SelectableInt(0, 16)
436 zero4
= SelectableInt(0, 4)
437 res
= selectconcat(zero16
,
439 (prtbl
[28:52] & ~finalmask24
) |
#
440 (effpid
[0:24] & finalmask24
), #
446 def _get_pgtable_addr(self
, mask_size
, pgbase
, addrsh
):
448 x"00" & r.pgbase(55 downto 19) &
449 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
452 mask16
= genmask(mask_size
+5, 16)
453 zero8
= SelectableInt(0, 8)
454 zero3
= SelectableInt(0, 3)
455 res
= selectconcat(zero8
,
457 (prtbl
[45:61] & ~mask16
) |
#
463 def _get_pte(self
, shift
, addr
, pde
):
466 ((r.pde(55 downto 12) and not finalmask) or
467 (r.addr(55 downto 12) and finalmask))
468 & r.pde(11 downto 0);
470 finalmask
= genmask(shift
, 44)
471 zero8
= SelectableInt(0, 8)
472 res
= selectconcat(zero8
,
473 (pde
[8:52] & ~finalmask
) |
#
474 (addr
[8:52] & finalmask
), #
480 # very quick test of maskgen function (TODO, move to util later)
481 if __name__
== '__main__':
482 # set up dummy minimal ISACaller
483 spr
= {'DSISR': SelectableInt(0, 64),
484 'DAR': SelectableInt(0, 64),
485 'PIDR': SelectableInt(0, 64),
486 'PRTBL': SelectableInt(0, 64)
488 class ISACaller
: pass
492 shift
= SelectableInt(5, 6)
493 mask
= genmask(shift
, 43)
494 print (" mask", bin(mask
.value
))
496 mem
= Mem(row_bytes
=8)
497 mem
= RADIX(mem
, caller
)
498 # -----------------------------------------------
499 # |/|RTS1|/| RPDB | RTS2 | RPDS |
500 # -----------------------------------------------
501 # |0|1 2|3|4 55|56 58|59 63|
502 data
= SelectableInt(0, 64)
505 data
[59:64] = 0b01101 # mask
507 (rts
, mbits
, pgbase
) = mem
._decode
_prte
(data
)
508 print (" rts", bin(rts
.value
), rts
.bits
)
509 print (" mbits", bin(mbits
.value
), mbits
.bits
)
510 print (" pgbase", hex(pgbase
.value
), pgbase
.bits
)
511 addr
= SelectableInt(0x1000, 64)
512 check
= mem
._segment
_check
(addr
, mbits
, shift
)
513 print (" segment check", check
)