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[soc.git] / src / soc / decoder / isa / radixmmu.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2020, 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Copyright (C) 2021 Tobias Platen
4 # Funded by NLnet http://nlnet.nl
5 """core of the python-based POWER9 simulator
6
7 this is part of a cycle-accurate POWER9 simulator. its primary purpose is
8 not speed, it is for both learning and educational purposes, as well as
9 a method of verifying the HDL.
10
11 related bugs:
12
13 * https://bugs.libre-soc.org/show_bug.cgi?id=604
14 """
15
16 from nmigen.back.pysim import Settle
17 from copy import copy
18 from soc.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
19 selectconcat)
20 from soc.decoder.helpers import exts, gtu, ltu, undefined
21 from soc.decoder.isa.mem import Mem
22 from soc.consts import MSRb # big-endian (PowerISA versions)
23
24 import math
25 import sys
26
27 # very quick, TODO move to SelectableInt utils later
28 def genmask(shift, size):
29 res = SelectableInt(0, size)
30 for i in range(size):
31 if i < shift:
32 res[size-1-i] = SelectableInt(1, 1)
33 return res
34
35 # NOTE: POWER 3.0B annotation order! see p4 1.3.2
36 # MSB is indexed **LOWEST** (sigh)
37 # from gem5 radixwalk.hh
38 # Bitfield<63> valid; 64 - (63 + 1) = 0
39 # Bitfield<62> leaf; 64 - (62 + 1) = 1
40
41 def rpte_valid(r):
42 return bool(r[0])
43
44 def rpte_leaf(r):
45 return bool(r[1])
46
47 def NLB(x):
48 """
49 Next Level Base
50 right shifted by 8
51 """
52 return x[4:55]
53
54 def NLS(x):
55 """
56 Next Level Size
57 NLS >= 5
58 """
59 return x[59:63]
60
61 """
62 Get Root Page
63
64 //Accessing 2nd double word of partition table (pate1)
65 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.1
66 // PTCR Layout
67 // ====================================================
68 // -----------------------------------------------
69 // | /// | PATB | /// | PATS |
70 // -----------------------------------------------
71 // 0 4 51 52 58 59 63
72 // PATB[4:51] holds the base address of the Partition Table,
73 // right shifted by 12 bits.
74 // This is because the address of the Partition base is
75 // 4k aligned. Hence, the lower 12bits, which are always
76 // 0 are ommitted from the PTCR.
77 //
78 // Thus, The Partition Table Base is obtained by (PATB << 12)
79 //
80 // PATS represents the partition table size right-shifted by 12 bits.
81 // The minimal size of the partition table is 4k.
82 // Thus partition table size = (1 << PATS + 12).
83 //
84 // Partition Table
85 // ====================================================
86 // 0 PATE0 63 PATE1 127
87 // |----------------------|----------------------|
88 // | | |
89 // |----------------------|----------------------|
90 // | | |
91 // |----------------------|----------------------|
92 // | | | <-- effLPID
93 // |----------------------|----------------------|
94 // .
95 // .
96 // .
97 // |----------------------|----------------------|
98 // | | |
99 // |----------------------|----------------------|
100 //
101 // The effective LPID forms the index into the Partition Table.
102 //
103 // Each entry in the partition table contains 2 double words, PATE0, PATE1,
104 // corresponding to that partition.
105 //
106 // In case of Radix, The structure of PATE0 and PATE1 is as follows.
107 //
108 // PATE0 Layout
109 // -----------------------------------------------
110 // |1|RTS1|/| RPDB | RTS2 | RPDS |
111 // -----------------------------------------------
112 // 0 1 2 3 4 55 56 58 59 63
113 //
114 // HR[0] : For Radix Page table, first bit should be 1.
115 // RTS1[1:2] : Gives one fragment of the Radix treesize
116 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
117 // RTS = (RTS1 << 3 + RTS2) + 31.
118 //
119 // RPDB[4:55] = Root Page Directory Base.
120 // RPDS = Logarithm of Root Page Directory Size right shifted by 3.
121 // Thus, Root page directory size = 1 << (RPDS + 3).
122 // Note: RPDS >= 5.
123 //
124 // PATE1 Layout
125 // -----------------------------------------------
126 // |///| PRTB | // | PRTS |
127 // -----------------------------------------------
128 // 0 3 4 51 52 58 59 63
129 //
130 // PRTB[4:51] = Process Table Base. This is aligned to size.
131 // PRTS[59: 63] = Process Table Size right shifted by 12.
132 // Minimal size of the process table is 4k.
133 // Process Table Size = (1 << PRTS + 12).
134 // Note: PRTS <= 24.
135 //
136 // Computing the size aligned Process Table Base:
137 // table_base = (PRTB & ~((1 << PRTS) - 1)) << 12
138 // Thus, the lower 12+PRTS bits of table_base will
139 // be zero.
140
141
142 //Ref: Power ISA Manual v3.0B, Book-III, section 5.7.6.2
143 //
144 // Process Table
145 // ==========================
146 // 0 PRTE0 63 PRTE1 127
147 // |----------------------|----------------------|
148 // | | |
149 // |----------------------|----------------------|
150 // | | |
151 // |----------------------|----------------------|
152 // | | | <-- effPID
153 // |----------------------|----------------------|
154 // .
155 // .
156 // .
157 // |----------------------|----------------------|
158 // | | |
159 // |----------------------|----------------------|
160 //
161 // The effective Process id (PID) forms the index into the Process Table.
162 //
163 // Each entry in the partition table contains 2 double words, PRTE0, PRTE1,
164 // corresponding to that process
165 //
166 // In case of Radix, The structure of PRTE0 and PRTE1 is as follows.
167 //
168 // PRTE0 Layout
169 // -----------------------------------------------
170 // |/|RTS1|/| RPDB | RTS2 | RPDS |
171 // -----------------------------------------------
172 // 0 1 2 3 4 55 56 58 59 63
173 //
174 // RTS1[1:2] : Gives one fragment of the Radix treesize
175 // RTS2[56:58] : Gives the second fragment of the Radix Tree size.
176 // RTS = (RTS1 << 3 + RTS2) << 31,
177 // since minimal Radix Tree size is 4G.
178 //
179 // RPDB = Root Page Directory Base.
180 // RPDS = Root Page Directory Size right shifted by 3.
181 // Thus, Root page directory size = RPDS << 3.
182 // Note: RPDS >= 5.
183 //
184 // PRTE1 Layout
185 // -----------------------------------------------
186 // | /// |
187 // -----------------------------------------------
188 // 0 63
189 // All bits are reserved.
190
191
192 """
193
194 # see qemu/target/ppc/mmu-radix64.c for reference
195 class RADIX:
196 def __init__(self, mem, caller):
197 self.mem = mem
198 self.caller = caller
199 #TODO move to lookup
200 self.dsisr = self.caller.spr["DSISR"]
201 self.dar = self.caller.spr["DAR"]
202 self.pidr = self.caller.spr["PIDR"]
203 self.prtbl = self.caller.spr["PRTBL"]
204 self.msr = self.caller.msr
205
206 # cached page table stuff
207 self.pgtbl0 = 0
208 self.pt0_valid = False
209 self.pgtbl3 = 0
210 self.pt3_valid = False
211
212 def __call__(self, addr, sz):
213 val = self.ld(addr.value, sz, swap=False)
214 print("RADIX memread", addr, sz, val)
215 return SelectableInt(val, sz*8)
216
217 def ld(self, address, width=8, swap=True, check_in_mem=False,
218 instr_fetch=False):
219 print("RADIX: ld from addr 0x%x width %d" % (address, width))
220
221 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
222 if instr_fetch:
223 mode = 'EXECUTE'
224 else:
225 mode = 'LOAD'
226 addr = SelectableInt(address, 64)
227 (shift, mbits, pgbase) = self._decode_prte(addr)
228 #shift = SelectableInt(0, 32)
229
230 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
231 # use pte to caclculate phys address
232 return self.mem.ld(address, width, swap, check_in_mem)
233
234 # XXX set SPRs on error
235
236 # TODO implement
237 def st(self, address, v, width=8, swap=True):
238 print("RADIX: st to addr 0x%x width %d data %x" % (address, width, v))
239
240 priv = ~(self.msr(MSR_PR).value) # problem-state ==> privileged
241 mode = 'STORE'
242 addr = SelectableInt(address, 64)
243 (shift, mbits, pgbase) = self._decode_prte(addr)
244 pte = self._walk_tree(addr, pgbase, mode, mbits, shift, priv)
245
246 # use pte to caclculate phys address (addr)
247 return self.mem.st(addr.value, v, width, swap)
248
249 # XXX set SPRs on error
250
251 def memassign(self, addr, sz, val):
252 print("memassign", addr, sz, val)
253 self.st(addr.value, val.value, sz, swap=False)
254
255 def _next_level(self, addr, entry_width, swap, check_in_mem):
256 # implement read access to mmu mem here
257 value = self.mem.ld(addr.value, entry_width, swap, check_in_mem)
258 print("addr", addr.value)
259 data = SelectableInt(value, 64) # convert to SelectableInt
260 print("value", value)
261 # index += 1
262 return data;
263
264 def _walk_tree(self, addr, pgbase, mode, mbits, shift, priv=1):
265 """walk tree
266
267 // vaddr 64 Bit
268 // vaddr |-----------------------------------------------------|
269 // | Unused | Used |
270 // |-----------|-----------------------------------------|
271 // | 0000000 | usefulBits = X bits (typically 52) |
272 // |-----------|-----------------------------------------|
273 // | |<--Cursize---->| |
274 // | | Index | |
275 // | | into Page | |
276 // | | Directory | |
277 // |-----------------------------------------------------|
278 // | |
279 // V |
280 // PDE |---------------------------| |
281 // |V|L|//| NLB |///|NLS| |
282 // |---------------------------| |
283 // PDE = Page Directory Entry |
284 // [0] = V = Valid Bit |
285 // [1] = L = Leaf bit. If 0, then |
286 // [4:55] = NLB = Next Level Base |
287 // right shifted by 8 |
288 // [59:63] = NLS = Next Level Size |
289 // | NLS >= 5 |
290 // | V
291 // | |--------------------------|
292 // | | usfulBits = X-Cursize |
293 // | |--------------------------|
294 // |---------------------><--NLS-->| |
295 // | Index | |
296 // | into | |
297 // | PDE | |
298 // |--------------------------|
299 // |
300 // If the next PDE obtained by |
301 // (NLB << 8 + 8 * index) is a |
302 // nonleaf, then repeat the above. |
303 // |
304 // If the next PDE is a leaf, |
305 // then Leaf PDE structure is as |
306 // follows |
307 // |
308 // |
309 // Leaf PDE |
310 // |------------------------------| |----------------|
311 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
312 // |------------------------------| |----------------|
313 // [0] = V = Valid Bit |
314 // [1] = L = Leaf Bit = 1 if leaf |
315 // PDE |
316 // [2] = Sw = Sw bit 0. |
317 // [7:51] = RPN = Real Page Number, V
318 // real_page = RPN << 12 -------------> Logical OR
319 // [52:54] = Sw Bits 1:3 |
320 // [55] = R = Reference |
321 // [56] = C = Change V
322 // [58:59] = Att = Physical Address
323 // 0b00 = Normal Memory
324 // 0b01 = SAO
325 // 0b10 = Non Idenmpotent
326 // 0b11 = Tolerant I/O
327 // [60:63] = Encoded Access
328 // Authority
329 //
330 """
331 # get sprs
332 print("_walk_tree")
333 pidr = self.caller.spr["PIDR"]
334 prtbl = self.caller.spr["PRTBL"]
335 print(pidr)
336 print(prtbl)
337 p = addr[55:63]
338 print("last 8 bits ----------")
339 print
340
341 # get address of root entry
342 addr_next = self._get_prtable_addr(shift, prtbl, addr, pidr)
343
344 #test_input = [
345 # SelectableInt(0x8000000000000007, 64), #valid
346 # SelectableInt(0xc000000000000000, 64) #exit
347 #]
348 #index = 0
349
350 # walk tree starts on prtbl
351 while True:
352 print("nextlevel----------------------------")
353 # read an entry
354 swap = False
355 check_in_mem = False
356 entry_width = 8
357
358 data = self._next_level(addr_next, entry_width, swap, check_in_mem)
359 valid = rpte_valid(data)
360 leaf = rpte_leaf(data)
361
362 print(" valid, leaf", valid, leaf)
363 if not valid:
364 return "invalid" # TODO: return error
365 if leaf:
366 ok = self._check_perms(data, priv, mode)
367 if ok == True: # data was ok, found phys address, return it?
368 return addr_next
369 return ok # return the error code
370 else:
371 newlookup = self._new_lookup(data, mbits, shift)
372 if newlookup == 'badtree':
373 return newlookup
374 shift, mask, pgbase = newlookup
375 print (" next level", shift, mask, pgbase)
376 addr_next = self._get_pgtable_addr(mask, pgbase, shift)
377
378 def _new_lookup(self, data, mbits, shift):
379 """
380 mbits := unsigned('0' & data(4 downto 0));
381 if mbits < 5 or mbits > 16 or mbits > r.shift then
382 v.state := RADIX_FINISH;
383 v.badtree := '1'; -- throw error
384 else
385 v.shift := v.shift - mbits;
386 v.mask_size := mbits(4 downto 0);
387 v.pgbase := data(55 downto 8) & x"00"; NLB?
388 v.state := RADIX_LOOKUP; --> next level
389 end if;
390 """
391 mbits = data[59:64]
392 print("mbits=", mbits)
393 if mbits < 5 or mbits > 16: #fixme compare with r.shift
394 print("badtree")
395 return "badtree"
396 # reduce shift (has to be done at same bitwidth)
397 shift = shift - selectconcat(SelectableInt(0, 1), mbits)
398 mask_size = mbits[1:5] # get 4 LSBs
399 pgbase = selectconcat(data[8:56], SelectableInt(0, 8)) # shift up 8
400 return shift, mask_size, pgbase
401
402 def _decode_prte(self, data):
403 """PRTE0 Layout
404 -----------------------------------------------
405 |/|RTS1|/| RPDB | RTS2 | RPDS |
406 -----------------------------------------------
407 0 1 2 3 4 55 56 58 59 63
408 """
409 # note that SelectableInt does big-endian! so the indices
410 # below *directly* match the spec, unlike microwatt which
411 # has to turn them around (to LE)
412 zero = SelectableInt(0, 1)
413 rts = selectconcat(zero,
414 data[56:59], # RTS2
415 data[1:3], # RTS1
416 )
417 masksize = data[59:64] # RPDS
418 mbits = selectconcat(zero, masksize)
419 pgbase = selectconcat(data[8:56], # part of RPDB
420 SelectableInt(0, 16),)
421
422 return (rts, mbits, pgbase)
423
424 def _segment_check(self, addr, mbits, shift):
425 """checks segment valid
426 mbits := '0' & r.mask_size;
427 v.shift := r.shift + (31 - 12) - mbits;
428 nonzero := or(r.addr(61 downto 31) and not finalmask(30 downto 0));
429 if r.addr(63) /= r.addr(62) or nonzero = '1' then
430 v.state := RADIX_FINISH;
431 v.segerror := '1';
432 elsif mbits < 5 or mbits > 16 or mbits > (r.shift + (31 - 12)) then
433 v.state := RADIX_FINISH;
434 v.badtree := '1';
435 else
436 v.state := RADIX_LOOKUP;
437 """
438 # note that SelectableInt does big-endian! so the indices
439 # below *directly* match the spec, unlike microwatt which
440 # has to turn them around (to LE)
441 mask = genmask(shift, 44)
442 nonzero = addr[1:32] & mask[13:44] # mask 31 LSBs (BE numbered 13:44)
443 print ("RADIX _segment_check nonzero", bin(nonzero.value))
444 print ("RADIX _segment_check addr[0-1]", addr[0].value, addr[1].value)
445 if addr[0] != addr[1] or nonzero == 1:
446 return "segerror"
447 limit = shift + (31 - 12)
448 if mbits < 5 or mbits > 16 or mbits > limit:
449 return "badtree"
450 new_shift = shift + (31 - 12) - mbits
451 return new_shift
452
453 def _check_perms(self, data, priv, mode):
454 """check page permissions
455 // Leaf PDE |
456 // |------------------------------| |----------------|
457 // |V|L|sw|//|RPN|sw|R|C|/|ATT|EAA| | usefulBits |
458 // |------------------------------| |----------------|
459 // [0] = V = Valid Bit |
460 // [1] = L = Leaf Bit = 1 if leaf |
461 // PDE |
462 // [2] = Sw = Sw bit 0. |
463 // [7:51] = RPN = Real Page Number, V
464 // real_page = RPN << 12 -------------> Logical OR
465 // [52:54] = Sw Bits 1:3 |
466 // [55] = R = Reference |
467 // [56] = C = Change V
468 // [58:59] = Att = Physical Address
469 // 0b00 = Normal Memory
470 // 0b01 = SAO
471 // 0b10 = Non Idenmpotent
472 // 0b11 = Tolerant I/O
473 // [60:63] = Encoded Access
474 // Authority
475 //
476 -- test leaf bit
477 -- check permissions and RC bits
478 perm_ok := '0';
479 if r.priv = '1' or data(3) = '0' then
480 if r.iside = '0' then
481 perm_ok := data(1) or (data(2) and not r.store);
482 else
483 -- no IAMR, so no KUEP support for now
484 -- deny execute permission if cache inhibited
485 perm_ok := data(0) and not data(5);
486 end if;
487 end if;
488 rc_ok := data(8) and (data(7) or not r.store);
489 if perm_ok = '1' and rc_ok = '1' then
490 v.state := RADIX_LOAD_TLB;
491 else
492 v.state := RADIX_FINISH;
493 v.perm_err := not perm_ok;
494 -- permission error takes precedence over RC error
495 v.rc_error := perm_ok;
496 end if;
497 """
498 # decode mode into something that matches microwatt equivalent code
499 instr_fetch, store = 0, 0
500 if mode == 'STORE':
501 store = 1
502 if mode == 'EXECUTE':
503 inst_fetch = 1
504
505 # check permissions and RC bits
506 perm_ok = 0
507 if priv == 1 or data[60] == 0:
508 if instr_fetch == 0:
509 perm_ok = data[62] | (data[61] & (store == 0))
510 # no IAMR, so no KUEP support for now
511 # deny execute permission if cache inhibited
512 perm_ok = data[63] & ~data[58]
513 rc_ok = data[55] & (data[56] | (store == 0))
514 if perm_ok == 1 and rc_ok == 1:
515 return True
516
517 return "perm_err" if perm_ok == 0 else "rc_err"
518
519 def _get_prtable_addr(self, shift, prtbl, addr, pid):
520 """
521 if r.addr(63) = '1' then
522 effpid := x"00000000";
523 else
524 effpid := r.pid;
525 end if;
526 x"00" & r.prtbl(55 downto 36) &
527 ((r.prtbl(35 downto 12) and not finalmask(23 downto 0)) or
528 (effpid(31 downto 8) and finalmask(23 downto 0))) &
529 effpid(7 downto 0) & "0000";
530 """
531 print ("_get_prtable_addr_", shift, prtbl, addr, pid)
532 finalmask = genmask(shift, 44)
533 finalmask24 = finalmask[20:44]
534 if addr[0].value == 1:
535 effpid = SelectableInt(0, 32)
536 else:
537 effpid = pid #self.pid # TODO, check on this
538 zero16 = SelectableInt(0, 16)
539 zero4 = SelectableInt(0, 4)
540 res = selectconcat(zero16,
541 prtbl[8:28], #
542 (prtbl[28:52] & ~finalmask24) | #
543 (effpid[0:24] & finalmask24), #
544 effpid[24:32],
545 zero4
546 )
547 return res
548
549 def _get_pgtable_addr(self, mask_size, pgbase, addrsh):
550 """
551 x"00" & r.pgbase(55 downto 19) &
552 ((r.pgbase(18 downto 3) and not mask) or (addrsh and mask)) &
553 "000";
554 """
555 mask16 = genmask(mask_size+5, 16)
556 zero8 = SelectableInt(0, 8)
557 zero3 = SelectableInt(0, 3)
558 res = selectconcat(zero8,
559 pgbase[8:45], #
560 (prtbl[45:61] & ~mask16) | #
561 (addrsh & mask16), #
562 zero3
563 )
564 return res
565
566 def _get_pte(self, shift, addr, pde):
567 """
568 x"00" &
569 ((r.pde(55 downto 12) and not finalmask) or
570 (r.addr(55 downto 12) and finalmask))
571 & r.pde(11 downto 0);
572 """
573 finalmask = genmask(shift, 44)
574 zero8 = SelectableInt(0, 8)
575 res = selectconcat(zero8,
576 (pde[8:52] & ~finalmask) | #
577 (addr[8:52] & finalmask), #
578 pde[52:64],
579 )
580 return res
581
582
583 # very quick test of maskgen function (TODO, move to util later)
584 if __name__ == '__main__':
585 # set up dummy minimal ISACaller
586 spr = {'DSISR': SelectableInt(0, 64),
587 'DAR': SelectableInt(0, 64),
588 'PIDR': SelectableInt(0, 64),
589 'PRTBL': SelectableInt(0, 64)
590 }
591 # set problem state == 0 (other unit tests, set to 1)
592 msr = SelectableInt(0, 64)
593 msr[MSRb.PR] = 0
594 class ISACaller: pass
595 caller = ISACaller()
596 caller.spr = spr
597 caller.msr = msr
598
599 shift = SelectableInt(5, 6)
600 mask = genmask(shift, 43)
601 print (" mask", bin(mask.value))
602
603 mem = Mem(row_bytes=8)
604 mem = RADIX(mem, caller)
605 # -----------------------------------------------
606 # |/|RTS1|/| RPDB | RTS2 | RPDS |
607 # -----------------------------------------------
608 # |0|1 2|3|4 55|56 58|59 63|
609 data = SelectableInt(0, 64)
610 data[1:3] = 0b01
611 data[56:59] = 0b11
612 data[59:64] = 0b01101 # mask
613 data[55] = 1
614 (rts, mbits, pgbase) = mem._decode_prte(data)
615 print (" rts", bin(rts.value), rts.bits)
616 print (" mbits", bin(mbits.value), mbits.bits)
617 print (" pgbase", hex(pgbase.value), pgbase.bits)
618 addr = SelectableInt(0x1000, 64)
619 check = mem._segment_check(addr, mbits, shift)
620 print (" segment check", check)
621
622 print("walking tree")
623 # addr = unchanged
624 # pgbase = None
625 mode = None
626 #mbits = None
627 shift = rts
628 result = mem._walk_tree(addr, pgbase, mode, mbits, shift)
629 print(" walking tree result", result)