src/soc/decoder/isa/test_caller_setvl.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from soc.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_setvl_1(self):
  25         lst = SVP64Asm(["setvl 1, 0, 9, 1, 1",
  26                         ])
  27         lst = list(lst)
  28
  29         # SVSTATE (in this case, VL=2)
  30         svstate = SVP64State()
  31         svstate.vl[0:7] = 2 # VL
  32         svstate.maxvl[0:7] = 2 # MAXVL
  33         print ("SVSTATE", bin(svstate.spr.asint()))
  34
  35         with Program(lst, bigendian=False) as program:
  36             sim = self.run_tst_program(program, svstate=svstate)
  37             print ("SVSTATE after", bin(sim.svstate.spr.asint()))
  38             print ("        vl", bin(sim.svstate.vl.asint(True)))
  39             print ("        mvl", bin(sim.svstate.maxvl.asint(True)))
  40
  41     def run_tst_program(self, prog, initial_regs=None,
  42                               svstate=None):
  43         if initial_regs is None:
  44             initial_regs = [0] * 32
  45         simulator = run_tst(prog, initial_regs, svstate=svstate)
  46         simulator.gpr.dump()
  47         return simulator
  48
  49
  50 if __name__ == "__main__":
  51     unittest.main()