ad7991f18febae289809c53402f6d04841537fc6
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.isa
.caller
import ISACaller
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.simulator
.program
import Program
9 from soc
.decoder
.isa
.caller
import ISACaller
, SVP64State
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.decoder
.orderedset
import OrderedSet
12 from soc
.decoder
.isa
.all
import ISA
13 from soc
.decoder
.isa
.test_caller
import Register
, run_tst
14 from soc
.sv
.trans
.svp64
import SVP64Asm
15 from soc
.consts
import SVP64CROffs
16 from copy
import deepcopy
18 class DecoderTestCase(FHDLTestCase
):
20 def _check_regs(self
, sim
, expected
):
22 self
.assertEqual(sim
.gpr(i
), SelectableInt(expected
[i
], 64))
24 def test_setvl_1(self
):
25 lst
= SVP64Asm(["setvl 1, 0, 9, 1, 1",
29 # SVSTATE (in this case, VL=2)
30 svstate
= SVP64State()
31 svstate
.vl
[0:7] = 2 # VL
32 svstate
.maxvl
[0:7] = 2 # MAXVL
33 print ("SVSTATE", bin(svstate
.spr
.asint()))
35 with
Program(lst
, bigendian
=False) as program
:
36 sim
= self
.run_tst_program(program
, svstate
=svstate
)
37 print ("SVSTATE after", bin(sim
.svstate
.spr
.asint()))
38 print (" vl", bin(sim
.svstate
.vl
.asint(True)))
39 print (" mvl", bin(sim
.svstate
.maxvl
.asint(True)))
40 self
.assertEqual(sim
.svstate
.vl
.asint(True), 10)
41 self
.assertEqual(sim
.svstate
.maxvl
.asint(True), 10)
42 self
.assertEqual(sim
.svstate
.maxvl
.asint(True), 10)
43 print(" gpr1", sim
.gpr(1))
44 self
.assertEqual(sim
.gpr(1), SelectableInt(10, 64))
47 def test_sv_add(self
):
48 # sets VL=2 then adds:
49 # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
50 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
51 isa
= SVP64Asm(["setvl 3, 0, 1, 1, 1",
52 'sv.add 1.v, 5.v, 9.v'
55 print ("listing", lst
)
57 # initial values in GPR regfile
58 initial_regs
= [0] * 32
59 initial_regs
[9] = 0x1234
60 initial_regs
[10] = 0x1111
61 initial_regs
[5] = 0x4321
62 initial_regs
[6] = 0x2223
65 expected_regs
= deepcopy(initial_regs
)
66 expected_regs
[1] = 0x5555
67 expected_regs
[2] = 0x3334
68 expected_regs
[3] = 2 # setvl places copy of VL here
70 with
Program(lst
, bigendian
=False) as program
:
71 sim
= self
.run_tst_program(program
, initial_regs
)
72 self
._check
_regs
(sim
, expected_regs
)
74 def run_tst_program(self
, prog
, initial_regs
=None,
76 if initial_regs
is None:
77 initial_regs
= [0] * 32
78 simulator
= run_tst(prog
, initial_regs
, svstate
=svstate
)
83 if __name__
== "__main__":