src/soc/decoder/isa/test_caller_svp64.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from soc.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def test_sv_load_store(self):
  25         lst = SVP64Asm(["addi 1, 0, 0x0010",
  26                         "addi 2, 0, 0x1234",
  27                         "sv.stw 2, 0(1)",
  28                         "sv.lwz 3, 0(1)"])
  29         lst = list(lst)
  30
  31         # SVSTATE (in this case, VL=2)
  32         svstate = SVP64State()
  33         svstate.vl[0:7] = 1 # VL
  34         svstate.maxvl[0:7] = 1 # MAXVL
  35         print ("SVSTATE", bin(svstate.spr.asint()))
  36
  37         with Program(lst, bigendian=False) as program:
  38             sim = self.run_tst_program(program, svstate=svstate)
  39             print(sim.gpr(1))
  40             self.assertEqual(sim.gpr(3), SelectableInt(0x1234, 64))
  41
  42     def test_sv_add(self):
  43         # adds:
  44         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  45         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  46         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'
  47                        ])
  48         lst = list(isa)
  49         print ("listing", lst)
  50
  51         # initial values in GPR regfile
  52         initial_regs = [0] * 32
  53         initial_regs[9] = 0x1234
  54         initial_regs[10] = 0x1111
  55         initial_regs[5] = 0x4321
  56         initial_regs[6] = 0x2223
  57         # SVSTATE (in this case, VL=2)
  58         svstate = SVP64State()
  59         svstate.vl[0:7] = 2 # VL
  60         svstate.maxvl[0:7] = 2 # MAXVL
  61         print ("SVSTATE", bin(svstate.spr.asint()))
  62         # copy before running
  63         expected_regs = deepcopy(initial_regs)
  64         expected_regs[1] = 0x5555
  65         expected_regs[2] = 0x3334
  66
  67         with Program(lst, bigendian=False) as program:
  68             sim = self.run_tst_program(program, initial_regs, svstate)
  69             self._check_regs(sim, expected_regs)
  70
  71     def test_sv_add_2(self):
  72         # adds:
  73         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
  74         #       r1 is scalar so ENDS EARLY
  75         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
  76                        ])
  77         lst = list(isa)
  78         print ("listing", lst)
  79
  80         # initial values in GPR regfile
  81         initial_regs = [0] * 32
  82         initial_regs[9] = 0x1234
  83         initial_regs[10] = 0x1111
  84         initial_regs[5] = 0x4321
  85         initial_regs[6] = 0x2223
  86         # SVSTATE (in this case, VL=2)
  87         svstate = SVP64State()
  88         svstate.vl[0:7] = 2 # VL
  89         svstate.maxvl[0:7] = 2 # MAXVL
  90         print ("SVSTATE", bin(svstate.spr.asint()))
  91         # copy before running
  92         expected_regs = deepcopy(initial_regs)
  93         expected_regs[1] = 0x5555
  94
  95         with Program(lst, bigendian=False) as program:
  96             sim = self.run_tst_program(program, initial_regs, svstate)
  97             self._check_regs(sim, expected_regs)
  98
  99     def test_sv_add_3(self):
 100         # adds:
 101         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 102         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
 103         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
 104                        ])
 105         lst = list(isa)
 106         print ("listing", lst)
 107
 108         # initial values in GPR regfile
 109         initial_regs = [0] * 32
 110         initial_regs[9] = 0x1234
 111         initial_regs[10] = 0x1111
 112         initial_regs[5] = 0x4321
 113         initial_regs[6] = 0x2223
 114         # SVSTATE (in this case, VL=2)
 115         svstate = SVP64State()
 116         svstate.vl[0:7] = 2 # VL
 117         svstate.maxvl[0:7] = 2 # MAXVL
 118         print ("SVSTATE", bin(svstate.spr.asint()))
 119         # copy before running
 120         expected_regs = deepcopy(initial_regs)
 121         expected_regs[1] = 0x5555
 122         expected_regs[2] = 0x5432
 123
 124         with Program(lst, bigendian=False) as program:
 125             sim = self.run_tst_program(program, initial_regs, svstate)
 126             self._check_regs(sim, expected_regs)
 127
 128     def test_sv_add_vl_0(self):
 129         # adds:
 130         #       none because VL is zer0
 131         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
 132                        ])
 133         lst = list(isa)
 134         print ("listing", lst)
 135
 136         # initial values in GPR regfile
 137         initial_regs = [0] * 32
 138         initial_regs[9] = 0x1234
 139         initial_regs[10] = 0x1111
 140         initial_regs[5] = 0x4321
 141         initial_regs[6] = 0x2223
 142         # SVSTATE (in this case, VL=0)
 143         svstate = SVP64State()
 144         svstate.vl[0:7] = 0 # VL
 145         svstate.maxvl[0:7] = 0 # MAXVL
 146         print ("SVSTATE", bin(svstate.spr.asint()))
 147         # copy before running
 148         expected_regs = deepcopy(initial_regs)
 149
 150         with Program(lst, bigendian=False) as program:
 151             sim = self.run_tst_program(program, initial_regs, svstate)
 152             self._check_regs(sim, expected_regs)
 153
 154     def test_sv_add_cr(self):
 155         # adds when Rc=1:                               TODO CRs higher up
 156         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 157         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 158         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
 159                        ])
 160         lst = list(isa)
 161         print ("listing", lst)
 162
 163         # initial values in GPR regfile
 164         initial_regs = [0] * 32
 165         initial_regs[9] = 0xffffffffffffffff
 166         initial_regs[10] = 0x1111
 167         initial_regs[5] = 0x1
 168         initial_regs[6] = 0x2223
 169         # SVSTATE (in this case, VL=2)
 170         svstate = SVP64State()
 171         svstate.vl[0:7] = 2 # VL
 172         svstate.maxvl[0:7] = 2 # MAXVL
 173         print ("SVSTATE", bin(svstate.spr.asint()))
 174         # copy before running
 175         expected_regs = deepcopy(initial_regs)
 176         expected_regs[1] = 0
 177         expected_regs[2] = 0x3334
 178
 179         with Program(lst, bigendian=False) as program:
 180             sim = self.run_tst_program(program, initial_regs, svstate)
 181             # XXX TODO, these need to move to higher range (offset)
 182             cr0_idx = SVP64CROffs.CR0
 183             cr1_idx = SVP64CROffs.CR1
 184             CR0 = sim.crl[cr0_idx].get_range().value
 185             CR1 = sim.crl[cr1_idx].get_range().value
 186             print ("CR0", CR0)
 187             print ("CR1", CR1)
 188             self._check_regs(sim, expected_regs)
 189             self.assertEqual(CR0, SelectableInt(2, 4))
 190             self.assertEqual(CR1, SelectableInt(4, 4))
 191
 192     def run_tst_program(self, prog, initial_regs=None,
 193                               svstate=None):
 194         if initial_regs is None:
 195             initial_regs = [0] * 32
 196         simulator = run_tst(prog, initial_regs, svstate=svstate)
 197         simulator.gpr.dump()
 198         return simulator
 199
 200
 201 if __name__ == "__main__":
 202     unittest.main()