src/soc/decoder/isa/test_caller_svp64_predication.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from soc.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def tst_sv_load_store(self):
  25         lst = SVP64Asm(["addi 1, 0, 0x0010",
  26                         "addi 2, 0, 0x0008",
  27                         "addi 5, 0, 0x1234",
  28                         "addi 6, 0, 0x1235",
  29                         "sv.stw 5.v, 0(1.v)",
  30                         "sv.lwz 9.v, 0(1.v)"])
  31         lst = list(lst)
  32
  33         # SVSTATE (in this case, VL=2)
  34         svstate = SVP64State()
  35         svstate.vl[0:7] = 2 # VL
  36         svstate.maxvl[0:7] = 2 # MAXVL
  37         print ("SVSTATE", bin(svstate.spr.asint()))
  38
  39         with Program(lst, bigendian=False) as program:
  40             sim = self.run_tst_program(program, svstate=svstate)
  41             print(sim.gpr(1))
  42             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  43             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  44
  45     def test_sv_extsw_intpred(self):
  46         # extsb, integer twin-pred mask: source is ~r3 (0b01), dest r3 (0b10)
  47         # works as follows, where any zeros indicate "skip element"
  48         #       - sources are 9 and 10
  49         #       - dests are 5 and 6
  50         #       - source mask says "pick first element from source (5)
  51         #       - dest mask says "pick *second* element from dest (10)
  52         #
  53         # therefore the operation that's carried out is:
  54         #       GPR(10) = extsb(GPR(5))
  55         #
  56         # this is a type of back-to-back VREDUCE and VEXPAND but it applies
  57         # to *operations*, not just MVs like in traditional Vector ISAs
  58         # ascii graphic:
  59         #
  60         #   reg num        0 1 2 3 4 5 6 7 8 9 10
  61         #   src ~r3=0b01                     Y N
  62         #                                    |
  63         #                              +-----+
  64         #                              |
  65         #   dest r3=0b10             N Y
  66
  67         isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 5.v, 9.v'
  68                        ])
  69         lst = list(isa)
  70         print ("listing", lst)
  71
  72         # initial values in GPR regfile
  73         initial_regs = [0] * 32
  74         initial_regs[3] = 0b10   # predicate mask
  75         initial_regs[9] = 0x91   # source ~r3 is 0b01 so this will be used
  76         initial_regs[10] = 0x90  # this gets skipped
  77         # SVSTATE (in this case, VL=2)
  78         svstate = SVP64State()
  79         svstate.vl[0:7] = 2 # VL
  80         svstate.maxvl[0:7] = 2 # MAXVL
  81         print ("SVSTATE", bin(svstate.spr.asint()))
  82         # copy before running
  83         expected_regs = deepcopy(initial_regs)
  84         expected_regs[5] = 0x0                   # dest r3 is 0b10: skip
  85         expected_regs[6] = 0xffff_ffff_ffff_ff91 # 2nd bit of r3 is 1
  86
  87         with Program(lst, bigendian=False) as program:
  88             sim = self.run_tst_program(program, initial_regs, svstate)
  89             self._check_regs(sim, expected_regs)
  90
  91     def test_sv_extsw_intpred_dz(self):
  92         # extsb, integer twin-pred mask: dest is r3 (0b01), zeroing on dest
  93         isa = SVP64Asm(['sv.extsb/dm=r3/dz 5.v, 9.v'
  94                        ])
  95         lst = list(isa)
  96         print ("listing", lst)
  97
  98         # initial values in GPR regfile
  99         initial_regs = [0] * 32
 100         initial_regs[3] = 0b01   # predicate mask (dest)
 101         initial_regs[5] = 0xfeed # going to be overwritten
 102         initial_regs[6] = 0xbeef # going to be overwritten (with zero)
 103         initial_regs[9] = 0x91   # dest r3 is 0b01 so this will be used
 104         initial_regs[10] = 0x90  # this gets read but the output gets zero'd
 105         # SVSTATE (in this case, VL=2)
 106         svstate = SVP64State()
 107         svstate.vl[0:7] = 2 # VL
 108         svstate.maxvl[0:7] = 2 # MAXVL
 109         print ("SVSTATE", bin(svstate.spr.asint()))
 110         # copy before running
 111         expected_regs = deepcopy(initial_regs)
 112         expected_regs[5] = 0xffff_ffff_ffff_ff91 # dest r3 is 0b01: store
 113         expected_regs[6] = 0                     # 2nd bit of r3 is 1: zero
 114
 115         with Program(lst, bigendian=False) as program:
 116             sim = self.run_tst_program(program, initial_regs, svstate)
 117             self._check_regs(sim, expected_regs)
 118
 119     def test_sv_add_intpred(self):
 120         # adds, integer predicated mask r3=0b10
 121         #       1 = 5 + 9   => not to be touched (skipped)
 122         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 123         isa = SVP64Asm(['sv.add/m=r3 1.v, 5.v, 9.v'
 124                        ])
 125         lst = list(isa)
 126         print ("listing", lst)
 127
 128         # initial values in GPR regfile
 129         initial_regs = [0] * 32
 130         initial_regs[1] = 0xbeef   # not to be altered
 131         initial_regs[3] = 0b10   # predicate mask
 132         initial_regs[9] = 0x1234
 133         initial_regs[10] = 0x1111
 134         initial_regs[5] = 0x4321
 135         initial_regs[6] = 0x2223
 136         # SVSTATE (in this case, VL=2)
 137         svstate = SVP64State()
 138         svstate.vl[0:7] = 2 # VL
 139         svstate.maxvl[0:7] = 2 # MAXVL
 140         print ("SVSTATE", bin(svstate.spr.asint()))
 141         # copy before running
 142         expected_regs = deepcopy(initial_regs)
 143         expected_regs[1] = 0xbeef
 144         expected_regs[2] = 0x3334
 145
 146         with Program(lst, bigendian=False) as program:
 147             sim = self.run_tst_program(program, initial_regs, svstate)
 148             self._check_regs(sim, expected_regs)
 149
 150     def test_sv_add_cr_pred(self):
 151         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
 152         #       1 = 5 + 9   => not to be touched (skipped)
 153         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 154         isa = SVP64Asm(['sv.add/m=ne 1.v, 5.v, 9.v'
 155                        ])
 156         lst = list(isa)
 157         print ("listing", lst)
 158
 159         # initial values in GPR regfile
 160         initial_regs = [0] * 32
 161         initial_regs[1] = 0xbeef   # not to be altered
 162         initial_regs[9] = 0x1234
 163         initial_regs[10] = 0x1111
 164         initial_regs[5] = 0x4321
 165         initial_regs[6] = 0x2223
 166         # SVSTATE (in this case, VL=2)
 167         svstate = SVP64State()
 168         svstate.vl[0:7] = 2 # VL
 169         svstate.maxvl[0:7] = 2 # MAXVL
 170         print ("SVSTATE", bin(svstate.spr.asint()))
 171         # copy before running
 172         expected_regs = deepcopy(initial_regs)
 173         expected_regs[1] = 0xbeef
 174         expected_regs[2] = 0x3334
 175
 176         # set up CR predicate - CR4.eq=0 and CR5.eq=1
 177         cr = (0b0010) << ((7-4)*4) # CR5.eq (we hope)
 178
 179         with Program(lst, bigendian=False) as program:
 180             sim = self.run_tst_program(program, initial_regs, svstate,
 181                                        initial_cr=cr)
 182             self._check_regs(sim, expected_regs)
 183
 184     def tst_sv_add_2(self):
 185         # adds:
 186         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 187         #       r1 is scalar so ENDS EARLY
 188         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
 189                        ])
 190         lst = list(isa)
 191         print ("listing", lst)
 192
 193         # initial values in GPR regfile
 194         initial_regs = [0] * 32
 195         initial_regs[9] = 0x1234
 196         initial_regs[10] = 0x1111
 197         initial_regs[5] = 0x4321
 198         initial_regs[6] = 0x2223
 199         # SVSTATE (in this case, VL=2)
 200         svstate = SVP64State()
 201         svstate.vl[0:7] = 2 # VL
 202         svstate.maxvl[0:7] = 2 # MAXVL
 203         print ("SVSTATE", bin(svstate.spr.asint()))
 204         # copy before running
 205         expected_regs = deepcopy(initial_regs)
 206         expected_regs[1] = 0x5555
 207
 208         with Program(lst, bigendian=False) as program:
 209             sim = self.run_tst_program(program, initial_regs, svstate)
 210             self._check_regs(sim, expected_regs)
 211
 212     def tst_sv_add_3(self):
 213         # adds:
 214         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 215         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
 216         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'
 217                        ])
 218         lst = list(isa)
 219         print ("listing", lst)
 220
 221         # initial values in GPR regfile
 222         initial_regs = [0] * 32
 223         initial_regs[9] = 0x1234
 224         initial_regs[10] = 0x1111
 225         initial_regs[5] = 0x4321
 226         initial_regs[6] = 0x2223
 227         # SVSTATE (in this case, VL=2)
 228         svstate = SVP64State()
 229         svstate.vl[0:7] = 2 # VL
 230         svstate.maxvl[0:7] = 2 # MAXVL
 231         print ("SVSTATE", bin(svstate.spr.asint()))
 232         # copy before running
 233         expected_regs = deepcopy(initial_regs)
 234         expected_regs[1] = 0x5555
 235         expected_regs[2] = 0x5432
 236
 237         with Program(lst, bigendian=False) as program:
 238             sim = self.run_tst_program(program, initial_regs, svstate)
 239             self._check_regs(sim, expected_regs)
 240
 241     def tst_sv_add_vl_0(self):
 242         # adds:
 243         #       none because VL is zer0
 244         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'
 245                        ])
 246         lst = list(isa)
 247         print ("listing", lst)
 248
 249         # initial values in GPR regfile
 250         initial_regs = [0] * 32
 251         initial_regs[9] = 0x1234
 252         initial_regs[10] = 0x1111
 253         initial_regs[5] = 0x4321
 254         initial_regs[6] = 0x2223
 255         # SVSTATE (in this case, VL=0)
 256         svstate = SVP64State()
 257         svstate.vl[0:7] = 0 # VL
 258         svstate.maxvl[0:7] = 0 # MAXVL
 259         print ("SVSTATE", bin(svstate.spr.asint()))
 260         # copy before running
 261         expected_regs = deepcopy(initial_regs)
 262
 263         with Program(lst, bigendian=False) as program:
 264             sim = self.run_tst_program(program, initial_regs, svstate)
 265             self._check_regs(sim, expected_regs)
 266
 267     def tst_sv_add_cr(self):
 268         # adds when Rc=1:                               TODO CRs higher up
 269         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 270         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 271         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'
 272                        ])
 273         lst = list(isa)
 274         print ("listing", lst)
 275
 276         # initial values in GPR regfile
 277         initial_regs = [0] * 32
 278         initial_regs[9] = 0xffffffffffffffff
 279         initial_regs[10] = 0x1111
 280         initial_regs[5] = 0x1
 281         initial_regs[6] = 0x2223
 282         # SVSTATE (in this case, VL=2)
 283         svstate = SVP64State()
 284         svstate.vl[0:7] = 2 # VL
 285         svstate.maxvl[0:7] = 2 # MAXVL
 286         print ("SVSTATE", bin(svstate.spr.asint()))
 287         # copy before running
 288         expected_regs = deepcopy(initial_regs)
 289         expected_regs[1] = 0
 290         expected_regs[2] = 0x3334
 291
 292         with Program(lst, bigendian=False) as program:
 293             sim = self.run_tst_program(program, initial_regs, svstate)
 294             # XXX TODO, these need to move to higher range (offset)
 295             cr0_idx = SVP64CROffs.CR0
 296             cr1_idx = SVP64CROffs.CR1
 297             CR0 = sim.crl[cr0_idx].get_range().value
 298             CR1 = sim.crl[cr1_idx].get_range().value
 299             print ("CR0", CR0)
 300             print ("CR1", CR1)
 301             self._check_regs(sim, expected_regs)
 302             self.assertEqual(CR0, SelectableInt(2, 4))
 303             self.assertEqual(CR1, SelectableInt(4, 4))
 304
 305     def test_intpred_vcompress(self):
 306         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 307         #   src r3=0b101                     Y  N  Y
 308         #                                    |     |
 309         #                            +-------+     |
 310         #                            | +-----------+
 311         #                            | |
 312         #   dest always              Y Y Y
 313
 314         isa = SVP64Asm(['sv.extsb/sm=r3 5.v, 9.v'])
 315         lst = list(isa)
 316         print("listing", lst)
 317
 318         # initial values in GPR regfile
 319         initial_regs = [0] * 32
 320         initial_regs[3] = 0b101  # predicate mask
 321         initial_regs[9] = 0x90   # source r3 is 0b101 so this will be used
 322         initial_regs[10] = 0x91  # this gets skipped
 323         initial_regs[11] = 0x92  # source r3 is 0b101 so this will be used
 324         # SVSTATE (in this case, VL=3)
 325         svstate = SVP64State()
 326         svstate.vl[0:7] = 3  # VL
 327         svstate.maxvl[0:7] = 3  # MAXVL
 328         print("SVSTATE", bin(svstate.spr.asint()))
 329         # copy before running
 330         expected_regs = deepcopy(initial_regs)
 331         expected_regs[5] = 0xffff_ffff_ffff_ff90  # (from r9)
 332         expected_regs[6] = 0xffff_ffff_ffff_ff92  # (from r11)
 333         expected_regs[7] = 0x0  # (VL loop runs out before we can use it)
 334
 335         with Program(lst, bigendian=False) as program:
 336             sim = self.run_tst_program(program, initial_regs, svstate)
 337             self._check_regs(sim, expected_regs)
 338
 339     def test_intpred_vexpand(self):
 340         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 341         #   src always                       Y  Y  Y
 342         #                                    |  |
 343         #                            +-------+  |
 344         #                            |   +------+
 345         #                            |   |
 346         #   dest r3=0b101            Y N Y
 347
 348         isa = SVP64Asm(['sv.extsb/dm=r3 5.v, 9.v'])
 349         lst = list(isa)
 350         print("listing", lst)
 351
 352         # initial values in GPR regfile
 353         initial_regs = [0] * 32
 354         initial_regs[3] = 0b101  # predicate mask
 355         initial_regs[9] = 0x90   # source is "always", so this will be used
 356         initial_regs[10] = 0x91  # likewise
 357         initial_regs[11] = 0x92  # the VL loop runs out before we can use it
 358         # SVSTATE (in this case, VL=3)
 359         svstate = SVP64State()
 360         svstate.vl[0:7] = 3  # VL
 361         svstate.maxvl[0:7] = 3  # MAXVL
 362         print("SVSTATE", bin(svstate.spr.asint()))
 363         # copy before running
 364         expected_regs = deepcopy(initial_regs)
 365         expected_regs[5] = 0xffff_ffff_ffff_ff90  # 1st bit of r3 is 1
 366         expected_regs[6] = 0x0  # skip
 367         expected_regs[7] = 0xffff_ffff_ffff_ff91  # 3nd bit of r3 is 1
 368
 369         with Program(lst, bigendian=False) as program:
 370             sim = self.run_tst_program(program, initial_regs, svstate)
 371             self._check_regs(sim, expected_regs)
 372
 373     def test_intpred_twinpred(self):
 374         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 375         #   src r3=0b101                     Y  N  Y
 376         #                                    |
 377         #                              +-----+
 378         #                              |
 379         #   dest ~r3=0b010           N Y N
 380
 381         isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
 382         lst = list(isa)
 383         print("listing", lst)
 384
 385         # initial values in GPR regfile
 386         initial_regs = [0] * 32
 387         initial_regs[3] = 0b101  # predicate mask
 388         initial_regs[9] = 0x90   # source r3 is 0b101 so this will be used
 389         initial_regs[10] = 0x91  # this gets skipped
 390         initial_regs[11] = 0x92  # VL loop runs out before we can use it
 391         # SVSTATE (in this case, VL=3)
 392         svstate = SVP64State()
 393         svstate.vl[0:7] = 3  # VL
 394         svstate.maxvl[0:7] = 3  # MAXVL
 395         print("SVSTATE", bin(svstate.spr.asint()))
 396         # copy before running
 397         expected_regs = deepcopy(initial_regs)
 398         expected_regs[5] = 0x0  # dest ~r3 is 0b010: skip
 399         expected_regs[6] = 0xffff_ffff_ffff_ff90  # 2nd bit of ~r3 is 1
 400         expected_regs[7] = 0x0  # dest ~r3 is 0b010: skip
 401
 402         with Program(lst, bigendian=False) as program:
 403             sim = self.run_tst_program(program, initial_regs, svstate)
 404             self._check_regs(sim, expected_regs)
 405
 406     def run_tst_program(self, prog, initial_regs=None,
 407                               svstate=None,
 408                               initial_cr=0):
 409         if initial_regs is None:
 410             initial_regs = [0] * 32
 411         simulator = run_tst(prog, initial_regs, svstate=svstate,
 412                             initial_cr=initial_cr)
 413         simulator.gpr.dump()
 414         return simulator
 415
 416
 417 if __name__ == "__main__":
 418     unittest.main()