src/soc/decoder/isa/test_caller_svp64_predication.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 import unittest
   5 from soc.decoder.isa.caller import ISACaller
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.simulator.program import Program
   9 from soc.decoder.isa.caller import ISACaller, SVP64State
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.decoder.orderedset import OrderedSet
  12 from soc.decoder.isa.all import ISA
  13 from soc.decoder.isa.test_caller import Register, run_tst
  14 from soc.sv.trans.svp64 import SVP64Asm
  15 from soc.consts import SVP64CROffs
  16 from copy import deepcopy
  17
  18 class DecoderTestCase(FHDLTestCase):
  19
  20     def _check_regs(self, sim, expected):
  21         for i in range(32):
  22             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
  23
  24     def tst_sv_load_store(self):
  25         lst = SVP64Asm(["addi 1, 0, 0x0010",
  26                         "addi 2, 0, 0x0008",
  27                         "addi 5, 0, 0x1234",
  28                         "addi 6, 0, 0x1235",
  29                         "svstw 5.v, 0(1.v)",
  30                         "svlwz 9.v, 0(1.v)"])
  31         lst = list(lst)
  32
  33         # SVSTATE (in this case, VL=2)
  34         svstate = SVP64State()
  35         svstate.vl[0:7] = 2 # VL
  36         svstate.maxvl[0:7] = 2 # MAXVL
  37         print ("SVSTATE", bin(svstate.spr.asint()))
  38
  39         with Program(lst, bigendian=False) as program:
  40             sim = self.run_tst_program(program, svstate=svstate)
  41             print(sim.gpr(1))
  42             self.assertEqual(sim.gpr(9), SelectableInt(0x1234, 64))
  43             self.assertEqual(sim.gpr(10), SelectableInt(0x1235, 64))
  44
  45     def test_sv_extsw_intpred(self):
  46         # extsb, integer twin-pred mask: source is ~r3 (0b01), dest r3 (0b10)
  47         # works as follows, where any zeros indicate "skip element"
  48         #       - sources are 9 and 10
  49         #       - dests are 5 and 6
  50         #       - source mask says "pick first element from source (5)
  51         #       - dest mask says "pick *second* element from dest (10)
  52         # therefore the operation that's carried out is:
  53         #       GPR(10) = extsb(GPR(5))
  54         # this is a type of back-to-back VGATHER and VSCATTER but it applies
  55         # to *operations*, not just MVs like in traditional Vector ISAs
  56
  57         isa = SVP64Asm(['svextsb/sm=~r3/m=r3 5.v, 9.v'
  58                        ])
  59         lst = list(isa)
  60         print ("listing", lst)
  61
  62         # initial values in GPR regfile
  63         initial_regs = [0] * 32
  64         initial_regs[3] = 0b10   # predicate mask
  65         initial_regs[9] = 0x91   # source ~r3 is 0b01 so this will be used
  66         initial_regs[10] = 0x90  # this gets skipped
  67         # SVSTATE (in this case, VL=2)
  68         svstate = SVP64State()
  69         svstate.vl[0:7] = 2 # VL
  70         svstate.maxvl[0:7] = 2 # MAXVL
  71         print ("SVSTATE", bin(svstate.spr.asint()))
  72         # copy before running
  73         expected_regs = deepcopy(initial_regs)
  74         expected_regs[5] = 0x0                   # dest r3 is 0b10: skip
  75         expected_regs[6] = 0xffff_ffff_ffff_ff91 # 2nd bit of r3 is 1
  76
  77         with Program(lst, bigendian=False) as program:
  78             sim = self.run_tst_program(program, initial_regs, svstate)
  79             self._check_regs(sim, expected_regs)
  80
  81     def tst_sv_add_intpred(self):
  82         # adds, integer predicated mask r3=0b10
  83         #       1 = 5 + 9   => not to be touched (skipped)
  84         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
  85         isa = SVP64Asm(['svadd/m=r3 1.v, 5.v, 9.v'
  86                        ])
  87         lst = list(isa)
  88         print ("listing", lst)
  89
  90         # initial values in GPR regfile
  91         initial_regs = [0] * 32
  92         initial_regs[1] = 0xbeef   # not to be altered
  93         initial_regs[3] = 0b10   # predicate mask
  94         initial_regs[9] = 0x1234
  95         initial_regs[10] = 0x1111
  96         initial_regs[5] = 0x4321
  97         initial_regs[6] = 0x2223
  98         # SVSTATE (in this case, VL=2)
  99         svstate = SVP64State()
 100         svstate.vl[0:7] = 2 # VL
 101         svstate.maxvl[0:7] = 2 # MAXVL
 102         print ("SVSTATE", bin(svstate.spr.asint()))
 103         # copy before running
 104         expected_regs = deepcopy(initial_regs)
 105         expected_regs[1] = 0xbeef
 106         expected_regs[2] = 0x3334
 107
 108         with Program(lst, bigendian=False) as program:
 109             sim = self.run_tst_program(program, initial_regs, svstate)
 110             self._check_regs(sim, expected_regs)
 111
 112     def tst_sv_add_cr_pred(self):
 113         # adds, CR predicated mask CR4.eq = 1, CR5.eq = 0, invert (ne)
 114         #       1 = 5 + 9   => not to be touched (skipped)
 115         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111
 116         isa = SVP64Asm(['svadd/m=ne 1.v, 5.v, 9.v'
 117                        ])
 118         lst = list(isa)
 119         print ("listing", lst)
 120
 121         # initial values in GPR regfile
 122         initial_regs = [0] * 32
 123         initial_regs[1] = 0xbeef   # not to be altered
 124         initial_regs[9] = 0x1234
 125         initial_regs[10] = 0x1111
 126         initial_regs[5] = 0x4321
 127         initial_regs[6] = 0x2223
 128         # SVSTATE (in this case, VL=2)
 129         svstate = SVP64State()
 130         svstate.vl[0:7] = 2 # VL
 131         svstate.maxvl[0:7] = 2 # MAXVL
 132         print ("SVSTATE", bin(svstate.spr.asint()))
 133         # copy before running
 134         expected_regs = deepcopy(initial_regs)
 135         expected_regs[1] = 0xbeef
 136         expected_regs[2] = 0x3334
 137
 138         # set up CR predicate - CR4.eq=0 and CR5.eq=1
 139         cr = (0b0010) << ((7-4)*4) # CR5.eq (we hope)
 140
 141         with Program(lst, bigendian=False) as program:
 142             sim = self.run_tst_program(program, initial_regs, svstate,
 143                                        initial_cr=cr)
 144             self._check_regs(sim, expected_regs)
 145
 146     def tst_sv_add_2(self):
 147         # adds:
 148         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 149         #       r1 is scalar so ENDS EARLY
 150         isa = SVP64Asm(['svadd 1, 5.v, 9.v'
 151                        ])
 152         lst = list(isa)
 153         print ("listing", lst)
 154
 155         # initial values in GPR regfile
 156         initial_regs = [0] * 32
 157         initial_regs[9] = 0x1234
 158         initial_regs[10] = 0x1111
 159         initial_regs[5] = 0x4321
 160         initial_regs[6] = 0x2223
 161         # SVSTATE (in this case, VL=2)
 162         svstate = SVP64State()
 163         svstate.vl[0:7] = 2 # VL
 164         svstate.maxvl[0:7] = 2 # MAXVL
 165         print ("SVSTATE", bin(svstate.spr.asint()))
 166         # copy before running
 167         expected_regs = deepcopy(initial_regs)
 168         expected_regs[1] = 0x5555
 169
 170         with Program(lst, bigendian=False) as program:
 171             sim = self.run_tst_program(program, initial_regs, svstate)
 172             self._check_regs(sim, expected_regs)
 173
 174     def tst_sv_add_3(self):
 175         # adds:
 176         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 177         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
 178         isa = SVP64Asm(['svadd 1.v, 5, 9.v'
 179                        ])
 180         lst = list(isa)
 181         print ("listing", lst)
 182
 183         # initial values in GPR regfile
 184         initial_regs = [0] * 32
 185         initial_regs[9] = 0x1234
 186         initial_regs[10] = 0x1111
 187         initial_regs[5] = 0x4321
 188         initial_regs[6] = 0x2223
 189         # SVSTATE (in this case, VL=2)
 190         svstate = SVP64State()
 191         svstate.vl[0:7] = 2 # VL
 192         svstate.maxvl[0:7] = 2 # MAXVL
 193         print ("SVSTATE", bin(svstate.spr.asint()))
 194         # copy before running
 195         expected_regs = deepcopy(initial_regs)
 196         expected_regs[1] = 0x5555
 197         expected_regs[2] = 0x5432
 198
 199         with Program(lst, bigendian=False) as program:
 200             sim = self.run_tst_program(program, initial_regs, svstate)
 201             self._check_regs(sim, expected_regs)
 202
 203     def tst_sv_add_vl_0(self):
 204         # adds:
 205         #       none because VL is zer0
 206         isa = SVP64Asm(['svadd 1, 5.v, 9.v'
 207                        ])
 208         lst = list(isa)
 209         print ("listing", lst)
 210
 211         # initial values in GPR regfile
 212         initial_regs = [0] * 32
 213         initial_regs[9] = 0x1234
 214         initial_regs[10] = 0x1111
 215         initial_regs[5] = 0x4321
 216         initial_regs[6] = 0x2223
 217         # SVSTATE (in this case, VL=0)
 218         svstate = SVP64State()
 219         svstate.vl[0:7] = 0 # VL
 220         svstate.maxvl[0:7] = 0 # MAXVL
 221         print ("SVSTATE", bin(svstate.spr.asint()))
 222         # copy before running
 223         expected_regs = deepcopy(initial_regs)
 224
 225         with Program(lst, bigendian=False) as program:
 226             sim = self.run_tst_program(program, initial_regs, svstate)
 227             self._check_regs(sim, expected_regs)
 228
 229     def tst_sv_add_cr(self):
 230         # adds when Rc=1:                               TODO CRs higher up
 231         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
 232         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
 233         isa = SVP64Asm(['svadd. 1.v, 5.v, 9.v'
 234                        ])
 235         lst = list(isa)
 236         print ("listing", lst)
 237
 238         # initial values in GPR regfile
 239         initial_regs = [0] * 32
 240         initial_regs[9] = 0xffffffffffffffff
 241         initial_regs[10] = 0x1111
 242         initial_regs[5] = 0x1
 243         initial_regs[6] = 0x2223
 244         # SVSTATE (in this case, VL=2)
 245         svstate = SVP64State()
 246         svstate.vl[0:7] = 2 # VL
 247         svstate.maxvl[0:7] = 2 # MAXVL
 248         print ("SVSTATE", bin(svstate.spr.asint()))
 249         # copy before running
 250         expected_regs = deepcopy(initial_regs)
 251         expected_regs[1] = 0
 252         expected_regs[2] = 0x3334
 253
 254         with Program(lst, bigendian=False) as program:
 255             sim = self.run_tst_program(program, initial_regs, svstate)
 256             # XXX TODO, these need to move to higher range (offset)
 257             cr0_idx = SVP64CROffs.CR0
 258             cr1_idx = SVP64CROffs.CR1
 259             CR0 = sim.crl[cr0_idx].get_range().value
 260             CR1 = sim.crl[cr1_idx].get_range().value
 261             print ("CR0", CR0)
 262             print ("CR1", CR1)
 263             self._check_regs(sim, expected_regs)
 264             self.assertEqual(CR0, SelectableInt(2, 4))
 265             self.assertEqual(CR1, SelectableInt(4, 4))
 266
 267     def run_tst_program(self, prog, initial_regs=None,
 268                               svstate=None,
 269                               initial_cr=0):
 270         if initial_regs is None:
 271             initial_regs = [0] * 32
 272         simulator = run_tst(prog, initial_regs, svstate=svstate,
 273                             initial_cr=initial_cr)
 274         simulator.gpr.dump()
 275         return simulator
 276
 277
 278 if __name__ == "__main__":
 279     unittest.main()