220258e0a7e5e9faab40572e3ec842578b8e0603
1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from soc
.regfile
.regfiles
import XERRegs
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from soc
.experiment
.mem_types
import LDSTException
19 from soc
.decoder
.power_regspec_map
import regspec_decode_read
20 from soc
.decoder
.power_regspec_map
import regspec_decode_write
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
24 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
25 OutSel
, SPR
, RC
, LDSTMode
,
27 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
29 from soc
.sv
.svp64
import SVP64Rec
30 from soc
.consts
import MSR
32 from soc
.regfile
.regfiles
import FastRegs
33 from soc
.consts
import TT
34 from soc
.config
.state
import CoreState
35 from soc
.regfile
.util
import spr_to_fast
38 def decode_spr_num(spr
):
39 return Cat(spr
[5:10], spr
[0:5])
42 def instr_is_priv(m
, op
, insn
):
43 """determines if the instruction is privileged or not
46 is_priv_insn
= Signal(reset_less
=True)
48 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
49 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
50 comb
+= is_priv_insn
.eq(1)
52 #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
53 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
54 with m
.If(insn
[20]): # field XFX.spr[-1] i think
55 comb
+= is_priv_insn
.eq(1)
59 class SPRMap(Elaboratable
):
60 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
64 self
.spr_i
= Signal(10, reset_less
=True)
65 self
.spr_o
= Data(SPR
, name
="spr_o")
66 self
.fast_o
= Data(3, name
="fast_o")
68 def elaborate(self
, platform
):
70 with m
.Switch(self
.spr_i
):
71 for i
, x
in enumerate(SPR
):
73 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
74 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
75 for x
, v
in spr_to_fast
.items():
77 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
78 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
82 class SVP64RegExtra(Elaboratable
):
83 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
85 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
86 depending on info in one of the positions in the EXTRA field.
88 designed so that "no change" to the 5-bit register number occurs if
89 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
91 see https://libre-soc.org/openpower/sv/svp64/
94 self
.extra
= Signal(10, reset_less
=True)
95 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
96 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
97 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
98 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
99 self
.isvec
= Signal(1) # reg is marked as vector if true
101 def elaborate(self
, platform
):
105 # first get the spec. if not changed it's "scalar identity behaviour"
106 # which is zero which is ok.
109 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
110 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
111 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
112 # the register-extension information. extract those how
113 with m
.Switch(self
.etype
):
114 # 2-bit index selection mode
115 with m
.Case(SVEtype
.EXTRA2
):
116 with m
.Switch(self
.idx
):
117 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits
118 comb
+= spec
[1:3].eq(self
.extra
[0:2])
119 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits
120 comb
+= spec
[1:3].eq(self
.extra
[2:4])
121 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits
122 comb
+= spec
[1:3].eq(self
.extra
[4:6])
123 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits
124 comb
+= spec
[1:3].eq(self
.extra
[6:8])
125 # 3-bit index selection mode
126 with m
.Case(SVEtype
.EXTRA3
):
127 with m
.Switch(self
.idx
):
128 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits
129 comb
+= spec
.eq(self
.extra
[0:3])
130 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits
131 comb
+= spec
.eq(self
.extra
[3:6])
132 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits
133 comb
+= spec
.eq(self
.extra
[6:9])
134 # cannot fit more than 9 bits so there is no 4th thing
136 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
137 # from above, which (by design) has the effect of "no change", below.
139 # simple: isvec is top bit of spec
140 comb
+= self
.isvec
.eq(spec
[2])
142 # decode vector differently from scalar
143 with m
.If(self
.isvec
):
144 # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
145 comb
+= self
.reg_out
.eq(Cat(spec
[:2], self
.reg_in
))
147 # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
148 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec
[:2]))
153 class DecodeA(Elaboratable
):
154 """DecodeA from instruction
156 decodes register RA, implicit and explicit CSRs
159 def __init__(self
, dec
):
161 self
.sv_rm
= SVP64Rec() # SVP64 RM field
162 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
163 self
.insn_in
= Signal(32, reset_less
=True)
164 self
.reg_out
= Data(7, name
="reg_a")
165 self
.reg_isvec
= Signal(1, name
="reg_a_isvec") # TODO: in reg_out
166 self
.spr_out
= Data(SPR
, "spr_a")
167 self
.fast_out
= Data(3, "fast_a")
169 def elaborate(self
, platform
):
173 m
.submodules
.sprmap
= sprmap
= SPRMap()
174 m
.submodules
.svdec
= svdec
= SVP64RegExtra()
176 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
177 reg
= Signal(5, reset_less
=True)
179 # select Register A field
180 ra
= Signal(5, reset_less
=True)
181 comb
+= ra
.eq(self
.dec
.RA
)
182 with m
.If((self
.sel_in
== In1Sel
.RA
) |
183 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
184 (ra
!= Const(0, 5)))):
186 comb
+= self
.reg_out
.ok
.eq(1)
188 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
189 # moved it to 1st position (in1_sel)... because
190 rs
= Signal(5, reset_less
=True)
191 comb
+= rs
.eq(self
.dec
.RS
)
192 with m
.If(self
.sel_in
== In1Sel
.RS
):
194 comb
+= self
.reg_out
.ok
.eq(1)
196 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
197 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
198 # which in turn were auto-generated by sv_analysis.py
200 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
201 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
202 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
203 comb
+= svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
204 comb
+= svdec
.reg_in
.eq(reg
) # 5-bit (RA, RS)
206 # outputs: 7-bit reg number and whether it's vectorised
207 comb
+= self
.reg_out
.data
.eq(svdec
.reg_out
)
208 comb
+= self
.reg_isvec
.eq(svdec
.isvec
)
210 # decode Fast-SPR based on instruction type
211 with m
.Switch(op
.internal_op
):
213 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
214 with m
.Case(MicrOp
.OP_BC
):
215 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
217 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
218 comb
+= self
.fast_out
.ok
.eq(1)
219 with m
.Case(MicrOp
.OP_BCREG
):
220 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
221 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
222 with m
.If(xo9
& ~xo5
):
224 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
225 comb
+= self
.fast_out
.ok
.eq(1)
227 # MFSPR move from SPRs
228 with m
.Case(MicrOp
.OP_MFSPR
):
229 spr
= Signal(10, reset_less
=True)
230 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
231 comb
+= sprmap
.spr_i
.eq(spr
)
232 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
233 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
238 class DecodeAImm(Elaboratable
):
239 """DecodeA immediate from instruction
241 decodes register RA, whether immediate-zero, implicit and
245 def __init__(self
, dec
):
247 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
248 self
.immz_out
= Signal(reset_less
=True)
250 def elaborate(self
, platform
):
254 # zero immediate requested
255 ra
= Signal(5, reset_less
=True)
256 comb
+= ra
.eq(self
.dec
.RA
)
257 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
258 comb
+= self
.immz_out
.eq(1)
263 class DecodeB(Elaboratable
):
264 """DecodeB from instruction
266 decodes register RB, different forms of immediate (signed, unsigned),
267 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
268 by industry-standard convention, "lane 2" is where fully-decoded
269 immediates are muxed in.
272 def __init__(self
, dec
):
274 self
.sv_rm
= SVP64Rec() # SVP64 RM field
275 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
276 self
.insn_in
= Signal(32, reset_less
=True)
277 self
.reg_out
= Data(5, "reg_b")
278 self
.fast_out
= Data(3, "fast_b")
280 def elaborate(self
, platform
):
284 # select Register B field
285 with m
.Switch(self
.sel_in
):
286 with m
.Case(In2Sel
.RB
):
287 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
)
288 comb
+= self
.reg_out
.ok
.eq(1)
289 with m
.Case(In2Sel
.RS
):
290 # for M-Form shiftrot
291 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
292 comb
+= self
.reg_out
.ok
.eq(1)
294 # decode SPR2 based on instruction type
296 # BCREG implicitly uses LR or TAR for 2nd reg
297 # CTR however is already in fast_spr1 *not* 2.
298 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
299 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
300 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
302 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
303 comb
+= self
.fast_out
.ok
.eq(1)
305 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
306 comb
+= self
.fast_out
.ok
.eq(1)
311 class DecodeBImm(Elaboratable
):
312 """DecodeB immediate from instruction
314 def __init__(self
, dec
):
316 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
317 self
.imm_out
= Data(64, "imm_b")
319 def elaborate(self
, platform
):
323 # select Register B Immediate
324 with m
.Switch(self
.sel_in
):
325 with m
.Case(In2Sel
.CONST_UI
): # unsigned
326 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
327 comb
+= self
.imm_out
.ok
.eq(1)
328 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
329 si
= Signal(16, reset_less
=True)
330 comb
+= si
.eq(self
.dec
.SI
)
331 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
332 comb
+= self
.imm_out
.ok
.eq(1)
333 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
334 si_hi
= Signal(32, reset_less
=True)
335 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
336 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
337 comb
+= self
.imm_out
.ok
.eq(1)
338 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
339 ui
= Signal(16, reset_less
=True)
340 comb
+= ui
.eq(self
.dec
.UI
)
341 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
342 comb
+= self
.imm_out
.ok
.eq(1)
343 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
344 li
= Signal(26, reset_less
=True)
345 comb
+= li
.eq(self
.dec
.LI
<< 2)
346 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
347 comb
+= self
.imm_out
.ok
.eq(1)
348 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
349 bd
= Signal(16, reset_less
=True)
350 comb
+= bd
.eq(self
.dec
.BD
<< 2)
351 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
352 comb
+= self
.imm_out
.ok
.eq(1)
353 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
354 ds
= Signal(16, reset_less
=True)
355 comb
+= ds
.eq(self
.dec
.DS
<< 2)
356 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
357 comb
+= self
.imm_out
.ok
.eq(1)
358 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
359 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
360 comb
+= self
.imm_out
.ok
.eq(1)
361 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
362 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
363 comb
+= self
.imm_out
.ok
.eq(1)
364 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
365 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
366 comb
+= self
.imm_out
.ok
.eq(1)
371 class DecodeC(Elaboratable
):
372 """DecodeC from instruction
374 decodes register RC. this is "lane 3" into some CompUnits (not many)
377 def __init__(self
, dec
):
379 self
.sv_rm
= SVP64Rec() # SVP64 RM field
380 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
381 self
.insn_in
= Signal(32, reset_less
=True)
382 self
.reg_out
= Data(5, "reg_c")
384 def elaborate(self
, platform
):
388 # select Register C field
389 with m
.Switch(self
.sel_in
):
390 with m
.Case(In3Sel
.RB
):
391 # for M-Form shiftrot
392 comb
+= self
.reg_out
.data
.eq(self
.dec
.RB
)
393 comb
+= self
.reg_out
.ok
.eq(1)
394 with m
.Case(In3Sel
.RS
):
395 comb
+= self
.reg_out
.data
.eq(self
.dec
.RS
)
396 comb
+= self
.reg_out
.ok
.eq(1)
401 class DecodeOut(Elaboratable
):
402 """DecodeOut from instruction
404 decodes output register RA, RT or SPR
407 def __init__(self
, dec
):
409 self
.sv_rm
= SVP64Rec() # SVP64 RM field
410 self
.sel_in
= Signal(OutSel
, reset_less
=True)
411 self
.insn_in
= Signal(32, reset_less
=True)
412 self
.reg_out
= Data(5, "reg_o")
413 self
.spr_out
= Data(SPR
, "spr_o")
414 self
.fast_out
= Data(3, "fast_o")
416 def elaborate(self
, platform
):
419 m
.submodules
.sprmap
= sprmap
= SPRMap()
422 # select Register out field
423 with m
.Switch(self
.sel_in
):
424 with m
.Case(OutSel
.RT
):
425 comb
+= self
.reg_out
.data
.eq(self
.dec
.RT
)
426 comb
+= self
.reg_out
.ok
.eq(1)
427 with m
.Case(OutSel
.RA
):
428 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
429 comb
+= self
.reg_out
.ok
.eq(1)
430 with m
.Case(OutSel
.SPR
):
431 spr
= Signal(10, reset_less
=True)
432 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
433 # MFSPR move to SPRs - needs mapping
434 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
435 comb
+= sprmap
.spr_i
.eq(spr
)
436 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
437 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
439 with m
.Switch(op
.internal_op
):
441 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
442 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
443 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
445 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
446 comb
+= self
.fast_out
.ok
.eq(1)
448 # RFID 1st spr (fast)
449 with m
.Case(MicrOp
.OP_RFID
):
450 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
451 comb
+= self
.fast_out
.ok
.eq(1)
456 class DecodeOut2(Elaboratable
):
457 """DecodeOut2 from instruction
459 decodes output registers
462 def __init__(self
, dec
):
464 self
.sv_rm
= SVP64Rec() # SVP64 RM field
465 self
.sel_in
= Signal(OutSel
, reset_less
=True)
466 self
.lk
= Signal(reset_less
=True)
467 self
.insn_in
= Signal(32, reset_less
=True)
468 self
.reg_out
= Data(5, "reg_o")
469 self
.fast_out
= Data(3, "fast_o")
471 def elaborate(self
, platform
):
475 if hasattr(self
.dec
.op
, "upd"):
476 # update mode LD/ST uses read-reg A also as an output
477 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
478 comb
+= self
.reg_out
.eq(self
.dec
.RA
)
479 comb
+= self
.reg_out
.ok
.eq(1)
481 # B, BC or BCREG: potential implicit register (LR) output
482 # these give bl, bcl, bclrl, etc.
484 with m
.Switch(op
.internal_op
):
486 # BC* implicit register (LR)
487 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
488 with m
.If(self
.lk
): # "link" mode
489 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
490 comb
+= self
.fast_out
.ok
.eq(1)
492 # RFID 2nd spr (fast)
493 with m
.Case(MicrOp
.OP_RFID
):
494 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
495 comb
+= self
.fast_out
.ok
.eq(1)
500 class DecodeRC(Elaboratable
):
501 """DecodeRc from instruction
503 decodes Record bit Rc
506 def __init__(self
, dec
):
508 self
.sel_in
= Signal(RC
, reset_less
=True)
509 self
.insn_in
= Signal(32, reset_less
=True)
510 self
.rc_out
= Data(1, "rc")
512 def elaborate(self
, platform
):
516 # select Record bit out field
517 with m
.Switch(self
.sel_in
):
519 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
520 comb
+= self
.rc_out
.ok
.eq(1)
522 comb
+= self
.rc_out
.data
.eq(1)
523 comb
+= self
.rc_out
.ok
.eq(1)
524 with m
.Case(RC
.NONE
):
525 comb
+= self
.rc_out
.data
.eq(0)
526 comb
+= self
.rc_out
.ok
.eq(1)
531 class DecodeOE(Elaboratable
):
532 """DecodeOE from instruction
534 decodes OE field: uses RC decode detection which might not be good
536 -- For now, use "rc" in the decode table to decide whether oe exists.
537 -- This is not entirely correct architecturally: For mulhd and
538 -- mulhdu, the OE field is reserved. It remains to be seen what an
539 -- actual POWER9 does if we set it on those instructions, for now we
540 -- test that further down when assigning to the multiplier oe input.
543 def __init__(self
, dec
):
545 self
.sel_in
= Signal(RC
, reset_less
=True)
546 self
.insn_in
= Signal(32, reset_less
=True)
547 self
.oe_out
= Data(1, "oe")
549 def elaborate(self
, platform
):
554 with m
.Switch(op
.internal_op
):
556 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
558 # XXX ARGH! ignoring OE causes incompatibility with microwatt
559 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
560 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
561 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
562 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
563 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
564 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
568 # all other ops decode OE field
570 # select OE bit out field
571 with m
.Switch(self
.sel_in
):
573 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
574 comb
+= self
.oe_out
.ok
.eq(1)
579 class DecodeCRIn(Elaboratable
):
580 """Decodes input CR from instruction
582 CR indices - insn fields - (not the data *in* the CR) require only 3
583 bits because they refer to CR0-CR7
586 def __init__(self
, dec
):
588 self
.sv_rm
= SVP64Rec() # SVP64 RM field
589 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
590 self
.insn_in
= Signal(32, reset_less
=True)
591 self
.cr_bitfield
= Data(3, "cr_bitfield")
592 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
593 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
594 self
.whole_reg
= Data(8, "cr_fxm")
596 def elaborate(self
, platform
):
598 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
604 comb
+= self
.cr_bitfield
.ok
.eq(0)
605 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
606 comb
+= self
.whole_reg
.ok
.eq(0)
607 with m
.Switch(self
.sel_in
):
608 with m
.Case(CRInSel
.NONE
):
609 pass # No bitfield activated
610 with m
.Case(CRInSel
.CR0
):
611 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
612 comb
+= self
.cr_bitfield
.ok
.eq(1)
613 with m
.Case(CRInSel
.BI
):
614 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
615 comb
+= self
.cr_bitfield
.ok
.eq(1)
616 with m
.Case(CRInSel
.BFA
):
617 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
618 comb
+= self
.cr_bitfield
.ok
.eq(1)
619 with m
.Case(CRInSel
.BA_BB
):
620 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
621 comb
+= self
.cr_bitfield
.ok
.eq(1)
622 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
623 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
624 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
625 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
626 with m
.Case(CRInSel
.BC
):
627 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
628 comb
+= self
.cr_bitfield
.ok
.eq(1)
629 with m
.Case(CRInSel
.WHOLE_REG
):
630 comb
+= self
.whole_reg
.ok
.eq(1)
631 move_one
= Signal(reset_less
=True)
632 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
633 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
634 # must one-hot the FXM field
635 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
636 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
638 # otherwise use all of it
639 comb
+= self
.whole_reg
.data
.eq(0xff)
644 class DecodeCROut(Elaboratable
):
645 """Decodes input CR from instruction
647 CR indices - insn fields - (not the data *in* the CR) require only 3
648 bits because they refer to CR0-CR7
651 def __init__(self
, dec
):
653 self
.sv_rm
= SVP64Rec() # SVP64 RM field
654 self
.rc_in
= Signal(reset_less
=True)
655 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
656 self
.insn_in
= Signal(32, reset_less
=True)
657 self
.cr_bitfield
= Data(3, "cr_bitfield")
658 self
.whole_reg
= Data(8, "cr_fxm")
660 def elaborate(self
, platform
):
664 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
667 comb
+= self
.cr_bitfield
.ok
.eq(0)
668 comb
+= self
.whole_reg
.ok
.eq(0)
669 with m
.Switch(self
.sel_in
):
670 with m
.Case(CROutSel
.NONE
):
671 pass # No bitfield activated
672 with m
.Case(CROutSel
.CR0
):
673 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
674 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
675 with m
.Case(CROutSel
.BF
):
676 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
677 comb
+= self
.cr_bitfield
.ok
.eq(1)
678 with m
.Case(CROutSel
.BT
):
679 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
680 comb
+= self
.cr_bitfield
.ok
.eq(1)
681 with m
.Case(CROutSel
.WHOLE_REG
):
682 comb
+= self
.whole_reg
.ok
.eq(1)
683 move_one
= Signal(reset_less
=True)
684 comb
+= move_one
.eq(self
.insn_in
[20])
685 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
687 # must one-hot the FXM field
688 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
689 with m
.If(ppick
.en_o
):
690 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
692 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
694 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
696 # otherwise use all of it
697 comb
+= self
.whole_reg
.data
.eq(0xff)
701 # dictionary of Input Record field names that, if they exist,
702 # will need a corresponding CSV Decoder file column (actually, PowerOp)
703 # to be decoded (this includes the single bit names)
704 record_names
= {'insn_type': 'internal_op',
705 'fn_unit': 'function_unit',
709 'imm_data': 'in2_sel',
710 'invert_in': 'inv_a',
711 'invert_out': 'inv_out',
714 'output_carry': 'cry_out',
715 'input_carry': 'cry_in',
716 'is_32bit': 'is_32b',
719 'data_len': 'ldst_len',
720 'byte_reverse': 'br',
721 'sign_extend': 'sgn_ext',
726 class PowerDecodeSubset(Elaboratable
):
727 """PowerDecodeSubset: dynamic subset decoder
729 only fields actually requested are copied over. hence, "subset" (duh).
731 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
733 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
736 self
.fn_name
= fn_name
738 opkls
= Decode2ToOperand
739 self
.do
= opkls(fn_name
)
740 col_subset
= self
.get_col_subset(self
.do
)
742 # only needed for "main" PowerDecode2
744 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
746 # create decoder if one not already given
748 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
749 row_subset
=self
.rowsubsetfn
)
752 # state information needed by the Decoder
754 state
= CoreState("dec2")
757 def get_col_subset(self
, do
):
758 subset
= {'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
759 for k
, v
in record_names
.items():
762 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
765 def rowsubsetfn(self
, opcode
, row
):
766 return row
['unit'] == self
.fn_name
769 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
771 def needs_field(self
, field
, op_field
):
776 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
778 def do_copy(self
, field
, val
, final
=False):
779 if final
or self
.final
:
783 if hasattr(do
, field
) and val
is not None:
784 return getattr(do
, field
).eq(val
)
787 def op_get(self
, op_field
):
788 return getattr(self
.dec
.op
, op_field
, None)
790 def elaborate(self
, platform
):
794 op
, do
= self
.dec
.op
, self
.do
795 msr
, cia
= state
.msr
, state
.pc
797 # fill in for a normal instruction (not an exception)
798 # copy over if non-exception, non-privileged etc. is detected
800 if self
.fn_name
is None:
803 name
= self
.fn_name
+ "tmp"
804 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
806 # set up submodule decoders
807 m
.submodules
.dec
= self
.dec
808 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
809 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
810 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
811 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
813 # copy instruction through...
815 dec_rc
.insn_in
, dec_oe
.insn_in
,
816 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
]:
817 comb
+= i
.eq(self
.dec
.opcode_in
)
819 # ...and subdecoders' input fields
820 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
821 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
822 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
823 comb
+= self
.dec_cr_in
.sv_rm
.eq(self
.sv_rm
)
824 comb
+= self
.dec_cr_out
.sv_rm
.eq(self
.sv_rm
)
825 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
826 comb
+= self
.dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
829 comb
+= self
.do_copy("msr", msr
)
830 comb
+= self
.do_copy("cia", cia
)
832 # set up instruction type
833 # no op: defaults to OP_ILLEGAL
834 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
836 # function unit for decoded instruction: requires minor redirect
838 fn
= self
.op_get("function_unit")
839 spr
= Signal(10, reset_less
=True)
840 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
842 # for first test only forward SPRs 18 and 19 to MMU, when
843 # operation is MTSPR or MFSPR. TODO: add other MMU SPRs
844 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
845 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
846 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
))):
847 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
849 comb
+= self
.do_copy("fn_unit",fn
)
852 if self
.needs_field("zero_a", "in1_sel"):
853 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
854 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
855 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
856 if self
.needs_field("imm_data", "in2_sel"):
857 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
858 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
859 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
862 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
863 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
866 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
867 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
868 comb
+= self
.do_copy("write_cr0", self
.dec_cr_out
.cr_bitfield
.ok
)
870 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
871 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
873 # decoded/selected instruction flags
874 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
875 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
876 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
877 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
878 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
879 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
880 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
881 lk
= self
.op_get("lk")
884 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
886 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
887 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
888 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
893 class PowerDecode2(PowerDecodeSubset
):
894 """PowerDecode2: the main instruction decoder.
896 whilst PowerDecode is responsible for decoding the actual opcode, this
897 module encapsulates further specialist, sparse information and
898 expansion of fields that is inconvenient to have in the CSV files.
899 for example: the encoding of the immediates, which are detected
900 and expanded out to their full value from an annotated (enum)
903 implicit register usage is also set up, here. for example: OP_BC
904 requires implicitly reading CTR, OP_RFID requires implicitly writing
907 in addition, PowerDecoder2 is responsible for detecting whether
908 instructions are illegal (or privileged) or not, and instead of
909 just leaving at that, *replacing* the instruction to execute with
910 a suitable alternative (trap).
912 LDSTExceptions are done the cycle _after_ they're detected (after
913 they come out of LDSTCompUnit). basically despite the instruction
914 being decoded, the results of the decode are completely ignored
915 and "exception.happened" used to set the "actual" instruction to
916 "OP_TRAP". the LDSTException data structure gets filled in,
917 in the CompTrapOpSubset and that's what it fills in SRR.
919 to make this work, TestIssuer must notice "exception.happened"
920 after the (failed) LD/ST and copies the LDSTException info from
921 the output, into here (PowerDecoder2). without incrementing PC.
924 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
925 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
926 self
.exc
= LDSTException("dec2_exc")
928 def get_col_subset(self
, opkls
):
929 subset
= super().get_col_subset(opkls
)
930 subset
.add("asmcode")
931 subset
.add("in1_sel")
932 subset
.add("in2_sel")
933 subset
.add("in3_sel")
934 subset
.add("out_sel")
939 subset
.add("SV_Etype")
940 subset
.add("SV_Ptype")
942 subset
.add("internal_op")
946 def elaborate(self
, platform
):
947 m
= super().elaborate(platform
)
950 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
951 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
955 # fill in for a normal instruction (not an exception)
956 # copy over if non-exception, non-privileged etc. is detected
958 # set up submodule decoders
959 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
960 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
961 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
962 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
963 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
965 # copy instruction through...
966 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
967 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
968 comb
+= i
.eq(self
.dec
.opcode_in
)
971 for i
in [dec_a
.insn_in
, dec_b
.insn_in
,
972 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
973 comb
+= i
.eq(self
.sv_rm
)
975 # ...and subdecoders' input fields
976 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
977 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
978 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
979 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
980 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
981 if hasattr(do
, "lk"):
982 comb
+= dec_o2
.lk
.eq(do
.lk
)
984 # registers a, b, c and out and out2 (LD/ST EA)
985 for to_reg
, fromreg
in (
986 (e
.read_reg1
, dec_a
.reg_out
),
987 (e
.read_reg2
, dec_b
.reg_out
),
988 (e
.read_reg3
, dec_c
.reg_out
),
989 (e
.write_reg
, dec_o
.reg_out
),
990 (e
.write_ea
, dec_o2
.reg_out
)):
991 comb
+= to_reg
.data
.eq(fromreg
.data
)
992 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
995 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
996 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
999 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1000 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1001 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1002 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1004 # condition registers (CR)
1005 comb
+= e
.read_cr1
.eq(self
.dec_cr_in
.cr_bitfield
)
1006 comb
+= e
.read_cr2
.eq(self
.dec_cr_in
.cr_bitfield_b
)
1007 comb
+= e
.read_cr3
.eq(self
.dec_cr_in
.cr_bitfield_o
)
1008 comb
+= e
.write_cr
.eq(self
.dec_cr_out
.cr_bitfield
)
1010 # sigh this is exactly the sort of thing for which the
1011 # decoder is designed to not need. MTSPR, MFSPR and others need
1012 # access to the XER bits. however setting e.oe is not appropriate
1013 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1014 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1015 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1016 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1017 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1018 comb
+= e
.xer_out
.eq(1)
1020 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1021 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1022 # *DO NOT* call self.trap here. that would reset absolutely
1023 # everything including destroying read of RA and RB.
1024 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1026 ####################
1027 # ok so the instruction's been decoded, blah blah, however
1028 # now we need to determine if it's actually going to go ahead...
1029 # *or* if in fact it's a privileged operation, whether there's
1030 # an external interrupt, etc. etc. this is a simple priority
1031 # if-elif-elif sequence. decrement takes highest priority,
1032 # EINT next highest, privileged operation third.
1034 # check if instruction is privileged
1035 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1037 # different IRQ conditions
1038 ext_irq_ok
= Signal()
1039 dec_irq_ok
= Signal()
1044 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1045 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1046 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1047 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1049 # LD/ST exceptions. TestIssuer copies the exception info at us
1050 # after a failed LD/ST.
1051 with m
.If(exc
.happened
):
1052 with m
.If(exc
.alignment
):
1053 self
.trap(m
, TT
.PRIV
, 0x600)
1054 with m
.Elif(exc
.instr_fault
):
1055 with m
.If(exc
.segment_fault
):
1056 self
.trap(m
, TT
.PRIV
, 0x480)
1058 # pass exception info to trap to create SRR1
1059 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1061 with m
.If(exc
.segment_fault
):
1062 self
.trap(m
, TT
.PRIV
, 0x380)
1064 self
.trap(m
, TT
.PRIV
, 0x300)
1066 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1067 with m
.Elif(dec_irq_ok
):
1068 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1070 # external interrupt? only if MSR.EE set
1071 with m
.Elif(ext_irq_ok
):
1072 self
.trap(m
, TT
.EINT
, 0x500)
1074 # privileged instruction trap
1075 with m
.Elif(priv_ok
):
1076 self
.trap(m
, TT
.PRIV
, 0x700)
1078 # illegal instruction must redirect to trap. this is done by
1079 # *overwriting* the decoded instruction and starting again.
1080 # (note: the same goes for interrupts and for privileged operations,
1081 # just with different trapaddr and traptype)
1082 with m
.Elif(illeg_ok
):
1083 # illegal instruction trap
1084 self
.trap(m
, TT
.ILLEG
, 0x700)
1086 # no exception, just copy things to the output
1090 ####################
1091 # follow-up after trap/irq to set up SRR0/1
1093 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1094 # Note: OP_SC could actually be modified to just be a trap
1095 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1096 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1097 # TRAP write fast1 = SRR0
1098 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1099 comb
+= e_out
.write_fast1
.ok
.eq(1)
1100 # TRAP write fast2 = SRR1
1101 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1102 comb
+= e_out
.write_fast2
.ok
.eq(1)
1104 # RFID: needs to read SRR0/1
1105 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1106 # TRAP read fast1 = SRR0
1107 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1108 comb
+= e_out
.read_fast1
.ok
.eq(1)
1109 # TRAP read fast2 = SRR1
1110 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1111 comb
+= e_out
.read_fast2
.ok
.eq(1)
1113 # annoying simulator bug
1114 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1115 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1119 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1120 """trap: this basically "rewrites" the decoded instruction as a trap
1123 op
, e
= self
.dec
.op
, self
.e
1124 comb
+= e
.eq(0) # reset eeeeeverything
1127 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1128 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1129 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1130 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1131 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1132 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1133 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1134 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1137 def get_rdflags(e
, cu
):
1139 for idx
in range(cu
.n_src
):
1140 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1141 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1143 print("rdflags", rdl
)
1147 if __name__
== '__main__':
1148 pdecode
= create_pdecode()
1149 dec2
= PowerDecode2(pdecode
)
1150 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1151 with
open("dec2.il", "w") as f
: