bfe9eda4d3a29f6f6f37a3d4248248fcff6d0c90
1 """Power ISA Decoder second stage
3 based on Anton Blanchard microwatt decode2.vhdl
5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
6 over-riding the internal opcode when an exception is needed.
9 from nmigen
import Module
, Elaboratable
, Signal
, Mux
, Const
, Cat
, Repl
, Record
10 from nmigen
.cli
import rtlil
11 from soc
.regfile
.regfiles
import XERRegs
13 from nmutil
.picker
import PriorityPicker
14 from nmutil
.iocontrol
import RecordObject
15 from nmutil
.extend
import exts
17 from soc
.experiment
.mem_types
import LDSTException
19 from soc
.decoder
.power_regspec_map
import regspec_decode_read
20 from soc
.decoder
.power_regspec_map
import regspec_decode_write
21 from soc
.decoder
.power_decoder
import create_pdecode
22 from soc
.decoder
.power_enums
import (MicrOp
, CryIn
, Function
,
24 LdstLen
, In1Sel
, In2Sel
, In3Sel
,
25 OutSel
, SPR
, RC
, LDSTMode
,
27 from soc
.decoder
.decode2execute1
import (Decode2ToExecute1Type
, Data
,
29 from soc
.sv
.svp64
import SVP64Rec
30 from soc
.consts
import MSR
32 from soc
.regfile
.regfiles
import FastRegs
33 from soc
.consts
import TT
34 from soc
.config
.state
import CoreState
35 from soc
.regfile
.util
import spr_to_fast
38 def decode_spr_num(spr
):
39 return Cat(spr
[5:10], spr
[0:5])
42 def instr_is_priv(m
, op
, insn
):
43 """determines if the instruction is privileged or not
46 is_priv_insn
= Signal(reset_less
=True)
48 with m
.Case(MicrOp
.OP_ATTN
, MicrOp
.OP_MFMSR
, MicrOp
.OP_MTMSRD
,
49 MicrOp
.OP_MTMSR
, MicrOp
.OP_RFID
):
50 comb
+= is_priv_insn
.eq(1)
52 #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
53 with m
.Case(MicrOp
.OP_MFSPR
, MicrOp
.OP_MTSPR
):
54 with m
.If(insn
[20]): # field XFX.spr[-1] i think
55 comb
+= is_priv_insn
.eq(1)
59 class SPRMap(Elaboratable
):
60 """SPRMap: maps POWER9 SPR numbers to internal enum values, fast and slow
64 self
.spr_i
= Signal(10, reset_less
=True)
65 self
.spr_o
= Data(SPR
, name
="spr_o")
66 self
.fast_o
= Data(3, name
="fast_o")
68 def elaborate(self
, platform
):
70 with m
.Switch(self
.spr_i
):
71 for i
, x
in enumerate(SPR
):
73 m
.d
.comb
+= self
.spr_o
.data
.eq(i
)
74 m
.d
.comb
+= self
.spr_o
.ok
.eq(1)
75 for x
, v
in spr_to_fast
.items():
77 m
.d
.comb
+= self
.fast_o
.data
.eq(v
)
78 m
.d
.comb
+= self
.fast_o
.ok
.eq(1)
82 class SVP64ExtraSpec(Elaboratable
):
83 """SVP64ExtraSpec - decodes SVP64 Extra specification.
85 selects the required EXTRA2/3 field.
87 see https://libre-soc.org/openpower/sv/svp64/
90 self
.extra
= Signal(10, reset_less
=True)
91 self
.etype
= Signal(SVEtype
, reset_less
=True) # 2 or 3 bits
92 self
.idx
= Signal(SVEXTRA
, reset_less
=True) # which part of extra
93 self
.spec
= Signal(3) # EXTRA spec for the register
95 def elaborate(self
, platform
):
100 # back in the LDSTRM-* and RM-* files generated by sv_analysis.py
101 # we marked every op with an Etype: EXTRA2 or EXTRA3, and also said
102 # which of the 4 (or 3 for EXTRA3) sub-fields of bits 10:18 contain
103 # the register-extension information. extract those now
104 with m
.Switch(self
.etype
):
105 # 2-bit index selection mode
106 with m
.Case(SVEtype
.EXTRA2
):
107 with m
.Switch(self
.idx
):
108 with m
.Case(SVEXTRA
.Idx0
): # 1st 2 bits
109 comb
+= spec
[1:3].eq(self
.extra
[0:2])
110 with m
.Case(SVEXTRA
.Idx1
): # 2nd 2 bits
111 comb
+= spec
[1:3].eq(self
.extra
[2:4])
112 with m
.Case(SVEXTRA
.Idx2
): # 3rd 2 bits
113 comb
+= spec
[1:3].eq(self
.extra
[4:6])
114 with m
.Case(SVEXTRA
.Idx3
): # 4th 2 bits
115 comb
+= spec
[1:3].eq(self
.extra
[6:8])
116 # 3-bit index selection mode
117 with m
.Case(SVEtype
.EXTRA3
):
118 with m
.Switch(self
.idx
):
119 with m
.Case(SVEXTRA
.Idx0
): # 1st 3 bits
120 comb
+= spec
.eq(self
.extra
[0:3])
121 with m
.Case(SVEXTRA
.Idx1
): # 2nd 3 bits
122 comb
+= spec
.eq(self
.extra
[3:6])
123 with m
.Case(SVEXTRA
.Idx2
): # 3rd 3 bits
124 comb
+= spec
.eq(self
.extra
[6:9])
125 # cannot fit more than 9 bits so there is no 4th thing
130 class SVP64RegExtra(SVP64ExtraSpec
):
131 """SVP64RegExtra - decodes SVP64 Extra fields to determine reg extension
133 incoming 5-bit GPR/FP is turned into a 7-bit and marked as scalar/vector
134 depending on info in one of the positions in the EXTRA field.
136 designed so that "no change" to the 5-bit register number occurs if
137 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
139 see https://libre-soc.org/openpower/sv/svp64/
142 SVP64ExtraSpec
.__init
__(self
)
143 self
.reg_in
= Signal(5) # incoming reg number (5 bits, RA, RB)
144 self
.reg_out
= Signal(7) # extra-augmented output (7 bits)
145 self
.isvec
= Signal(1) # reg is marked as vector if true
147 def elaborate(self
, platform
):
148 m
= super().elaborate(platform
) # select required EXTRA2/3
151 # first get the spec. if not changed it's "scalar identity behaviour"
152 # which is zero which is ok.
155 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
156 # from above, which (by design) has the effect of "no change", below.
158 # simple: isvec is top bit of spec
159 comb
+= self
.isvec
.eq(spec
[2])
161 # decode vector differently from scalar
162 with m
.If(self
.isvec
):
163 # Vector: shifted up, extra in LSBs (RA << 2) | spec[0:1]
164 comb
+= self
.reg_out
.eq(Cat(spec
[:2], self
.reg_in
))
166 # Scalar: not shifted up, extra in MSBs RA | (spec[0:1] << 5)
167 comb
+= self
.reg_out
.eq(Cat(self
.reg_in
, spec
[:2]))
172 class SVP64CRExtra(SVP64ExtraSpec
):
173 """SVP64CRExtra - decodes SVP64 Extra fields to determine CR extension
175 incoming 3-bit CR is turned into a 7-bit and marked as scalar/vector
176 depending on info in one of the positions in the EXTRA field.
178 yes, really, 128 CRs. INT is 128, FP is 128, therefore CRs are 128.
180 designed so that "no change" to the 3-bit CR register number occurs if
181 SV either does not apply or the relevant EXTRA2/3 field bits are zero.
183 see https://libre-soc.org/openpower/sv/svp64/appendix
186 SVP64ExtraSpec
.__init
__(self
)
187 self
.cr_in
= Signal(3) # incoming CR number (3 bits, BA[2:5], BFA)
188 self
.cr_out
= Signal(7) # extra-augmented CR output (7 bits)
189 self
.isvec
= Signal(1) # reg is marked as vector if true
191 def elaborate(self
, platform
):
192 m
= super().elaborate(platform
) # select required EXTRA2/3
195 # first get the spec. if not changed it's "scalar identity behaviour"
196 # which is zero which is ok.
199 # now decode it. bit 2 is "scalar/vector". note that spec could be zero
200 # from above, which (by design) has the effect of "no change", below.
202 # simple: isvec is top bit of spec
203 comb
+= self
.isvec
.eq(spec
[2])
205 # decode vector differently from scalar, insert bits 0 and 1 accordingly
206 with m
.If(self
.isvec
):
207 # Vector: shifted up, extra in LSBs (CR << 4) | (spec[0:1] << 2)
208 comb
+= self
.cr_out
.eq(Cat(Const(0, 2), spec
[:2], self
.cr_in
))
210 # Scalar: not shifted up, extra in MSBs CR | (spec[0:1] << 3)
211 comb
+= self
.cr_out
.eq(Cat(self
.cr_in
, spec
[:2]))
216 class DecodeA(Elaboratable
):
217 """DecodeA from instruction
219 decodes register RA, implicit and explicit CSRs
222 def __init__(self
, dec
):
224 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
225 self
.insn_in
= Signal(32, reset_less
=True)
226 self
.reg_out
= Data(5, name
="reg_a")
227 self
.spr_out
= Data(SPR
, "spr_a")
228 self
.fast_out
= Data(3, "fast_a")
230 def elaborate(self
, platform
):
235 m
.submodules
.sprmap
= sprmap
= SPRMap()
237 # select Register A field
238 ra
= Signal(5, reset_less
=True)
239 comb
+= ra
.eq(self
.dec
.RA
)
240 with m
.If((self
.sel_in
== In1Sel
.RA
) |
241 ((self
.sel_in
== In1Sel
.RA_OR_ZERO
) &
242 (ra
!= Const(0, 5)))):
243 comb
+= reg
.data
.eq(ra
)
246 # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
247 # moved it to 1st position (in1_sel)... because
248 rs
= Signal(5, reset_less
=True)
249 comb
+= rs
.eq(self
.dec
.RS
)
250 with m
.If(self
.sel_in
== In1Sel
.RS
):
251 comb
+= reg
.data
.eq(rs
)
254 # decode Fast-SPR based on instruction type
255 with m
.Switch(op
.internal_op
):
257 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
258 with m
.Case(MicrOp
.OP_BC
):
259 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
261 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
262 comb
+= self
.fast_out
.ok
.eq(1)
263 with m
.Case(MicrOp
.OP_BCREG
):
264 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
265 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
266 with m
.If(xo9
& ~xo5
):
268 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
269 comb
+= self
.fast_out
.ok
.eq(1)
271 # MFSPR move from SPRs
272 with m
.Case(MicrOp
.OP_MFSPR
):
273 spr
= Signal(10, reset_less
=True)
274 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
275 comb
+= sprmap
.spr_i
.eq(spr
)
276 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
277 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
282 class DecodeAImm(Elaboratable
):
283 """DecodeA immediate from instruction
285 decodes register RA, whether immediate-zero, implicit and
289 def __init__(self
, dec
):
291 self
.sel_in
= Signal(In1Sel
, reset_less
=True)
292 self
.immz_out
= Signal(reset_less
=True)
294 def elaborate(self
, platform
):
298 # zero immediate requested
299 ra
= Signal(5, reset_less
=True)
300 comb
+= ra
.eq(self
.dec
.RA
)
301 with m
.If((self
.sel_in
== In1Sel
.RA_OR_ZERO
) & (ra
== Const(0, 5))):
302 comb
+= self
.immz_out
.eq(1)
307 class DecodeB(Elaboratable
):
308 """DecodeB from instruction
310 decodes register RB, different forms of immediate (signed, unsigned),
311 and implicit SPRs. register B is basically "lane 2" into the CompUnits.
312 by industry-standard convention, "lane 2" is where fully-decoded
313 immediates are muxed in.
316 def __init__(self
, dec
):
318 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
319 self
.insn_in
= Signal(32, reset_less
=True)
320 self
.reg_out
= Data(7, "reg_b")
321 self
.reg_isvec
= Signal(1, name
="reg_b_isvec") # TODO: in reg_out
322 self
.fast_out
= Data(3, "fast_b")
324 def elaborate(self
, platform
):
330 # select Register B field
331 with m
.Switch(self
.sel_in
):
332 with m
.Case(In2Sel
.RB
):
333 comb
+= reg
.data
.eq(self
.dec
.RB
)
335 with m
.Case(In2Sel
.RS
):
336 # for M-Form shiftrot
337 comb
+= reg
.data
.eq(self
.dec
.RS
)
340 # decode SPR2 based on instruction type
341 # BCREG implicitly uses LR or TAR for 2nd reg
342 # CTR however is already in fast_spr1 *not* 2.
343 with m
.If(op
.internal_op
== MicrOp
.OP_BCREG
):
344 xo9
= self
.dec
.FormXL
.XO
[9] # 3.0B p38 top bit of XO
345 xo5
= self
.dec
.FormXL
.XO
[5] # 3.0B p38
347 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
)
348 comb
+= self
.fast_out
.ok
.eq(1)
350 comb
+= self
.fast_out
.data
.eq(FastRegs
.TAR
)
351 comb
+= self
.fast_out
.ok
.eq(1)
356 class DecodeBImm(Elaboratable
):
357 """DecodeB immediate from instruction
359 def __init__(self
, dec
):
361 self
.sel_in
= Signal(In2Sel
, reset_less
=True)
362 self
.imm_out
= Data(64, "imm_b")
364 def elaborate(self
, platform
):
368 # select Register B Immediate
369 with m
.Switch(self
.sel_in
):
370 with m
.Case(In2Sel
.CONST_UI
): # unsigned
371 comb
+= self
.imm_out
.data
.eq(self
.dec
.UI
)
372 comb
+= self
.imm_out
.ok
.eq(1)
373 with m
.Case(In2Sel
.CONST_SI
): # sign-extended 16-bit
374 si
= Signal(16, reset_less
=True)
375 comb
+= si
.eq(self
.dec
.SI
)
376 comb
+= self
.imm_out
.data
.eq(exts(si
, 16, 64))
377 comb
+= self
.imm_out
.ok
.eq(1)
378 with m
.Case(In2Sel
.CONST_SI_HI
): # sign-extended 16+16=32 bit
379 si_hi
= Signal(32, reset_less
=True)
380 comb
+= si_hi
.eq(self
.dec
.SI
<< 16)
381 comb
+= self
.imm_out
.data
.eq(exts(si_hi
, 32, 64))
382 comb
+= self
.imm_out
.ok
.eq(1)
383 with m
.Case(In2Sel
.CONST_UI_HI
): # unsigned
384 ui
= Signal(16, reset_less
=True)
385 comb
+= ui
.eq(self
.dec
.UI
)
386 comb
+= self
.imm_out
.data
.eq(ui
<< 16)
387 comb
+= self
.imm_out
.ok
.eq(1)
388 with m
.Case(In2Sel
.CONST_LI
): # sign-extend 24+2=26 bit
389 li
= Signal(26, reset_less
=True)
390 comb
+= li
.eq(self
.dec
.LI
<< 2)
391 comb
+= self
.imm_out
.data
.eq(exts(li
, 26, 64))
392 comb
+= self
.imm_out
.ok
.eq(1)
393 with m
.Case(In2Sel
.CONST_BD
): # sign-extend (14+2)=16 bit
394 bd
= Signal(16, reset_less
=True)
395 comb
+= bd
.eq(self
.dec
.BD
<< 2)
396 comb
+= self
.imm_out
.data
.eq(exts(bd
, 16, 64))
397 comb
+= self
.imm_out
.ok
.eq(1)
398 with m
.Case(In2Sel
.CONST_DS
): # sign-extended (14+2=16) bit
399 ds
= Signal(16, reset_less
=True)
400 comb
+= ds
.eq(self
.dec
.DS
<< 2)
401 comb
+= self
.imm_out
.data
.eq(exts(ds
, 16, 64))
402 comb
+= self
.imm_out
.ok
.eq(1)
403 with m
.Case(In2Sel
.CONST_M1
): # signed (-1)
404 comb
+= self
.imm_out
.data
.eq(~
Const(0, 64)) # all 1s
405 comb
+= self
.imm_out
.ok
.eq(1)
406 with m
.Case(In2Sel
.CONST_SH
): # unsigned - for shift
407 comb
+= self
.imm_out
.data
.eq(self
.dec
.sh
)
408 comb
+= self
.imm_out
.ok
.eq(1)
409 with m
.Case(In2Sel
.CONST_SH32
): # unsigned - for shift
410 comb
+= self
.imm_out
.data
.eq(self
.dec
.SH32
)
411 comb
+= self
.imm_out
.ok
.eq(1)
416 class DecodeC(Elaboratable
):
417 """DecodeC from instruction
419 decodes register RC. this is "lane 3" into some CompUnits (not many)
422 def __init__(self
, dec
):
424 self
.sel_in
= Signal(In3Sel
, reset_less
=True)
425 self
.insn_in
= Signal(32, reset_less
=True)
426 self
.reg_out
= Data(5, "reg_c")
428 def elaborate(self
, platform
):
434 # select Register C field
435 with m
.Switch(self
.sel_in
):
436 with m
.Case(In3Sel
.RB
):
437 # for M-Form shiftrot
438 comb
+= reg
.data
.eq(self
.dec
.RB
)
440 with m
.Case(In3Sel
.RS
):
441 comb
+= reg
.data
.eq(self
.dec
.RS
)
447 class DecodeOut(Elaboratable
):
448 """DecodeOut from instruction
450 decodes output register RA, RT or SPR
453 def __init__(self
, dec
):
455 self
.sel_in
= Signal(OutSel
, reset_less
=True)
456 self
.insn_in
= Signal(32, reset_less
=True)
457 self
.reg_out
= Data(5, "reg_o")
458 self
.spr_out
= Data(SPR
, "spr_o")
459 self
.fast_out
= Data(3, "fast_o")
461 def elaborate(self
, platform
):
464 m
.submodules
.sprmap
= sprmap
= SPRMap()
468 # select Register out field
469 with m
.Switch(self
.sel_in
):
470 with m
.Case(OutSel
.RT
):
471 comb
+= reg
.data
.eq(self
.dec
.RT
)
473 with m
.Case(OutSel
.RA
):
474 comb
+= reg
.data
.eq(self
.dec
.RA
)
476 with m
.Case(OutSel
.SPR
):
477 spr
= Signal(10, reset_less
=True)
478 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
479 # MFSPR move to SPRs - needs mapping
480 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
481 comb
+= sprmap
.spr_i
.eq(spr
)
482 comb
+= self
.spr_out
.eq(sprmap
.spr_o
)
483 comb
+= self
.fast_out
.eq(sprmap
.fast_o
)
486 with m
.Switch(op
.internal_op
):
488 # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
489 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_BCREG
):
490 with m
.If(~self
.dec
.BO
[2]): # 3.0B p38 BO2=0, use CTR reg
492 comb
+= self
.fast_out
.data
.eq(FastRegs
.CTR
)
493 comb
+= self
.fast_out
.ok
.eq(1)
495 # RFID 1st spr (fast)
496 with m
.Case(MicrOp
.OP_RFID
):
497 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
498 comb
+= self
.fast_out
.ok
.eq(1)
503 class DecodeOut2(Elaboratable
):
504 """DecodeOut2 from instruction
506 decodes output registers (2nd one). note that RA is *implicit* below,
507 which now causes problems with SVP64
509 TODO: SVP64 is a little more complex, here. svp64 allows extending
510 by one more destination by having one more EXTRA field. RA-as-src
511 is not the same as RA-as-dest. limited in that it's the same first
512 5 bits (from the v3.0B opcode), but still kinda cool. mostly used
513 for operations that have src-as-dest: mostly this is LD/ST-with-update
514 but there are others.
517 def __init__(self
, dec
):
519 self
.sel_in
= Signal(OutSel
, reset_less
=True)
520 self
.lk
= Signal(reset_less
=True)
521 self
.insn_in
= Signal(32, reset_less
=True)
522 self
.reg_out
= Data(5, "reg_o2")
523 self
.fast_out
= Data(3, "fast_o2")
525 def elaborate(self
, platform
):
529 #m.submodules.svdec = svdec = SVP64RegExtra()
531 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
532 #reg = Signal(5, reset_less=True)
534 if hasattr(self
.dec
.op
, "upd"):
535 # update mode LD/ST uses read-reg A also as an output
536 with m
.If(self
.dec
.op
.upd
== LDSTMode
.update
):
537 comb
+= self
.reg_out
.data
.eq(self
.dec
.RA
)
538 comb
+= self
.reg_out
.ok
.eq(1)
540 # B, BC or BCREG: potential implicit register (LR) output
541 # these give bl, bcl, bclrl, etc.
542 with m
.Switch(op
.internal_op
):
544 # BC* implicit register (LR)
545 with m
.Case(MicrOp
.OP_BC
, MicrOp
.OP_B
, MicrOp
.OP_BCREG
):
546 with m
.If(self
.lk
): # "link" mode
547 comb
+= self
.fast_out
.data
.eq(FastRegs
.LR
) # constant: LR
548 comb
+= self
.fast_out
.ok
.eq(1)
550 # RFID 2nd spr (fast)
551 with m
.Case(MicrOp
.OP_RFID
):
552 comb
+= self
.fast_out
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
553 comb
+= self
.fast_out
.ok
.eq(1)
558 class DecodeRC(Elaboratable
):
559 """DecodeRc from instruction
561 decodes Record bit Rc
564 def __init__(self
, dec
):
566 self
.sel_in
= Signal(RC
, reset_less
=True)
567 self
.insn_in
= Signal(32, reset_less
=True)
568 self
.rc_out
= Data(1, "rc")
570 def elaborate(self
, platform
):
574 # select Record bit out field
575 with m
.Switch(self
.sel_in
):
577 comb
+= self
.rc_out
.data
.eq(self
.dec
.Rc
)
578 comb
+= self
.rc_out
.ok
.eq(1)
580 comb
+= self
.rc_out
.data
.eq(1)
581 comb
+= self
.rc_out
.ok
.eq(1)
582 with m
.Case(RC
.NONE
):
583 comb
+= self
.rc_out
.data
.eq(0)
584 comb
+= self
.rc_out
.ok
.eq(1)
589 class DecodeOE(Elaboratable
):
590 """DecodeOE from instruction
592 decodes OE field: uses RC decode detection which might not be good
594 -- For now, use "rc" in the decode table to decide whether oe exists.
595 -- This is not entirely correct architecturally: For mulhd and
596 -- mulhdu, the OE field is reserved. It remains to be seen what an
597 -- actual POWER9 does if we set it on those instructions, for now we
598 -- test that further down when assigning to the multiplier oe input.
601 def __init__(self
, dec
):
603 self
.sel_in
= Signal(RC
, reset_less
=True)
604 self
.insn_in
= Signal(32, reset_less
=True)
605 self
.oe_out
= Data(1, "oe")
607 def elaborate(self
, platform
):
612 with m
.Switch(op
.internal_op
):
614 # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
616 # XXX ARGH! ignoring OE causes incompatibility with microwatt
617 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
618 with m
.Case(MicrOp
.OP_MUL_H64
, MicrOp
.OP_MUL_H32
,
619 MicrOp
.OP_EXTS
, MicrOp
.OP_CNTZ
,
620 MicrOp
.OP_SHL
, MicrOp
.OP_SHR
, MicrOp
.OP_RLC
,
621 MicrOp
.OP_LOAD
, MicrOp
.OP_STORE
,
622 MicrOp
.OP_RLCL
, MicrOp
.OP_RLCR
,
626 # all other ops decode OE field
628 # select OE bit out field
629 with m
.Switch(self
.sel_in
):
631 comb
+= self
.oe_out
.data
.eq(self
.dec
.OE
)
632 comb
+= self
.oe_out
.ok
.eq(1)
637 class DecodeCRIn(Elaboratable
):
638 """Decodes input CR from instruction
640 CR indices - insn fields - (not the data *in* the CR) require only 3
641 bits because they refer to CR0-CR7
644 def __init__(self
, dec
):
646 self
.sel_in
= Signal(CRInSel
, reset_less
=True)
647 self
.insn_in
= Signal(32, reset_less
=True)
648 self
.cr_bitfield
= Data(3, "cr_bitfield")
649 self
.cr_bitfield_b
= Data(3, "cr_bitfield_b")
650 self
.cr_bitfield_o
= Data(3, "cr_bitfield_o")
651 self
.whole_reg
= Data(8, "cr_fxm")
653 def elaborate(self
, platform
):
657 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
660 # zero-initialisation
661 comb
+= self
.cr_bitfield
.ok
.eq(0)
662 comb
+= self
.cr_bitfield_b
.ok
.eq(0)
663 comb
+= self
.cr_bitfield_o
.ok
.eq(0)
664 comb
+= self
.whole_reg
.ok
.eq(0)
666 # select the relevant CR bitfields
667 with m
.Switch(self
.sel_in
):
668 with m
.Case(CRInSel
.NONE
):
669 pass # No bitfield activated
670 with m
.Case(CRInSel
.CR0
):
671 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
672 comb
+= self
.cr_bitfield
.ok
.eq(1)
673 with m
.Case(CRInSel
.BI
):
674 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BI
[2:5])
675 comb
+= self
.cr_bitfield
.ok
.eq(1)
676 with m
.Case(CRInSel
.BFA
):
677 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BFA
)
678 comb
+= self
.cr_bitfield
.ok
.eq(1)
679 with m
.Case(CRInSel
.BA_BB
):
680 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BA
[2:5])
681 comb
+= self
.cr_bitfield
.ok
.eq(1)
682 comb
+= self
.cr_bitfield_b
.data
.eq(self
.dec
.BB
[2:5])
683 comb
+= self
.cr_bitfield_b
.ok
.eq(1)
684 comb
+= self
.cr_bitfield_o
.data
.eq(self
.dec
.BT
[2:5])
685 comb
+= self
.cr_bitfield_o
.ok
.eq(1)
686 with m
.Case(CRInSel
.BC
):
687 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.BC
[2:5])
688 comb
+= self
.cr_bitfield
.ok
.eq(1)
689 with m
.Case(CRInSel
.WHOLE_REG
):
690 comb
+= self
.whole_reg
.ok
.eq(1)
691 move_one
= Signal(reset_less
=True)
692 comb
+= move_one
.eq(self
.insn_in
[20]) # MSB0 bit 11
693 with m
.If((op
.internal_op
== MicrOp
.OP_MFCR
) & move_one
):
694 # must one-hot the FXM field
695 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
696 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
698 # otherwise use all of it
699 comb
+= self
.whole_reg
.data
.eq(0xff)
704 class DecodeCROut(Elaboratable
):
705 """Decodes input CR from instruction
707 CR indices - insn fields - (not the data *in* the CR) require only 3
708 bits because they refer to CR0-CR7
711 def __init__(self
, dec
):
713 self
.rc_in
= Signal(reset_less
=True)
714 self
.sel_in
= Signal(CROutSel
, reset_less
=True)
715 self
.insn_in
= Signal(32, reset_less
=True)
716 self
.cr_bitfield
= Data(3, "cr_bitfield")
717 self
.whole_reg
= Data(8, "cr_fxm")
719 def elaborate(self
, platform
):
723 m
.submodules
.ppick
= ppick
= PriorityPicker(8, reverse_i
=True,
726 comb
+= self
.cr_bitfield
.ok
.eq(0)
727 comb
+= self
.whole_reg
.ok
.eq(0)
729 with m
.Switch(self
.sel_in
):
730 with m
.Case(CROutSel
.NONE
):
731 pass # No bitfield activated
732 with m
.Case(CROutSel
.CR0
):
733 comb
+= self
.cr_bitfield
.data
.eq(0) # CR0 (MSB0 numbering)
734 comb
+= self
.cr_bitfield
.ok
.eq(self
.rc_in
) # only when RC=1
735 with m
.Case(CROutSel
.BF
):
736 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormX
.BF
)
737 comb
+= self
.cr_bitfield
.ok
.eq(1)
738 with m
.Case(CROutSel
.BT
):
739 comb
+= self
.cr_bitfield
.data
.eq(self
.dec
.FormXL
.BT
[2:5])
740 comb
+= self
.cr_bitfield
.ok
.eq(1)
741 with m
.Case(CROutSel
.WHOLE_REG
):
742 comb
+= self
.whole_reg
.ok
.eq(1)
743 move_one
= Signal(reset_less
=True)
744 comb
+= move_one
.eq(self
.insn_in
[20])
745 with m
.If((op
.internal_op
== MicrOp
.OP_MTCRF
)):
747 # must one-hot the FXM field
748 comb
+= ppick
.i
.eq(self
.dec
.FXM
)
749 with m
.If(ppick
.en_o
):
750 comb
+= self
.whole_reg
.data
.eq(ppick
.o
)
752 comb
+= self
.whole_reg
.data
.eq(0b00000001) # CR7
754 comb
+= self
.whole_reg
.data
.eq(self
.dec
.FXM
)
756 # otherwise use all of it
757 comb
+= self
.whole_reg
.data
.eq(0xff)
761 # dictionary of Input Record field names that, if they exist,
762 # will need a corresponding CSV Decoder file column (actually, PowerOp)
763 # to be decoded (this includes the single bit names)
764 record_names
= {'insn_type': 'internal_op',
765 'fn_unit': 'function_unit',
769 'imm_data': 'in2_sel',
770 'invert_in': 'inv_a',
771 'invert_out': 'inv_out',
774 'output_carry': 'cry_out',
775 'input_carry': 'cry_in',
776 'is_32bit': 'is_32b',
779 'data_len': 'ldst_len',
780 'byte_reverse': 'br',
781 'sign_extend': 'sgn_ext',
786 class PowerDecodeSubset(Elaboratable
):
787 """PowerDecodeSubset: dynamic subset decoder
789 only fields actually requested are copied over. hence, "subset" (duh).
791 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
793 self
.sv_rm
= SVP64Rec(name
="dec_svp64") # SVP64 RM field
796 self
.fn_name
= fn_name
798 opkls
= Decode2ToOperand
799 self
.do
= opkls(fn_name
)
800 col_subset
= self
.get_col_subset(self
.do
)
802 # only needed for "main" PowerDecode2
804 self
.e
= Decode2ToExecute1Type(name
=self
.fn_name
, do
=self
.do
)
806 # create decoder if one not already given
808 dec
= create_pdecode(name
=fn_name
, col_subset
=col_subset
,
809 row_subset
=self
.rowsubsetfn
)
812 # state information needed by the Decoder
814 state
= CoreState("dec2")
817 def get_col_subset(self
, do
):
818 subset
= { 'cr_in', 'cr_out', 'rc_sel'} # needed, non-optional
819 for k
, v
in record_names
.items():
822 print ("get_col_subset", self
.fn_name
, do
.fields
, subset
)
825 def rowsubsetfn(self
, opcode
, row
):
826 return row
['unit'] == self
.fn_name
829 return self
.dec
.ports() + self
.e
.ports() + self
.sv_rm
.ports()
831 def needs_field(self
, field
, op_field
):
836 return hasattr(do
, field
) and self
.op_get(op_field
) is not None
838 def do_copy(self
, field
, val
, final
=False):
839 if final
or self
.final
:
843 if hasattr(do
, field
) and val
is not None:
844 return getattr(do
, field
).eq(val
)
847 def op_get(self
, op_field
):
848 return getattr(self
.dec
.op
, op_field
, None)
850 def elaborate(self
, platform
):
854 op
, do
= self
.dec
.op
, self
.do
855 msr
, cia
= state
.msr
, state
.pc
857 # fill in for a normal instruction (not an exception)
858 # copy over if non-exception, non-privileged etc. is detected
860 if self
.fn_name
is None:
863 name
= self
.fn_name
+ "tmp"
864 self
.e_tmp
= Decode2ToExecute1Type(name
=name
, opkls
=self
.opkls
)
866 # set up submodule decoders
867 m
.submodules
.dec
= self
.dec
868 m
.submodules
.dec_rc
= dec_rc
= DecodeRC(self
.dec
)
869 m
.submodules
.dec_oe
= dec_oe
= DecodeOE(self
.dec
)
870 m
.submodules
.dec_cr_in
= self
.dec_cr_in
= DecodeCRIn(self
.dec
)
871 m
.submodules
.dec_cr_out
= self
.dec_cr_out
= DecodeCROut(self
.dec
)
873 # copy instruction through...
875 dec_rc
.insn_in
, dec_oe
.insn_in
,
876 self
.dec_cr_in
.insn_in
, self
.dec_cr_out
.insn_in
]:
877 comb
+= i
.eq(self
.dec
.opcode_in
)
879 # ...and subdecoders' input fields
880 comb
+= dec_rc
.sel_in
.eq(op
.rc_sel
)
881 comb
+= dec_oe
.sel_in
.eq(op
.rc_sel
) # XXX should be OE sel
882 comb
+= self
.dec_cr_in
.sel_in
.eq(op
.cr_in
)
883 comb
+= self
.dec_cr_out
.sel_in
.eq(op
.cr_out
)
884 comb
+= self
.dec_cr_out
.rc_in
.eq(dec_rc
.rc_out
.data
)
887 comb
+= self
.do_copy("msr", msr
)
888 comb
+= self
.do_copy("cia", cia
)
890 # set up instruction type
891 # no op: defaults to OP_ILLEGAL
892 if self
.fn_name
=="MMU":
893 # mmu is special case: needs SPR opcode as well
894 mmu0
= self
.mmu0_spr_dec
895 with m
.If(((mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
896 (mmu0
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
))):
897 comb
+= self
.do_copy("insn_type", mmu0
.op_get("internal_op"))
899 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
901 comb
+= self
.do_copy("insn_type", self
.op_get("internal_op"))
903 # function unit for decoded instruction: requires minor redirect
905 fn
= self
.op_get("function_unit")
906 spr
= Signal(10, reset_less
=True)
907 comb
+= spr
.eq(decode_spr_num(self
.dec
.SPR
)) # from XFX
909 # for first test only forward SPRs 18 and 19 to MMU, when
910 # operation is MTSPR or MFSPR. TODO: add other MMU SPRs
911 with m
.If(((self
.dec
.op
.internal_op
== MicrOp
.OP_MTSPR
) |
912 (self
.dec
.op
.internal_op
== MicrOp
.OP_MFSPR
)) &
913 ((spr
== SPR
.DSISR
) |
(spr
== SPR
.DAR
))):
914 comb
+= self
.do_copy("fn_unit", Function
.MMU
)
916 comb
+= self
.do_copy("fn_unit",fn
)
919 if self
.needs_field("zero_a", "in1_sel"):
920 m
.submodules
.dec_ai
= dec_ai
= DecodeAImm(self
.dec
)
921 comb
+= dec_ai
.sel_in
.eq(op
.in1_sel
)
922 comb
+= self
.do_copy("zero_a", dec_ai
.immz_out
) # RA==0 detected
923 if self
.needs_field("imm_data", "in2_sel"):
924 m
.submodules
.dec_bi
= dec_bi
= DecodeBImm(self
.dec
)
925 comb
+= dec_bi
.sel_in
.eq(op
.in2_sel
)
926 comb
+= self
.do_copy("imm_data", dec_bi
.imm_out
) # imm in RB
929 comb
+= self
.do_copy("rc", dec_rc
.rc_out
)
930 comb
+= self
.do_copy("oe", dec_oe
.oe_out
)
933 comb
+= self
.do_copy("read_cr_whole", self
.dec_cr_in
.whole_reg
)
934 comb
+= self
.do_copy("write_cr_whole", self
.dec_cr_out
.whole_reg
)
935 comb
+= self
.do_copy("write_cr0", self
.dec_cr_out
.cr_bitfield
.ok
)
937 comb
+= self
.do_copy("input_cr", self
.op_get("cr_in")) # CR in
938 comb
+= self
.do_copy("output_cr", self
.op_get("cr_out")) # CR out
940 # decoded/selected instruction flags
941 comb
+= self
.do_copy("data_len", self
.op_get("ldst_len"))
942 comb
+= self
.do_copy("invert_in", self
.op_get("inv_a"))
943 comb
+= self
.do_copy("invert_out", self
.op_get("inv_out"))
944 comb
+= self
.do_copy("input_carry", self
.op_get("cry_in"))
945 comb
+= self
.do_copy("output_carry", self
.op_get("cry_out"))
946 comb
+= self
.do_copy("is_32bit", self
.op_get("is_32b"))
947 comb
+= self
.do_copy("is_signed", self
.op_get("sgn"))
948 lk
= self
.op_get("lk")
951 comb
+= self
.do_copy("lk", self
.dec
.LK
) # XXX TODO: accessor
953 comb
+= self
.do_copy("byte_reverse", self
.op_get("br"))
954 comb
+= self
.do_copy("sign_extend", self
.op_get("sgn_ext"))
955 comb
+= self
.do_copy("ldst_mode", self
.op_get("upd")) # LD/ST mode
960 class PowerDecode2(PowerDecodeSubset
):
961 """PowerDecode2: the main instruction decoder.
963 whilst PowerDecode is responsible for decoding the actual opcode, this
964 module encapsulates further specialist, sparse information and
965 expansion of fields that is inconvenient to have in the CSV files.
966 for example: the encoding of the immediates, which are detected
967 and expanded out to their full value from an annotated (enum)
970 implicit register usage is also set up, here. for example: OP_BC
971 requires implicitly reading CTR, OP_RFID requires implicitly writing
974 in addition, PowerDecoder2 is responsible for detecting whether
975 instructions are illegal (or privileged) or not, and instead of
976 just leaving at that, *replacing* the instruction to execute with
977 a suitable alternative (trap).
979 LDSTExceptions are done the cycle _after_ they're detected (after
980 they come out of LDSTCompUnit). basically despite the instruction
981 being decoded, the results of the decode are completely ignored
982 and "exception.happened" used to set the "actual" instruction to
983 "OP_TRAP". the LDSTException data structure gets filled in,
984 in the CompTrapOpSubset and that's what it fills in SRR.
986 to make this work, TestIssuer must notice "exception.happened"
987 after the (failed) LD/ST and copies the LDSTException info from
988 the output, into here (PowerDecoder2). without incrementing PC.
991 def __init__(self
, dec
, opkls
=None, fn_name
=None, final
=False, state
=None):
992 super().__init
__(dec
, opkls
, fn_name
, final
, state
)
993 self
.exc
= LDSTException("dec2_exc")
995 self
.cr_out_isvec
= Signal(1, name
="cr_out_isvec")
996 self
.cr_in_isvec
= Signal(1, name
="cr_in_isvec")
997 self
.cr_in_b_isvec
= Signal(1, name
="cr_in_b_isvec")
998 self
.cr_in_o_isvec
= Signal(1, name
="cr_in_o_isvec")
999 self
.in1_isvec
= Signal(1, name
="reg_a_isvec")
1000 self
.in2_isvec
= Signal(1, name
="reg_b_isvec")
1001 self
.in3_isvec
= Signal(1, name
="reg_c_isvec")
1002 self
.o_isvec
= Signal(1, name
="reg_o_isvec")
1003 self
.o2_isvec
= Signal(1, name
="reg_o2_isvec")
1005 def get_col_subset(self
, opkls
):
1006 subset
= super().get_col_subset(opkls
)
1007 subset
.add("asmcode")
1008 subset
.add("in1_sel")
1009 subset
.add("in2_sel")
1010 subset
.add("in3_sel")
1011 subset
.add("out_sel")
1012 subset
.add("sv_in1")
1013 subset
.add("sv_in2")
1014 subset
.add("sv_in3")
1015 subset
.add("sv_out")
1016 subset
.add("sv_cr_in")
1017 subset
.add("sv_cr_out")
1018 subset
.add("SV_Etype")
1019 subset
.add("SV_Ptype")
1021 subset
.add("internal_op")
1025 def elaborate(self
, platform
):
1026 m
= super().elaborate(platform
)
1029 e_out
, op
, do_out
= self
.e
, self
.dec
.op
, self
.e
.do
1030 dec_spr
, msr
, cia
, ext_irq
= state
.dec
, state
.msr
, state
.pc
, state
.eint
1034 # fill in for a normal instruction (not an exception)
1035 # copy over if non-exception, non-privileged etc. is detected
1037 # set up submodule decoders
1038 m
.submodules
.dec_a
= dec_a
= DecodeA(self
.dec
)
1039 m
.submodules
.dec_b
= dec_b
= DecodeB(self
.dec
)
1040 m
.submodules
.dec_c
= dec_c
= DecodeC(self
.dec
)
1041 m
.submodules
.dec_o
= dec_o
= DecodeOut(self
.dec
)
1042 m
.submodules
.dec_o2
= dec_o2
= DecodeOut2(self
.dec
)
1044 # and SVP64 Extra decoders
1045 m
.submodules
.crout_svdec
= crout_svdec
= SVP64CRExtra()
1046 m
.submodules
.crin_svdec
= crin_svdec
= SVP64CRExtra()
1047 m
.submodules
.crin_svdec_b
= crin_svdec_b
= SVP64CRExtra()
1048 m
.submodules
.crin_svdec_o
= crin_svdec_o
= SVP64CRExtra()
1049 m
.submodules
.in1_svdec
= in1_svdec
= SVP64RegExtra()
1050 m
.submodules
.in2_svdec
= in2_svdec
= SVP64RegExtra()
1051 m
.submodules
.in3_svdec
= in3_svdec
= SVP64RegExtra()
1052 m
.submodules
.o_svdec
= o_svdec
= SVP64RegExtra()
1053 m
.submodules
.o2_svdec
= o2_svdec
= SVP64RegExtra()
1055 # get the 5-bit reg data before svp64-munging it into 7-bit plus isvec
1056 reg
= Signal(5, reset_less
=True)
1058 # copy instruction through...
1059 for i
in [do
.insn
, dec_a
.insn_in
, dec_b
.insn_in
,
1060 dec_c
.insn_in
, dec_o
.insn_in
, dec_o2
.insn_in
]:
1061 comb
+= i
.eq(self
.dec
.opcode_in
)
1063 # now do the SVP64 munging. op.SV_Etype and op.sv_in1 comes from
1064 # PowerDecoder which in turn comes from LDST-RM*.csv and RM-*.csv
1065 # which in turn were auto-generated by sv_analysis.py
1066 extra
= self
.sv_rm
.extra
# SVP64 extra bits 10:18
1070 comb
+= crout_svdec
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1071 comb
+= self
.cr_out_isvec
.eq(crout_svdec
.isvec
)
1074 # CR in - index selection slightly different due to shared CR field sigh
1075 cr_a_idx
= Signal(SVEXTRA
)
1076 cr_b_idx
= Signal(SVEXTRA
)
1078 # these change slightly, when decoding BA/BB. really should have
1079 # their own separate CSV column: sv_cr_in1 and sv_cr_in2, but hey
1080 comb
+= cr_a_idx
.eq(op
.sv_cr_in
)
1081 comb
+= cr_b_idx
.eq(SVEXTRA
.NONE
)
1082 with m
.If(op
.sv_cr_in
== SVEXTRA
.Idx_1_2
.value
):
1083 comb
+= cr_a_idx
.eq(SVEXTRA
.Idx1
)
1084 comb
+= cr_b_idx
.eq(SVEXTRA
.Idx2
)
1086 comb
+= self
.cr_in_isvec
.eq(crin_svdec
.isvec
)
1087 comb
+= self
.cr_in_b_isvec
.eq(crin_svdec_b
.isvec
)
1088 comb
+= self
.cr_in_o_isvec
.eq(crin_svdec_o
.isvec
)
1090 # indices are slightly different, BA/BB mess sorted above
1091 comb
+= crin_svdec
.idx
.eq(cr_a_idx
) # SVP64 CR in A
1092 comb
+= crin_svdec_b
.idx
.eq(cr_b_idx
) # SVP64 CR in B
1093 comb
+= crin_svdec_o
.idx
.eq(op
.sv_cr_out
) # SVP64 CR out
1095 # ...and subdecoders' input fields
1096 comb
+= dec_a
.sel_in
.eq(op
.in1_sel
)
1097 comb
+= dec_b
.sel_in
.eq(op
.in2_sel
)
1098 comb
+= dec_c
.sel_in
.eq(op
.in3_sel
)
1099 comb
+= dec_o
.sel_in
.eq(op
.out_sel
)
1100 comb
+= dec_o2
.sel_in
.eq(op
.out_sel
)
1101 if hasattr(do
, "lk"):
1102 comb
+= dec_o2
.lk
.eq(do
.lk
)
1104 # registers a, b, c and out and out2 (LD/ST EA)
1105 for to_reg
, fromreg
, svdec
in (
1106 (e
.read_reg1
, dec_a
.reg_out
, in1_svdec
),
1107 (e
.read_reg2
, dec_b
.reg_out
, in2_svdec
),
1108 (e
.read_reg3
, dec_c
.reg_out
, in3_svdec
),
1109 (e
.write_reg
, dec_o
.reg_out
, o_svdec
),
1110 (e
.write_ea
, dec_o2
.reg_out
, o2_svdec
)):
1111 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1112 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1113 comb
+= svdec
.reg_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1114 comb
+= to_reg
.data
.eq(svdec
.reg_out
) # 7-bit output
1115 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1117 comb
+= in1_svdec
.idx
.eq(op
.sv_in1
) # SVP64 reg #1 (matches in1_sel)
1118 comb
+= in2_svdec
.idx
.eq(op
.sv_in2
) # SVP64 reg #2 (matches in2_sel)
1119 comb
+= in3_svdec
.idx
.eq(op
.sv_in3
) # SVP64 reg #3 (matches in3_sel)
1120 comb
+= o_svdec
.idx
.eq(op
.sv_out
) # SVP64 output (matches out_sel)
1121 # XXX TODO - work out where this should come from. the problem is
1122 # that LD-with-update is implied (computed from "is instruction in
1123 # "update mode" rather than specified cleanly as its own CSV column
1124 #comb += o2_svdec.idx.eq(op.sv_out) # SVP64 output (implicit)
1126 comb
+= self
.in1_isvec
.eq(in1_svdec
.isvec
)
1127 comb
+= self
.in2_isvec
.eq(in2_svdec
.isvec
)
1128 comb
+= self
.in3_isvec
.eq(in3_svdec
.isvec
)
1129 comb
+= self
.o_isvec
.eq(o_svdec
.isvec
)
1130 comb
+= self
.o2_isvec
.eq(o2_svdec
.isvec
)
1133 comb
+= e
.read_spr1
.eq(dec_a
.spr_out
)
1134 comb
+= e
.write_spr
.eq(dec_o
.spr_out
)
1137 comb
+= e
.read_fast1
.eq(dec_a
.fast_out
)
1138 comb
+= e
.read_fast2
.eq(dec_b
.fast_out
)
1139 comb
+= e
.write_fast1
.eq(dec_o
.fast_out
)
1140 comb
+= e
.write_fast2
.eq(dec_o2
.fast_out
)
1142 # condition registers (CR)
1143 for to_reg
, fromreg
, svdec
in (
1144 (e
.read_cr1
, self
.dec_cr_in
.cr_bitfield
, crin_svdec
),
1145 (e
.read_cr2
, self
.dec_cr_in
.cr_bitfield_b
, crin_svdec_b
),
1146 (e
.read_cr3
, self
.dec_cr_in
.cr_bitfield_o
, crin_svdec_o
),
1147 (e
.write_cr
, self
.dec_cr_out
.cr_bitfield
, crout_svdec
)):
1148 comb
+= svdec
.extra
.eq(extra
) # EXTRA field of SVP64 RM
1149 comb
+= svdec
.etype
.eq(op
.SV_Etype
) # EXTRA2/3 for this insn
1150 comb
+= svdec
.cr_in
.eq(fromreg
.data
) # 3-bit (CR0/BC/BFA)
1151 comb
+= to_reg
.data
.eq(svdec
.cr_out
) # 7-bit output
1152 comb
+= to_reg
.ok
.eq(fromreg
.ok
)
1154 # sigh this is exactly the sort of thing for which the
1155 # decoder is designed to not need. MTSPR, MFSPR and others need
1156 # access to the XER bits. however setting e.oe is not appropriate
1157 with m
.If(op
.internal_op
== MicrOp
.OP_MFSPR
):
1158 comb
+= e
.xer_in
.eq(0b111) # SO, CA, OV
1159 with m
.If(op
.internal_op
== MicrOp
.OP_CMP
):
1160 comb
+= e
.xer_in
.eq(1<<XERRegs
.SO
) # SO
1161 with m
.If(op
.internal_op
== MicrOp
.OP_MTSPR
):
1162 comb
+= e
.xer_out
.eq(1)
1164 # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
1165 with m
.If(op
.internal_op
== MicrOp
.OP_TRAP
):
1166 # *DO NOT* call self.trap here. that would reset absolutely
1167 # everything including destroying read of RA and RB.
1168 comb
+= self
.do_copy("trapaddr", 0x70) # strip first nibble
1170 ####################
1171 # ok so the instruction's been decoded, blah blah, however
1172 # now we need to determine if it's actually going to go ahead...
1173 # *or* if in fact it's a privileged operation, whether there's
1174 # an external interrupt, etc. etc. this is a simple priority
1175 # if-elif-elif sequence. decrement takes highest priority,
1176 # EINT next highest, privileged operation third.
1178 # check if instruction is privileged
1179 is_priv_insn
= instr_is_priv(m
, op
.internal_op
, e
.do
.insn
)
1181 # different IRQ conditions
1182 ext_irq_ok
= Signal()
1183 dec_irq_ok
= Signal()
1188 comb
+= ext_irq_ok
.eq(ext_irq
& msr
[MSR
.EE
]) # v3.0B p944 (MSR.EE)
1189 comb
+= dec_irq_ok
.eq(dec_spr
[63] & msr
[MSR
.EE
]) # 6.5.11 p1076
1190 comb
+= priv_ok
.eq(is_priv_insn
& msr
[MSR
.PR
])
1191 comb
+= illeg_ok
.eq(op
.internal_op
== MicrOp
.OP_ILLEGAL
)
1193 # LD/ST exceptions. TestIssuer copies the exception info at us
1194 # after a failed LD/ST.
1195 with m
.If(exc
.happened
):
1196 with m
.If(exc
.alignment
):
1197 self
.trap(m
, TT
.PRIV
, 0x600)
1198 with m
.Elif(exc
.instr_fault
):
1199 with m
.If(exc
.segment_fault
):
1200 self
.trap(m
, TT
.PRIV
, 0x480)
1202 # pass exception info to trap to create SRR1
1203 self
.trap(m
, TT
.MEMEXC
, 0x400, exc
)
1205 with m
.If(exc
.segment_fault
):
1206 self
.trap(m
, TT
.PRIV
, 0x380)
1208 self
.trap(m
, TT
.PRIV
, 0x300)
1210 # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR)
1211 with m
.Elif(dec_irq_ok
):
1212 self
.trap(m
, TT
.DEC
, 0x900) # v3.0B 6.5 p1065
1214 # external interrupt? only if MSR.EE set
1215 with m
.Elif(ext_irq_ok
):
1216 self
.trap(m
, TT
.EINT
, 0x500)
1218 # privileged instruction trap
1219 with m
.Elif(priv_ok
):
1220 self
.trap(m
, TT
.PRIV
, 0x700)
1222 # illegal instruction must redirect to trap. this is done by
1223 # *overwriting* the decoded instruction and starting again.
1224 # (note: the same goes for interrupts and for privileged operations,
1225 # just with different trapaddr and traptype)
1226 with m
.Elif(illeg_ok
):
1227 # illegal instruction trap
1228 self
.trap(m
, TT
.ILLEG
, 0x700)
1230 # no exception, just copy things to the output
1234 ####################
1235 # follow-up after trap/irq to set up SRR0/1
1237 # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
1238 # Note: OP_SC could actually be modified to just be a trap
1239 with m
.If((do_out
.insn_type
== MicrOp
.OP_TRAP
) |
1240 (do_out
.insn_type
== MicrOp
.OP_SC
)):
1241 # TRAP write fast1 = SRR0
1242 comb
+= e_out
.write_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1243 comb
+= e_out
.write_fast1
.ok
.eq(1)
1244 # TRAP write fast2 = SRR1
1245 comb
+= e_out
.write_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1246 comb
+= e_out
.write_fast2
.ok
.eq(1)
1248 # RFID: needs to read SRR0/1
1249 with m
.If(do_out
.insn_type
== MicrOp
.OP_RFID
):
1250 # TRAP read fast1 = SRR0
1251 comb
+= e_out
.read_fast1
.data
.eq(FastRegs
.SRR0
) # constant: SRR0
1252 comb
+= e_out
.read_fast1
.ok
.eq(1)
1253 # TRAP read fast2 = SRR1
1254 comb
+= e_out
.read_fast2
.data
.eq(FastRegs
.SRR1
) # constant: SRR1
1255 comb
+= e_out
.read_fast2
.ok
.eq(1)
1257 # annoying simulator bug
1258 if hasattr(e_out
, "asmcode") and hasattr(self
.dec
.op
, "asmcode"):
1259 comb
+= e_out
.asmcode
.eq(self
.dec
.op
.asmcode
)
1263 def trap(self
, m
, traptype
, trapaddr
, exc
=None):
1264 """trap: this basically "rewrites" the decoded instruction as a trap
1267 op
, e
= self
.dec
.op
, self
.e
1268 comb
+= e
.eq(0) # reset eeeeeverything
1271 comb
+= self
.do_copy("insn", self
.dec
.opcode_in
, True)
1272 comb
+= self
.do_copy("insn_type", MicrOp
.OP_TRAP
, True)
1273 comb
+= self
.do_copy("fn_unit", Function
.TRAP
, True)
1274 comb
+= self
.do_copy("trapaddr", trapaddr
>> 4, True) # bottom 4 bits
1275 comb
+= self
.do_copy("traptype", traptype
, True) # request type
1276 comb
+= self
.do_copy("ldst_exc", exc
, True) # request type
1277 comb
+= self
.do_copy("msr", self
.state
.msr
, True) # copy of MSR "state"
1278 comb
+= self
.do_copy("cia", self
.state
.pc
, True) # copy of PC "state"
1281 # SVP64 Prefix fields: see https://libre-soc.org/openpower/sv/svp64/
1282 # identifies if an instruction is a SVP64-encoded prefix, and extracts
1283 # the 24-bit SVP64 context (RM) if it is
1284 class SVP64PowerDecoder(Elaboratable
):
1287 self
.opcode_in
= Signal(32, reset_less
=True)
1288 self
.raw_opcode_in
= Signal
.like(self
.opcode_in
, reset_less
=True)
1289 self
.is_svp64_mode
= Signal(1, reset_less
=True)
1290 self
.svp64_rm
= Signal(24, reset_less
=True)
1291 self
.bigendian
= Signal(reset_less
=True)
1293 def elaborate(self
, platform
):
1296 # sigh copied this from TopPowerDecoder
1297 # raw opcode in assumed to be in LE order: byte-reverse it to get BE
1298 raw_le
= self
.raw_opcode_in
1300 for i
in range(0, 32, 8):
1301 l
.append(raw_le
[i
:i
+8])
1304 comb
+= self
.opcode_in
.eq(Mux(self
.bigendian
, raw_be
, raw_le
))
1306 # start identifying if the incoming opcode is SVP64 prefix)
1307 major
= Signal(6, reset_less
=True)
1309 comb
+= major
.eq(self
.opcode_in
[26:32])
1310 comb
+= self
.is_svp64_mode
.eq((major
== Const(1, 6)) & # EXT01
1311 self
.opcode_in
[31-7] & # identifier
1312 self
.opcode_in
[31-9]) # bits
1314 # now grab the 24-bit ReMap context bits,
1315 rmfields
= [6, 8] + list(range(10,32)) # SVP64 24-bit RM
1317 for idx
in rmfields
:
1318 l
.append(self
.opcode_in
[32-idx
])
1319 with m
.If(self
.is_svp64_mode
):
1320 comb
+= self
.svp64_rm
.eq(Cat(*l
))
1325 return [self
.opcode_in
, self
.raw_opcode_in
, self
.is_svp64_mode
,
1326 self
.svp64_rm
, self
.bigendian
]
1328 def get_rdflags(e
, cu
):
1330 for idx
in range(cu
.n_src
):
1331 regfile
, regname
, _
= cu
.get_in_spec(idx
)
1332 rdflag
, read
= regspec_decode_read(e
, regfile
, regname
)
1334 print("rdflags", rdl
)
1338 if __name__
== '__main__':
1339 svp64
= SVP64PowerDecoder()
1340 vl
= rtlil
.convert(svp64
, ports
=svp64
.ports())
1341 with
open("svp64_dec.il", "w") as f
:
1343 pdecode
= create_pdecode()
1344 dec2
= PowerDecode2(pdecode
)
1345 vl
= rtlil
.convert(dec2
, ports
=dec2
.ports() + pdecode
.ports())
1346 with
open("dec2.il", "w") as f
: