1 """LOAD / STORE Computation Unit.
3 This module covers POWER9-compliant Load and Store operations,
4 with selection on each between immediate and indexed mode as
5 options for the calculation of the Effective Address (EA),
6 and also "update" mode which optionally stores that EA into
7 an additional register.
10 Note: it took 15 attempts over several weeks to redraw the diagram
11 needed to capture this FSM properly. To understand it fully, please
12 take the time to review the links, video, and diagram.
15 Stores are activated when Go_Store is enabled, and use a sync'd "ADD" to
16 compute the "Effective Address", and, when ready the operand (src3_i)
17 is stored in the computed address (passed through to the PortInterface)
19 Loads are activated when Go_Write[0] is enabled. The EA is computed,
20 and (as long as there was no exception) the data comes out (at any
21 time from the PortInterface), and is captured by the LDCompSTUnit.
23 TODO: dcbz, yes, that's going to be complicated, has to be done
24 with great care, to detect the case when dcbz is set
25 and *not* expect to read any data, just the address.
26 so, wait for RA but not RB.
28 Both LD and ST may request that the address be computed from summing
29 operand1 (src[0]) with operand2 (src[1]) *or* by summing operand1 with
30 the immediate (from the opcode).
32 Both LD and ST may also request "update" mode (op_is_update) which
33 activates the use of Go_Write[1] to control storage of the EA into
34 a *second* operand in the register file.
36 Thus this module has *TWO* write-requests to the register file and
37 *THREE* read-requests to the register file (not all at the same time!)
38 The regfile port usage is:
50 It's a multi-level Finite State Machine that (unfortunately) nmigen.FSM
51 is not suited to (nmigen.FSM is clock-driven, and some aspects of
52 the nested FSMs below are *combinatorial*).
54 * One FSM covers Operand collection and communication address-side
55 with the LD/ST PortInterface. its role ends when "RD_DONE" is asserted
57 * A second FSM activates to cover LD. it activates if op_is_ld is true
59 * A third FSM activates to cover ST. it activates if op_is_st is true
61 * TODO document DCBZ (not complete yet)
63 * The "overall" (fourth) FSM coordinates the progression and completion
64 of the three other FSMs, firing "WR_RESET" which switches off "busy"
68 https://libre-soc.org/3d_gpu/ld_st_comp_unit.jpg
70 Links including to walk-through videos:
72 * https://libre-soc.org/3d_gpu/architecture/6600scoreboard/
73 * http://libre-soc.org/openpower/isa/fixedload
74 * http://libre-soc.org/openpower/isa/fixedstore
78 * https://bugs.libre-soc.org/show_bug.cgi?id=302
79 * https://bugs.libre-soc.org/show_bug.cgi?id=216
83 * EA - Effective Address
88 from nmigen
.compat
.sim
import run_simulation
89 from nmigen
.cli
import verilog
, rtlil
90 from nmigen
import Module
, Signal
, Mux
, Cat
, Elaboratable
, Array
, Repl
, C
91 from nmigen
.hdl
.rec
import Record
, Layout
93 from nmutil
.latch
import SRLatch
, latchregister
94 from nmutil
.byterev
import byte_reverse
95 from nmutil
.extend
import exts
97 from soc
.experiment
.compalu_multi
import go_record
, CompUnitRecord
98 from soc
.experiment
.l0_cache
import PortInterface
99 from soc
.experiment
.pimem
import LDSTException
100 from soc
.fu
.regspec
import RegSpecAPI
102 from openpower
.decoder
.power_enums
import MicrOp
, Function
, LDSTMode
103 from soc
.fu
.ldst
.ldst_input_record
import CompLDSTOpSubset
104 from openpower
.decoder
.power_decoder2
import Data
105 from openpower
.consts
import MSR
106 from soc
.config
.test
.test_loadstore
import TestMemPspec
109 from nmutil
.util
import Display
112 # TODO: LDSTInputData and LDSTOutputData really should be used
113 # here, to make things more like the other CompUnits. currently,
114 # also, RegSpecAPI is used explicitly here
117 class LDSTCompUnitRecord(CompUnitRecord
):
118 def __init__(self
, rwid
, opsubset
=CompLDSTOpSubset
, name
=None):
119 CompUnitRecord
.__init
__(self
, opsubset
, rwid
,
120 n_src
=3, n_dst
=2, name
=name
)
122 self
.ad
= go_record(1, name
="cu_ad") # address go in, req out
123 self
.st
= go_record(1, name
="cu_st") # store go in, req out
125 self
.exc_o
= LDSTException("exc_o")
127 self
.ld_o
= Signal(reset_less
=True) # operation is a LD
128 self
.st_o
= Signal(reset_less
=True) # operation is a ST
130 # hmm... are these necessary?
131 self
.load_mem_o
= Signal(reset_less
=True) # activate memory LOAD
132 self
.stwd_mem_o
= Signal(reset_less
=True) # activate memory STORE
135 class LDSTCompUnit(RegSpecAPI
, Elaboratable
):
136 """LOAD / STORE Computation Unit
141 * :pi: a PortInterface to the memory subsystem (read-write capable)
142 * :rwid: register width
143 * :awid: address width
147 * :src_i: Source Operands (RA/RB/RC) - managed by rd[0-3] go/req
151 * :o_data: Dest out (LD) - managed by wr[0] go/req
152 * :addr_o: Address out (LD or ST) - managed by wr[1] go/req
153 * :exc_o: Address/Data Exception occurred. LD/ST must terminate
155 TODO: make exc_o a data-type rather than a single-bit signal
161 * :oper_i: operation being carried out (POWER9 decode LD/ST subset)
162 * :issue_i: LD/ST is being "issued".
163 * :shadown_i: Inverted-shadow is being held (stops STORE *and* WRITE)
164 * :go_rd_i: read is being actioned (latches in src regs)
165 * :go_wr_i: write mode (exactly like ALU CompUnit)
166 * :go_ad_i: address is being actioned (triggers actual mem LD)
167 * :go_st_i: store is being actioned (triggers actual mem STORE)
168 * :go_die_i: resets the unit back to "wait for issue"
170 Control Signals (Out)
171 ---------------------
173 * :busy_o: function unit is busy
174 * :rd_rel_o: request src1/src2
175 * :adr_rel_o: request address (from mem)
176 * :sto_rel_o: request store (to mem)
177 * :req_rel_o: request write (result)
178 * :load_mem_o: activate memory LOAD
179 * :stwd_mem_o: activate memory STORE
181 Note: load_mem_o, stwd_mem_o and req_rel_o MUST all be acknowledged
182 in a single cycle and the CompUnit set back to doing another op.
183 This means deasserting go_st_i, go_ad_i or go_wr_i as appropriate
184 depending on whether the operation is a ST or LD.
186 Note: LDSTCompUnit takes care of LE/BE normalisation:
187 * LD data is normalised after receipt from the PortInterface
188 * ST data is normalised *prior* to sending onto the PortInterface
189 TODO: use one module for the byte-reverse as it's quite expensive in gates
192 def __init__(self
, pi
=None, rwid
=64, awid
=64, opsubset
=CompLDSTOpSubset
,
193 debugtest
=False, name
=None):
194 super().__init
__(rwid
)
197 self
.cu
= cu
= LDSTCompUnitRecord(rwid
, opsubset
, name
=name
)
198 self
.debugtest
= debugtest
# enable debug output for unit testing
200 # POWER-compliant LD/ST has index and update: *fixed* number of ports
201 self
.n_src
= n_src
= 3 # RA, RB, RT/RS
202 self
.n_dst
= n_dst
= 3 # RA, RT/RS, CR0
204 # set up array of src and dest signals
205 for i
in range(n_src
):
206 j
= i
+ 1 # name numbering to match src1/src2
208 setattr(self
, name
, getattr(cu
, name
))
211 for i
in range(n_dst
):
212 j
= i
+ 1 # name numbering to match dest1/2...
213 name
= "dest%d_o" % j
214 setattr(self
, name
, getattr(cu
, name
))
219 self
.rdmaskn
= cu
.rdmaskn
220 self
.wrmask
= cu
.wrmask
225 # HACK: get data width from dest[0]. this is used across the board
226 # (it really shouldn't be)
227 self
.data_wid
= self
.dest
[0].shape()
229 self
.go_rd_i
= self
.rd
.go_i
# temporary naming
230 self
.go_wr_i
= self
.wr
.go_i
# temporary naming
231 self
.go_ad_i
= self
.ad
.go_i
# temp naming: go address in
232 self
.go_st_i
= self
.st
.go_i
# temp naming: go store in
234 self
.rd_rel_o
= self
.rd
.rel_o
# temporary naming
235 self
.req_rel_o
= self
.wr
.rel_o
# temporary naming
236 self
.adr_rel_o
= self
.ad
.rel_o
# request address (from mem)
237 self
.sto_rel_o
= self
.st
.rel_o
# request store (to mem)
239 self
.issue_i
= cu
.issue_i
240 self
.shadown_i
= cu
.shadown_i
241 self
.go_die_i
= cu
.go_die_i
243 self
.oper_i
= cu
.oper_i
244 self
.src_i
= cu
._src
_i
246 self
.o_data
= Data(self
.data_wid
, name
="o") # Dest1 out: RT
247 self
.addr_o
= Data(self
.data_wid
, name
="ea") # Addr out: Update => RA
248 self
.cr_o
= Data(self
.data_wid
, name
="cr0") # CR0 (for stdcx etc)
249 self
.exc_o
= cu
.exc_o
250 self
.done_o
= cu
.done_o
251 self
.busy_o
= cu
.busy_o
256 self
.load_mem_o
= cu
.load_mem_o
257 self
.stwd_mem_o
= cu
.stwd_mem_o
259 def elaborate(self
, platform
):
265 issue_i
= self
.issue_i
267 #####################
268 # latches for the FSM.
269 m
.submodules
.opc_l
= opc_l
= SRLatch(sync
=False, name
="opc")
270 m
.submodules
.src_l
= src_l
= SRLatch(False, self
.n_src
, name
="src")
271 m
.submodules
.alu_l
= alu_l
= SRLatch(sync
=False, name
="alu")
272 m
.submodules
.adr_l
= adr_l
= SRLatch(sync
=False, name
="adr")
273 m
.submodules
.lod_l
= lod_l
= SRLatch(sync
=False, name
="lod")
274 m
.submodules
.sto_l
= sto_l
= SRLatch(sync
=False, name
="sto")
275 m
.submodules
.wri_l
= wri_l
= SRLatch(sync
=False, name
="wri")
276 m
.submodules
.upd_l
= upd_l
= SRLatch(sync
=False, name
="upd")
277 m
.submodules
.cr0_l
= cr0_l
= SRLatch(sync
=False, name
="cr0")
278 m
.submodules
.rst_l
= rst_l
= SRLatch(sync
=False, name
="rst")
279 m
.submodules
.lsd_l
= lsd_l
= SRLatch(sync
=False, name
="lsd") # done
285 op_is_ld
= Signal(reset_less
=True)
286 op_is_st
= Signal(reset_less
=True)
287 op_is_dcbz
= Signal(reset_less
=True)
288 op_is_st_or_dcbz
= Signal(reset_less
=True)
289 op_is_atomic
= Signal(reset_less
=True)
291 # ALU/LD data output control
292 alu_valid
= Signal(reset_less
=True) # ALU operands are valid
293 alu_ok
= Signal(reset_less
=True) # ALU out ok (1 clock delay valid)
294 addr_ok
= Signal(reset_less
=True) # addr ok (from PortInterface)
295 ld_ok
= Signal(reset_less
=True) # LD out ok from PortInterface
296 wr_any
= Signal(reset_less
=True) # any write (incl. store)
297 rda_any
= Signal(reset_less
=True) # any read for address ops
298 rd_done
= Signal(reset_less
=True) # all *necessary* operands read
299 wr_reset
= Signal(reset_less
=True) # final reset condition
300 canceln
= Signal(reset_less
=True) # cancel (active low)
301 store_done
= Signal(reset_less
=True) # store has been actioned
304 alu_o
= Signal(self
.data_wid
, reset_less
=True)
305 ldd_o
= Signal(self
.data_wid
, reset_less
=True)
307 ##############################
308 # reset conditions for latches
310 # temporaries (also convenient when debugging)
311 reset_o
= Signal(reset_less
=True) # reset opcode
312 reset_w
= Signal(reset_less
=True) # reset write
313 reset_u
= Signal(reset_less
=True) # reset update
314 reset_c
= Signal(reset_less
=True) # reset cr0
315 reset_a
= Signal(reset_less
=True) # reset adr latch
316 reset_i
= Signal(reset_less
=True) # issue|die (use a lot)
317 reset_r
= Signal(self
.n_src
, reset_less
=True) # reset src
318 reset_s
= Signal(reset_less
=True) # reset store
320 # end execution when a terminating condition is detected:
321 # - go_die_i: a speculative operation was cancelled
322 # - exc_o.happened: an exception has occurred
324 comb
+= terminate
.eq(self
.go_die_i | self
.exc_o
.happened
)
326 comb
+= reset_i
.eq(issue_i | terminate
) # various
327 comb
+= reset_o
.eq(self
.done_o | terminate
) # opcode reset
328 comb
+= reset_w
.eq(self
.wr
.go_i
[0] | terminate
) # write reg 1
329 comb
+= reset_u
.eq(self
.wr
.go_i
[1] | terminate
) # update (reg 2)
330 comb
+= reset_c
.eq(self
.wr
.go_i
[2] | terminate
) # cr0 (reg 3)
331 comb
+= reset_s
.eq(self
.go_st_i | terminate
) # store reset
332 comb
+= reset_r
.eq(self
.rd
.go_i |
Repl(terminate
, self
.n_src
))
333 comb
+= reset_a
.eq(self
.go_ad_i | terminate
)
335 p_st_go
= Signal(reset_less
=True)
336 sync
+= p_st_go
.eq(self
.st
.go_i
)
338 # decode bits of operand (latched)
339 oper_r
= CompLDSTOpSubset(name
="oper_r") # Dest register
340 comb
+= op_is_st
.eq(oper_r
.insn_type
== MicrOp
.OP_STORE
) # ST
341 comb
+= op_is_ld
.eq(oper_r
.insn_type
== MicrOp
.OP_LOAD
) # LD
342 comb
+= op_is_dcbz
.eq(oper_r
.insn_type
== MicrOp
.OP_DCBZ
) # DCBZ
343 comb
+= op_is_atomic
.eq(oper_r
.reserve
) # atomic LR/SC
344 comb
+= op_is_st_or_dcbz
.eq(op_is_st | op_is_dcbz
)
345 # dcbz is special case of store
347 #comb += Display("compldst_multi: op_is_dcbz = %i",
348 # (oper_r.insn_type == MicrOp.OP_DCBZ))
349 op_is_update
= oper_r
.ldst_mode
== LDSTMode
.update
# UPDATE
350 op_is_cix
= oper_r
.ldst_mode
== LDSTMode
.cix
# cache-inhibit
351 comb
+= self
.load_mem_o
.eq(op_is_ld
& self
.go_ad_i
)
352 comb
+= self
.stwd_mem_o
.eq(op_is_st
& self
.go_st_i
)
353 comb
+= self
.ld_o
.eq(op_is_ld
)
354 comb
+= self
.st_o
.eq(op_is_st
)
356 ##########################
357 # FSM implemented through sequence of latches. approximately this:
359 # - src_l[0] : operands
361 # - alu_l : looks after add of src1/2/imm (EA)
362 # - adr_l : waits for add (EA)
363 # - upd_l : waits for adr and Regfile (port 2)
364 # - cr0_l : waits for Rc=1 and CR0 Regfile (port 3)
366 # - lod_l : waits for adr (EA) and for LD Data
367 # - wri_l : waits for LD Data and Regfile (port 1)
368 # - st_l : waits for alu and operand2
369 # - rst_l : waits for all FSM paths to converge.
370 # NOTE: use sync to stop combinatorial loops.
372 # opcode latch - inverted so that busy resets to 0
373 # note this MUST be sync so as to avoid a combinatorial loop
374 # between busy_o and issue_i on the reset latch (rst_l)
375 sync
+= opc_l
.s
.eq(issue_i
) # XXX NOTE: INVERTED FROM book!
376 sync
+= opc_l
.r
.eq(reset_o
) # XXX NOTE: INVERTED FROM book!
379 sync
+= src_l
.s
.eq(Repl(issue_i
, self
.n_src
) & ~self
.rdmaskn
)
380 sync
+= src_l
.r
.eq(reset_r
)
381 #### sync += Display("reset_r = %i",reset_r)
383 # alu latch. use sync-delay between alu_ok and valid to generate pulse
384 comb
+= alu_l
.s
.eq(reset_i
)
385 comb
+= alu_l
.r
.eq(alu_ok
& ~alu_valid
& ~rda_any
)
388 comb
+= adr_l
.s
.eq(reset_i
)
389 sync
+= adr_l
.r
.eq(reset_a
)
392 comb
+= lod_l
.s
.eq(reset_i
)
393 comb
+= lod_l
.r
.eq(ld_ok
)
396 comb
+= wri_l
.s
.eq(issue_i
)
397 sync
+= wri_l
.r
.eq(reset_w |
Repl(wr_reset |
398 (~self
.pi
.busy_o
& op_is_update
),
399 #(self.pi.busy_o & op_is_update),
400 #self.done_o | (self.pi.busy_o & op_is_update),
403 # CR0 operand latch (CR0 written to reg 3 if Rc=1)
404 op_is_rc1
= oper_r
.rc
.rc
& oper_r
.rc
.ok
405 sync
+= cr0_l
.s
.eq(reset_i
& op_is_rc1
)
406 sync
+= cr0_l
.r
.eq(reset_c
)
408 # update-mode operand latch (EA written to reg 2)
409 sync
+= upd_l
.s
.eq(reset_i
)
410 sync
+= upd_l
.r
.eq(reset_u
)
413 comb
+= sto_l
.s
.eq(addr_ok
& op_is_st_or_dcbz
)
414 sync
+= sto_l
.r
.eq(reset_s | p_st_go
)
416 # ld/st done. needed to stop LD/ST from activating repeatedly
417 comb
+= lsd_l
.s
.eq(issue_i
)
418 sync
+= lsd_l
.r
.eq(reset_s | p_st_go | ld_ok
)
421 comb
+= rst_l
.s
.eq(addr_ok
) # start when address is ready
422 comb
+= rst_l
.r
.eq(issue_i
)
424 # create a latch/register for the operand
425 with m
.If(self
.issue_i
):
426 sync
+= oper_r
.eq(self
.oper_i
)
427 with m
.If(self
.done_o | terminate
):
431 ldd_r
= Signal(self
.data_wid
, reset_less
=True) # Dest register
432 latchregister(m
, ldd_o
, ldd_r
, ld_ok
, name
="ldo_r")
434 # and for each input from the incoming src operands
436 for i
in range(self
.n_src
):
438 src_r
= Signal(self
.data_wid
, name
=name
, reset_less
=True)
439 with m
.If(self
.rd
.go_i
[i
]):
440 sync
+= src_r
.eq(self
.src_i
[i
])
441 with m
.If(self
.issue_i
):
445 # and one for the output from the ADD (for the EA)
446 addr_r
= Signal(self
.data_wid
, reset_less
=True) # Effective Address
447 latchregister(m
, alu_o
, addr_r
, alu_l
.q
, "ea_r")
449 # select either zero or src1 if opcode says so
450 op_is_z
= oper_r
.zero_a
451 src1_or_z
= Signal(self
.data_wid
, reset_less
=True)
452 m
.d
.comb
+= src1_or_z
.eq(Mux(op_is_z
, 0, srl
[0]))
454 # select either immediate or src2 if opcode says so
455 op_is_imm
= oper_r
.imm_data
.ok
456 src2_or_imm
= Signal(self
.data_wid
, reset_less
=True)
457 m
.d
.comb
+= src2_or_imm
.eq(Mux(op_is_imm
, oper_r
.imm_data
.data
, srl
[1]))
459 # now do the ALU addr add: one cycle, and say "ready" (next cycle, too)
460 comb
+= alu_o
.eq(src1_or_z
+ src2_or_imm
) # actual EA
461 m
.d
.sync
+= alu_ok
.eq(alu_valid
& canceln
) # keep ack in sync with EA
463 ############################
464 # Control Signal calculation
468 comb
+= self
.busy_o
.eq(opc_l
.q
) # | self.pi.busy_o) # busy out
470 # 1st operand read-request only when zero not active
471 # 2nd operand only needed when immediate is not active
472 slg
= Cat(op_is_z
, op_is_imm
) #is this correct ?
473 bro
= Repl(self
.busy_o
, self
.n_src
)
474 comb
+= self
.rd
.rel_o
.eq(src_l
.q
& bro
& ~slg
)
476 # note when the address-related read "go" signals are active
477 comb
+= rda_any
.eq(self
.rd
.go_i
[0] | self
.rd
.go_i
[1])
479 # alu input valid when 1st and 2nd ops done (or imm not active)
480 comb
+= alu_valid
.eq(busy_o
& ~
(self
.rd
.rel_o
[0] | self
.rd
.rel_o
[1]) &
483 # 3rd operand only needed when operation is a store
484 comb
+= self
.rd
.rel_o
[2].eq(src_l
.q
[2] & busy_o
& op_is_st
)
486 # all reads done when alu is valid and 3rd operand needed
487 comb
+= rd_done
.eq(alu_valid
& ~self
.rd
.rel_o
[2])
489 # address release only if addr ready, but Port must be idle
490 comb
+= self
.adr_rel_o
.eq(alu_valid
& adr_l
.q
& busy_o
)
492 # the write/store (etc) all must be cancelled if an exception occurs
493 # note: cancel is active low, like shadown_i,
494 # while exc_o.happpened is active high
495 comb
+= canceln
.eq(~self
.exc_o
.happened
& self
.shadown_i
)
497 # store release when st ready *and* all operands read (and no shadow)
498 # dcbz is special case of store -- TODO verify shadows
499 comb
+= self
.st
.rel_o
.eq(sto_l
.q
& busy_o
& rd_done
& op_is_st_or_dcbz
&
502 # request write of LD result. waits until shadow is dropped.
503 comb
+= self
.wr
.rel_o
[0].eq(rd_done
& wri_l
.q
& busy_o
& lod_l
.qn
&
506 # request write of EA result only in update mode
507 comb
+= self
.wr
.rel_o
[1].eq(upd_l
.q
& busy_o
& op_is_update
&
510 # request write of CR0 result only in reserve and Rc=1
511 comb
+= self
.wr
.rel_o
[2].eq(cr0_l
.q
& busy_o
& op_is_atomic
&
514 # provide "done" signal: select req_rel for non-LD/ST, adr_rel for LD/ST
515 comb
+= wr_any
.eq(self
.st
.go_i | p_st_go |
517 comb
+= wr_reset
.eq(rst_l
.q
& busy_o
& canceln
&
518 ~
(self
.st
.rel_o | self
.wr
.rel_o
.bool()) &
519 (lod_l
.qn | op_is_st_or_dcbz
)
521 comb
+= self
.done_o
.eq(wr_reset
& (~self
.pi
.busy_o | op_is_ld
))
523 ######################
524 # Data/Address outputs
526 # put the LD-output register directly onto the output bus on a go_write
527 comb
+= self
.o_data
.data
.eq(self
.dest
[0])
528 with m
.If(self
.wr
.go_i
[0]):
529 comb
+= self
.dest
[0].eq(ldd_r
)
531 # "update" mode, put address out on 2nd go-write
532 comb
+= self
.addr_o
.data
.eq(self
.dest
[1])
533 with m
.If(op_is_update
& self
.wr
.go_i
[1]):
534 comb
+= self
.dest
[1].eq(addr_r
)
536 # fun-fun-fun, calculate CR0 when Rc=1 requested.
538 comb
+= self
.cr_o
.data
.eq(cr0
)
540 comb
+= cr0
.eq(Cat(C(0, 1), store_done
, C(0, 2)))
542 # need to look like MultiCompUnit: put wrmask out.
543 # XXX may need to make this enable only when write active
544 comb
+= self
.wrmask
.eq(bro
& Cat(op_is_ld
, op_is_update
))
546 ###########################
547 # PortInterface connections
550 # connect to LD/ST PortInterface.
551 comb
+= pi
.is_ld_i
.eq(op_is_ld
& busy_o
) # decoded-LD
552 comb
+= pi
.is_st_i
.eq(op_is_st_or_dcbz
& busy_o
) # decoded-ST
553 comb
+= pi
.is_dcbz_i
.eq(op_is_dcbz
& busy_o
) # decoded-DCBZ
554 comb
+= pi
.reserve
.eq(oper_r
.reserve
& busy_o
) # atomic LR/SC
555 comb
+= pi
.data_len
.eq(oper_r
.data_len
) # data_len
556 # address: use sync to avoid long latency
557 sync
+= pi
.addr
.data
.eq(addr_r
) # EA from adder
558 with m
.If(op_is_dcbz
):
559 sync
+= Display("LDSTCompUnit.DCBZ: EA from adder %x", addr_r
)
561 sync
+= pi
.addr
.ok
.eq(alu_ok
& lsd_l
.q
) # "do address stuff" (once)
562 comb
+= self
.exc_o
.eq(pi
.exc_o
) # exception occurred
563 comb
+= addr_ok
.eq(self
.pi
.addr_ok_o
) # no exc, address fine
564 # connect MSR.PR etc. for priv/virt operation
565 comb
+= pi
.priv_mode
.eq(~oper_r
.msr
[MSR
.PR
])
566 comb
+= pi
.virt_mode
.eq(oper_r
.msr
[MSR
.DR
])
567 comb
+= pi
.mode_32bit
.eq(~oper_r
.msr
[MSR
.SF
])
568 with m
.If(self
.issue_i
): # display this only once
569 sync
+= Display("LDSTCompUnit: oper_r.msr %x pr=%x dr=%x sf=%x",
576 revnorev
= Signal(64, reset_less
=True)
577 with m
.If(oper_r
.byte_reverse
):
578 # byte-reverse the data based on ld/st width (turn it to LE)
579 data_len
= oper_r
.data_len
580 lddata_r
= byte_reverse(m
, 'lddata_r', pi
.ld
.data
, data_len
)
581 comb
+= revnorev
.eq(lddata_r
) # put reversed- data out
583 comb
+= revnorev
.eq(pi
.ld
.data
) # put data out, straight (as BE)
585 # then check sign-extend
586 with m
.If(oper_r
.sign_extend
):
587 # okok really should "if data_len == 4" and so on here
588 with m
.If(oper_r
.data_len
== 2):
589 comb
+= ldd_o
.eq(exts(revnorev
, 16, 64)) # sign-extend hword
591 comb
+= ldd_o
.eq(exts(revnorev
, 32, 64)) # sign-extend dword
593 comb
+= ldd_o
.eq(revnorev
)
595 # ld - ld gets latched in via lod_l
596 comb
+= ld_ok
.eq(pi
.ld
.ok
) # ld.ok *closes* (freezes) ld data
599 op3
= srl
[2] # 3rd operand latch
600 with m
.If(oper_r
.byte_reverse
):
601 # byte-reverse the data based on width
602 data_len
= oper_r
.data_len
603 stdata_r
= byte_reverse(m
, 'stdata_r', op3
, data_len
)
604 comb
+= pi
.st
.data
.eq(stdata_r
)
606 comb
+= pi
.st
.data
.eq(op3
)
608 # store - data goes in based on go_st
609 comb
+= pi
.st
.ok
.eq(self
.st
.go_i
) # go store signals st data valid
611 # store actioned, communicate through CR0 (for atomic LR/SC)
612 comb
+= store_done
.eq(pi
.store_done
)
616 def get_out(self
, i
):
617 """make LDSTCompUnit look like RegSpecALUAPI. these correspond
618 to LDSTOutputData o and o1 respectively.
621 return self
.o_data
# LDSTOutputData.regspec o
623 return self
.addr_o
# LDSTOutputData.regspec o1
625 return self
.cr_o
# LDSTOutputData.regspec cr_a
626 # return self.dest[i]
628 def get_fu_out(self
, i
):
629 return self
.get_out(i
)
639 yield from self
.oper_i
.ports()
640 yield from self
.src_i
646 yield from self
.o_data
.ports()
647 yield from self
.addr_o
.ports()
648 yield from self
.cr_o
.ports()
649 yield self
.load_mem_o
650 yield self
.stwd_mem_o
656 def wait_for(sig
, wait
=True, test1st
=False):
658 print("wait for", sig
, v
, wait
, test1st
)
659 if test1st
and bool(v
) == wait
:
664 #print("...wait for", sig, v)
669 def store(dut
, src1
, src2
, src3
, imm
, imm_ok
=True, update
=False,
671 print("ST", src1
, src2
, src3
, imm
, imm_ok
, update
)
672 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_STORE
)
673 yield dut
.oper_i
.data_len
.eq(2) # half-word
674 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
675 yield dut
.src1_i
.eq(src1
)
676 yield dut
.src2_i
.eq(src2
)
677 yield dut
.src3_i
.eq(src3
)
678 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
679 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
680 #guess: this one was removed -- yield dut.oper_i.update.eq(update)
681 yield dut
.issue_i
.eq(1)
683 yield dut
.issue_i
.eq(0)
689 # wait for all active rel signals to come up
691 rel
= yield dut
.rd
.rel_o
692 if rel
== active_rel
:
695 yield dut
.rd
.go_i
.eq(active_rel
)
697 yield dut
.rd
.go_i
.eq(0)
699 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
700 # yield from wait_for(dut.adr_rel_o)
701 # yield dut.ad.go.eq(1)
703 # yield dut.ad.go.eq(0)
706 yield from wait_for(dut
.wr
.rel_o
[1])
707 yield dut
.wr
.go
.eq(0b10)
709 addr
= yield dut
.addr_o
711 yield dut
.wr
.go
.eq(0)
715 yield from wait_for(dut
.sto_rel_o
)
716 yield dut
.go_st_i
.eq(1)
718 yield dut
.go_st_i
.eq(0)
719 yield from wait_for(dut
.busy_o
, False)
720 # wait_for(dut.stwd_mem_o)
725 def load(dut
, src1
, src2
, imm
, imm_ok
=True, update
=False, zero_a
=False,
727 print("LD", src1
, src2
, imm
, imm_ok
, update
)
728 yield dut
.oper_i
.insn_type
.eq(MicrOp
.OP_LOAD
)
729 yield dut
.oper_i
.data_len
.eq(2) # half-word
730 yield dut
.oper_i
.byte_reverse
.eq(byterev
)
731 yield dut
.src1_i
.eq(src1
)
732 yield dut
.src2_i
.eq(src2
)
733 yield dut
.oper_i
.zero_a
.eq(zero_a
)
734 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
735 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
736 yield dut
.issue_i
.eq(1)
738 yield dut
.issue_i
.eq(0)
741 # set up read-operand flags
743 if not imm_ok
: # no immediate means RB register needs to be read
745 if not zero_a
: # no zero-a means RA needs to be read
748 # wait for the operands (RA, RB, or both)
750 yield dut
.rd
.go_i
.eq(rd
)
751 yield from wait_for(dut
.rd
.rel_o
)
752 yield dut
.rd
.go_i
.eq(0)
754 yield from wait_for(dut
.adr_rel_o
, False, test1st
=True)
755 # yield dut.ad.go.eq(1)
757 # yield dut.ad.go.eq(0)
760 yield from wait_for(dut
.wr
.rel_o
[1])
761 yield dut
.wr
.go_i
.eq(0b10)
763 addr
= yield dut
.addr_o
765 yield dut
.wr
.go_i
.eq(0)
769 yield from wait_for(dut
.wr
.rel_o
[0], test1st
=True)
770 yield dut
.wr
.go_i
.eq(1)
772 data
= yield dut
.o_data
.o
773 data_ok
= yield dut
.o_data
.o_ok
774 yield dut
.wr
.go_i
.eq(0)
775 yield from wait_for(dut
.busy_o
)
777 # wait_for(dut.stwd_mem_o)
778 return data
, data_ok
, addr
786 # two STs (different addresses)
787 yield from store(dut
, 4, 0, 3, 2) # ST reg4 into addr rfile[reg3]+2
788 yield from store(dut
, 2, 0, 9, 2) # ST reg4 into addr rfile[reg9]+2
790 # two LDs (deliberately LD from the 1st address then 2nd)
791 data
, addr
= yield from load(dut
, 4, 0, 2)
792 assert data
== 0x0003, "returned %x" % data
793 data
, addr
= yield from load(dut
, 2, 0, 2)
794 assert data
== 0x0009, "returned %x" % data
798 yield from store(dut
, 9, 5, 3, 0, imm_ok
=False)
799 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False)
800 assert data
== 0x0003, "returned %x" % data
802 # update-immediate version
803 addr
= yield from store(dut
, 9, 6, 3, 2, update
=True)
804 assert addr
== 0x000b, "returned %x" % addr
806 # update-indexed version
807 data
, addr
= yield from load(dut
, 9, 5, 0, imm_ok
=False, update
=True)
808 assert data
== 0x0003, "returned %x" % data
809 assert addr
== 0x000e, "returned %x" % addr
811 # immediate *and* zero version
812 data
, addr
= yield from load(dut
, 1, 4, 8, imm_ok
=True, zero_a
=True)
813 assert data
== 0x0008, "returned %x" % data
816 class TestLDSTCompUnit(LDSTCompUnit
):
818 def __init__(self
, rwid
, pspec
):
819 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
820 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
822 LDSTCompUnit
.__init
__(self
, pi
, rwid
, 4)
824 def elaborate(self
, platform
):
825 m
= LDSTCompUnit
.elaborate(self
, platform
)
826 m
.submodules
.l0
= self
.l0
827 # link addr-go direct to rel
828 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
832 def test_scoreboard():
835 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
836 imem_ifacetype
='bare_wb',
842 dut
= TestLDSTCompUnit(16,pspec
)
843 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
844 with
open("test_ldst_comp.il", "w") as f
:
847 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_comp.vcd')
850 class TestLDSTCompUnitRegSpec(LDSTCompUnit
):
852 def __init__(self
, pspec
):
853 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
854 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
855 regspec
= LDSTPipeSpec
.regspec
856 self
.l0
= l0
= TstL0CacheBuffer(pspec
)
858 LDSTCompUnit
.__init
__(self
, pi
, regspec
, 4)
860 def elaborate(self
, platform
):
861 m
= LDSTCompUnit
.elaborate(self
, platform
)
862 m
.submodules
.l0
= self
.l0
863 # link addr-go direct to rel
864 m
.d
.comb
+= self
.ad
.go_i
.eq(self
.ad
.rel_o
)
868 def test_scoreboard_regspec():
871 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
872 imem_ifacetype
='bare_wb',
878 dut
= TestLDSTCompUnitRegSpec(pspec
)
879 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
880 with
open("test_ldst_comp.il", "w") as f
:
883 run_simulation(dut
, ldst_sim(dut
), vcd_name
='test_ldst_regspec.vcd')
886 if __name__
== '__main__':
887 test_scoreboard_regspec()