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[soc.git] / src / soc / experiment / dcache.py
1 """DCache
2
3 based on Anton Blanchard microwatt dcache.vhdl
4
5 """
6
7 from enum import Enum, unique
8
9 from nmigen import Module, Signal, Elaboratable, Cat, Repl, Array, Const
10 try:
11 from nmigen.hdl.ast import Display
12 except ImportError:
13 def Display(*args):
14 return []
15
16 from nmigen.cli import main
17 from nmutil.iocontrol import RecordObject
18 from nmutil.util import wrap
19 from nmigen.utils import log2_int
20 from soc.experiment.mem_types import (LoadStore1ToDCacheType,
21 DCacheToLoadStore1Type,
22 MMUToDCacheType,
23 DCacheToMMUType)
24
25 from soc.experiment.wb_types import (WB_ADDR_BITS, WB_DATA_BITS, WB_SEL_BITS,
26 WBAddrType, WBDataType, WBSelType,
27 WBMasterOut, WBSlaveOut,
28 WBMasterOutVector, WBSlaveOutVector,
29 WBIOMasterOut, WBIOSlaveOut)
30
31 from soc.experiment.cache_ram import CacheRam
32 from soc.experiment.plru import PLRU
33
34 # for test
35 from nmigen_soc.wishbone.sram import SRAM
36 from nmigen import Memory
37 from nmigen.cli import rtlil
38 if True:
39 from nmigen.back.pysim import Simulator, Delay, Settle
40 else:
41 from nmigen.sim.cxxsim import Simulator, Delay, Settle
42
43
44 # TODO: make these parameters of DCache at some point
45 LINE_SIZE = 64 # Line size in bytes
46 NUM_LINES = 16 # Number of lines in a set
47 NUM_WAYS = 4 # Number of ways
48 TLB_SET_SIZE = 64 # L1 DTLB entries per set
49 TLB_NUM_WAYS = 2 # L1 DTLB number of sets
50 TLB_LG_PGSZ = 12 # L1 DTLB log_2(page_size)
51 LOG_LENGTH = 0 # Non-zero to enable log data collection
52
53 # BRAM organisation: We never access more than
54 # -- WB_DATA_BITS at a time so to save
55 # -- resources we make the array only that wide, and
56 # -- use consecutive indices for to make a cache "line"
57 # --
58 # -- ROW_SIZE is the width in bytes of the BRAM
59 # -- (based on WB, so 64-bits)
60 ROW_SIZE = WB_DATA_BITS // 8;
61
62 # ROW_PER_LINE is the number of row (wishbone
63 # transactions) in a line
64 ROW_PER_LINE = LINE_SIZE // ROW_SIZE
65
66 # BRAM_ROWS is the number of rows in BRAM needed
67 # to represent the full dcache
68 BRAM_ROWS = NUM_LINES * ROW_PER_LINE
69
70
71 # Bit fields counts in the address
72
73 # REAL_ADDR_BITS is the number of real address
74 # bits that we store
75 REAL_ADDR_BITS = 56
76
77 # ROW_BITS is the number of bits to select a row
78 ROW_BITS = log2_int(BRAM_ROWS)
79
80 # ROW_LINE_BITS is the number of bits to select
81 # a row within a line
82 ROW_LINE_BITS = log2_int(ROW_PER_LINE)
83
84 # LINE_OFF_BITS is the number of bits for
85 # the offset in a cache line
86 LINE_OFF_BITS = log2_int(LINE_SIZE)
87
88 # ROW_OFF_BITS is the number of bits for
89 # the offset in a row
90 ROW_OFF_BITS = log2_int(ROW_SIZE)
91
92 # INDEX_BITS is the number if bits to
93 # select a cache line
94 INDEX_BITS = log2_int(NUM_LINES)
95
96 # SET_SIZE_BITS is the log base 2 of the set size
97 SET_SIZE_BITS = LINE_OFF_BITS + INDEX_BITS
98
99 # TAG_BITS is the number of bits of
100 # the tag part of the address
101 TAG_BITS = REAL_ADDR_BITS - SET_SIZE_BITS
102
103 # TAG_WIDTH is the width in bits of each way of the tag RAM
104 TAG_WIDTH = TAG_BITS + 7 - ((TAG_BITS + 7) % 8)
105
106 # WAY_BITS is the number of bits to select a way
107 WAY_BITS = log2_int(NUM_WAYS)
108
109 # Example of layout for 32 lines of 64 bytes:
110 #
111 # .. tag |index| line |
112 # .. | row | |
113 # .. | |---| | ROW_LINE_BITS (3)
114 # .. | |--- - --| LINE_OFF_BITS (6)
115 # .. | |- --| ROW_OFF_BITS (3)
116 # .. |----- ---| | ROW_BITS (8)
117 # .. |-----| | INDEX_BITS (5)
118 # .. --------| | TAG_BITS (45)
119
120 TAG_RAM_WIDTH = TAG_WIDTH * NUM_WAYS
121
122 def CacheTagArray():
123 return Array(Signal(TAG_RAM_WIDTH) for x in range(NUM_LINES))
124
125 def CacheValidBitsArray():
126 return Array(Signal(INDEX_BITS) for x in range(NUM_LINES))
127
128 def RowPerLineValidArray():
129 return Array(Signal(name="rows_valid%d" % x) for x in range(ROW_PER_LINE))
130
131 # L1 TLB
132 TLB_SET_BITS = log2_int(TLB_SET_SIZE)
133 TLB_WAY_BITS = log2_int(TLB_NUM_WAYS)
134 TLB_EA_TAG_BITS = 64 - (TLB_LG_PGSZ + TLB_SET_BITS)
135 TLB_TAG_WAY_BITS = TLB_NUM_WAYS * TLB_EA_TAG_BITS
136 TLB_PTE_BITS = 64
137 TLB_PTE_WAY_BITS = TLB_NUM_WAYS * TLB_PTE_BITS;
138
139 assert (LINE_SIZE % ROW_SIZE) == 0, "LINE_SIZE not multiple of ROW_SIZE"
140 assert (LINE_SIZE % 2) == 0, "LINE_SIZE not power of 2"
141 assert (NUM_LINES % 2) == 0, "NUM_LINES not power of 2"
142 assert (ROW_PER_LINE % 2) == 0, "ROW_PER_LINE not power of 2"
143 assert ROW_BITS == (INDEX_BITS + ROW_LINE_BITS), "geometry bits don't add up"
144 assert (LINE_OFF_BITS == ROW_OFF_BITS + ROW_LINE_BITS), \
145 "geometry bits don't add up"
146 assert REAL_ADDR_BITS == (TAG_BITS + INDEX_BITS + LINE_OFF_BITS), \
147 "geometry bits don't add up"
148 assert REAL_ADDR_BITS == (TAG_BITS + ROW_BITS + ROW_OFF_BITS), \
149 "geometry bits don't add up"
150 assert 64 == WB_DATA_BITS, "Can't yet handle wb width that isn't 64-bits"
151 assert SET_SIZE_BITS <= TLB_LG_PGSZ, "Set indexed by virtual address"
152
153
154 def TLBValidBitsArray():
155 return Array(Signal(TLB_NUM_WAYS) for x in range(TLB_SET_SIZE))
156
157 def TLBTagEAArray():
158 return Array(Signal(TLB_EA_TAG_BITS) for x in range (TLB_NUM_WAYS))
159
160 def TLBTagsArray():
161 return Array(Signal(TLB_TAG_WAY_BITS) for x in range (TLB_SET_SIZE))
162
163 def TLBPtesArray():
164 return Array(Signal(TLB_PTE_WAY_BITS) for x in range(TLB_SET_SIZE))
165
166 def HitWaySet():
167 return Array(Signal(WAY_BITS) for x in range(TLB_NUM_WAYS))
168
169 # Cache RAM interface
170 def CacheRamOut():
171 return Array(Signal(WB_DATA_BITS) for x in range(NUM_WAYS))
172
173 # PLRU output interface
174 def PLRUOut():
175 return Array(Signal(WAY_BITS) for x in range(NUM_LINES))
176
177 # TLB PLRU output interface
178 def TLBPLRUOut():
179 return Array(Signal(TLB_WAY_BITS) for x in range(TLB_SET_SIZE))
180
181 # Helper functions to decode incoming requests
182 #
183 # Return the cache line index (tag index) for an address
184 def get_index(addr):
185 return addr[LINE_OFF_BITS:SET_SIZE_BITS]
186
187 # Return the cache row index (data memory) for an address
188 def get_row(addr):
189 return addr[ROW_OFF_BITS:SET_SIZE_BITS]
190
191 # Return the index of a row within a line
192 def get_row_of_line(row):
193 return row[:ROW_LINE_BITS]
194
195 # Returns whether this is the last row of a line
196 def is_last_row_addr(addr, last):
197 return addr[ROW_OFF_BITS:LINE_OFF_BITS] == last
198
199 # Returns whether this is the last row of a line
200 def is_last_row(row, last):
201 return get_row_of_line(row) == last
202
203 # Return the next row in the current cache line. We use a
204 # dedicated function in order to limit the size of the
205 # generated adder to be only the bits within a cache line
206 # (3 bits with default settings)
207 def next_row(row):
208 row_v = row[0:ROW_LINE_BITS] + 1
209 return Cat(row_v[:ROW_LINE_BITS], row[ROW_LINE_BITS:])
210
211 # Get the tag value from the address
212 def get_tag(addr):
213 return addr[SET_SIZE_BITS:REAL_ADDR_BITS]
214
215 # Read a tag from a tag memory row
216 def read_tag(way, tagset):
217 return tagset.word_select(way, TAG_WIDTH)[:TAG_BITS]
218
219 # Read a TLB tag from a TLB tag memory row
220 def read_tlb_tag(way, tags):
221 return tags.word_select(way, TLB_EA_TAG_BITS)
222
223 # Write a TLB tag to a TLB tag memory row
224 def write_tlb_tag(way, tags, tag):
225 return read_tlb_tag(way, tags).eq(tag)
226
227 # Read a PTE from a TLB PTE memory row
228 def read_tlb_pte(way, ptes):
229 return ptes.word_select(way, TLB_PTE_BITS)
230
231 def write_tlb_pte(way, ptes, newpte):
232 return read_tlb_pte(way, ptes).eq(newpte)
233
234
235 # Record for storing permission, attribute, etc. bits from a PTE
236 class PermAttr(RecordObject):
237 def __init__(self):
238 super().__init__()
239 self.reference = Signal()
240 self.changed = Signal()
241 self.nocache = Signal()
242 self.priv = Signal()
243 self.rd_perm = Signal()
244 self.wr_perm = Signal()
245
246
247 def extract_perm_attr(pte):
248 pa = PermAttr()
249 pa.reference = pte[8]
250 pa.changed = pte[7]
251 pa.nocache = pte[5]
252 pa.priv = pte[3]
253 pa.rd_perm = pte[2]
254 pa.wr_perm = pte[1]
255 return pa;
256
257
258 # Type of operation on a "valid" input
259 @unique
260 class Op(Enum):
261 OP_NONE = 0
262 OP_BAD = 1 # NC cache hit, TLB miss, prot/RC failure
263 OP_STCX_FAIL = 2 # conditional store w/o reservation
264 OP_LOAD_HIT = 3 # Cache hit on load
265 OP_LOAD_MISS = 4 # Load missing cache
266 OP_LOAD_NC = 5 # Non-cachable load
267 OP_STORE_HIT = 6 # Store hitting cache
268 OP_STORE_MISS = 7 # Store missing cache
269
270
271 # Cache state machine
272 @unique
273 class State(Enum):
274 IDLE = 0 # Normal load hit processing
275 RELOAD_WAIT_ACK = 1 # Cache reload wait ack
276 STORE_WAIT_ACK = 2 # Store wait ack
277 NC_LOAD_WAIT_ACK = 3 # Non-cachable load wait ack
278
279
280 # Dcache operations:
281 #
282 # In order to make timing, we use the BRAMs with
283 # an output buffer, which means that the BRAM
284 # output is delayed by an extra cycle.
285 #
286 # Thus, the dcache has a 2-stage internal pipeline
287 # for cache hits with no stalls.
288 #
289 # All other operations are handled via stalling
290 # in the first stage.
291 #
292 # The second stage can thus complete a hit at the same
293 # time as the first stage emits a stall for a complex op.
294 #
295 # Stage 0 register, basically contains just the latched request
296
297 class RegStage0(RecordObject):
298 def __init__(self, name=None):
299 super().__init__(name=name)
300 self.req = LoadStore1ToDCacheType(name="lsmem")
301 self.tlbie = Signal()
302 self.doall = Signal()
303 self.tlbld = Signal()
304 self.mmu_req = Signal() # indicates source of request
305
306
307 class MemAccessRequest(RecordObject):
308 def __init__(self, name=None):
309 super().__init__(name=name)
310 self.op = Signal(Op)
311 self.valid = Signal()
312 self.dcbz = Signal()
313 self.real_addr = Signal(REAL_ADDR_BITS)
314 self.data = Signal(64)
315 self.byte_sel = Signal(8)
316 self.hit_way = Signal(WAY_BITS)
317 self.same_tag = Signal()
318 self.mmu_req = Signal()
319
320
321 # First stage register, contains state for stage 1 of load hits
322 # and for the state machine used by all other operations
323 class RegStage1(RecordObject):
324 def __init__(self, name=None):
325 super().__init__(name=name)
326 # Info about the request
327 self.full = Signal() # have uncompleted request
328 self.mmu_req = Signal() # request is from MMU
329 self.req = MemAccessRequest(name="reqmem")
330
331 # Cache hit state
332 self.hit_way = Signal(WAY_BITS)
333 self.hit_load_valid = Signal()
334 self.hit_index = Signal(INDEX_BITS)
335 self.cache_hit = Signal()
336
337 # TLB hit state
338 self.tlb_hit = Signal()
339 self.tlb_hit_way = Signal(TLB_NUM_WAYS)
340 self.tlb_hit_index = Signal(TLB_WAY_BITS)
341
342 # 2-stage data buffer for data forwarded from writes to reads
343 self.forward_data1 = Signal(64)
344 self.forward_data2 = Signal(64)
345 self.forward_sel1 = Signal(8)
346 self.forward_valid1 = Signal()
347 self.forward_way1 = Signal(WAY_BITS)
348 self.forward_row1 = Signal(ROW_BITS)
349 self.use_forward1 = Signal()
350 self.forward_sel = Signal(8)
351
352 # Cache miss state (reload state machine)
353 self.state = Signal(State)
354 self.dcbz = Signal()
355 self.write_bram = Signal()
356 self.write_tag = Signal()
357 self.slow_valid = Signal()
358 self.wb = WBMasterOut()
359 self.reload_tag = Signal(TAG_BITS)
360 self.store_way = Signal(WAY_BITS)
361 self.store_row = Signal(ROW_BITS)
362 self.store_index = Signal(INDEX_BITS)
363 self.end_row_ix = Signal(log2_int(ROW_LINE_BITS, False))
364 self.rows_valid = RowPerLineValidArray()
365 self.acks_pending = Signal(3)
366 self.inc_acks = Signal()
367 self.dec_acks = Signal()
368
369 # Signals to complete (possibly with error)
370 self.ls_valid = Signal()
371 self.ls_error = Signal()
372 self.mmu_done = Signal()
373 self.mmu_error = Signal()
374 self.cache_paradox = Signal()
375
376 # Signal to complete a failed stcx.
377 self.stcx_fail = Signal()
378
379
380 # Reservation information
381 class Reservation(RecordObject):
382 def __init__(self):
383 super().__init__()
384 self.valid = Signal()
385 self.addr = Signal(64-LINE_OFF_BITS)
386
387
388 class DTLBUpdate(Elaboratable):
389 def __init__(self):
390 self.tlbie = Signal()
391 self.tlbwe = Signal()
392 self.doall = Signal()
393 self.updated = Signal()
394 self.v_updated = Signal()
395 self.tlb_hit = Signal()
396 self.tlb_req_index = Signal(TLB_SET_BITS)
397
398 self.tlb_hit_way = Signal(TLB_WAY_BITS)
399 self.tlb_tag_way = Signal(TLB_TAG_WAY_BITS)
400 self.tlb_pte_way = Signal(TLB_PTE_WAY_BITS)
401 self.repl_way = Signal(TLB_WAY_BITS)
402 self.eatag = Signal(TLB_EA_TAG_BITS)
403 self.pte_data = Signal(TLB_PTE_BITS)
404
405 self.dv = Signal(TLB_PTE_WAY_BITS)
406
407 self.tb_out = Signal(TLB_TAG_WAY_BITS)
408 self.pb_out = Signal(TLB_NUM_WAYS)
409 self.db_out = Signal(TLB_PTE_WAY_BITS)
410
411 def elaborate(self, platform):
412 m = Module()
413 comb = m.d.comb
414 sync = m.d.sync
415
416 tagset = Signal(TLB_TAG_WAY_BITS)
417 pteset = Signal(TLB_PTE_WAY_BITS)
418
419 tb_out, pb_out, db_out = self.tb_out, self.pb_out, self.db_out
420
421 with m.If(self.tlbie & self.doall):
422 pass # clear all back in parent
423 with m.Elif(self.tlbie):
424 with m.If(self.tlb_hit):
425 comb += db_out.eq(self.dv)
426 comb += db_out.bit_select(self.tlb_hit_way, 1).eq(1)
427 comb += self.v_updated.eq(1)
428
429 with m.Elif(self.tlbwe):
430
431 comb += tagset.eq(self.tlb_tag_way)
432 comb += write_tlb_tag(self.repl_way, tagset, self.eatag)
433 comb += tb_out.eq(tagset)
434
435 comb += pteset.eq(self.tlb_pte_way)
436 comb += write_tlb_pte(self.repl_way, pteset, self.pte_data)
437 comb += pb_out.eq(pteset)
438
439 comb += db_out.bit_select(self.repl_way, 1).eq(1)
440
441 comb += self.updated.eq(1)
442 comb += self.v_updated.eq(1)
443
444 return m
445
446 def dcache_request(self, m, r0, ra, req_index, req_row, req_tag,
447 r0_valid, r1, cache_valid_bits, replace_way,
448 use_forward1_next, use_forward2_next,
449 req_hit_way, plru_victim, rc_ok, perm_attr,
450 valid_ra, perm_ok, access_ok, req_op, req_go,
451 tlb_pte_way,
452 tlb_hit, tlb_hit_way, tlb_valid_way, cache_tag_set,
453 cancel_store, req_same_tag, r0_stall, early_req_row):
454 """Cache request parsing and hit detection
455 """
456
457 class DCachePendingHit(Elaboratable):
458
459 def __init__(self, tlb_pte_way, tlb_valid_way, tlb_hit_way,
460 cache_valid_idx, cache_tag_set,
461 req_addr,
462 hit_set):
463
464 self.go = Signal()
465 self.virt_mode = Signal()
466 self.is_hit = Signal()
467 self.tlb_hit = Signal()
468 self.hit_way = Signal(WAY_BITS)
469 self.rel_match = Signal()
470 self.req_index = Signal(INDEX_BITS)
471 self.reload_tag = Signal(TAG_BITS)
472
473 self.tlb_hit_way = tlb_hit_way
474 self.tlb_pte_way = tlb_pte_way
475 self.tlb_valid_way = tlb_valid_way
476 self.cache_valid_idx = cache_valid_idx
477 self.cache_tag_set = cache_tag_set
478 self.req_addr = req_addr
479 self.hit_set = hit_set
480
481 def elaborate(self, platform):
482 m = Module()
483 comb = m.d.comb
484 sync = m.d.sync
485
486 go = self.go
487 virt_mode = self.virt_mode
488 is_hit = self.is_hit
489 tlb_pte_way = self.tlb_pte_way
490 tlb_valid_way = self.tlb_valid_way
491 cache_valid_idx = self.cache_valid_idx
492 cache_tag_set = self.cache_tag_set
493 req_addr = self.req_addr
494 tlb_hit_way = self.tlb_hit_way
495 tlb_hit = self.tlb_hit
496 hit_set = self.hit_set
497 hit_way = self.hit_way
498 rel_match = self.rel_match
499 req_index = self.req_index
500 reload_tag = self.reload_tag
501
502 rel_matches = Array(Signal() for i in range(TLB_NUM_WAYS))
503 hit_way_set = HitWaySet()
504
505 # Test if pending request is a hit on any way
506 # In order to make timing in virtual mode,
507 # when we are using the TLB, we compare each
508 # way with each of the real addresses from each way of
509 # the TLB, and then decide later which match to use.
510
511 with m.If(virt_mode):
512 for j in range(TLB_NUM_WAYS):
513 s_tag = Signal(TAG_BITS, name="s_tag%d" % j)
514 s_hit = Signal()
515 s_pte = Signal(TLB_PTE_BITS)
516 s_ra = Signal(REAL_ADDR_BITS)
517 comb += s_pte.eq(read_tlb_pte(j, tlb_pte_way))
518 comb += s_ra.eq(Cat(req_addr[0:TLB_LG_PGSZ],
519 s_pte[TLB_LG_PGSZ:REAL_ADDR_BITS]))
520 comb += s_tag.eq(get_tag(s_ra))
521
522 for i in range(NUM_WAYS):
523 is_tag_hit = Signal()
524 comb += is_tag_hit.eq(go & cache_valid_idx[i] &
525 (read_tag(i, cache_tag_set) == s_tag)
526 & tlb_valid_way[j])
527 with m.If(is_tag_hit):
528 comb += hit_way_set[j].eq(i)
529 comb += s_hit.eq(1)
530 comb += hit_set[j].eq(s_hit)
531 with m.If(s_tag == reload_tag):
532 comb += rel_matches[j].eq(1)
533 with m.If(tlb_hit):
534 comb += is_hit.eq(hit_set[tlb_hit_way])
535 comb += hit_way.eq(hit_way_set[tlb_hit_way])
536 comb += rel_match.eq(rel_matches[tlb_hit_way])
537 with m.Else():
538 s_tag = Signal(TAG_BITS)
539 comb += s_tag.eq(get_tag(req_addr))
540 for i in range(NUM_WAYS):
541 is_tag_hit = Signal()
542 comb += is_tag_hit.eq(go & cache_valid_idx[i] &
543 read_tag(i, cache_tag_set) == s_tag)
544 with m.If(is_tag_hit):
545 comb += hit_way.eq(i)
546 comb += is_hit.eq(1)
547 with m.If(s_tag == reload_tag):
548 comb += rel_match.eq(1)
549
550 return m
551
552
553 class DCache(Elaboratable):
554 """Set associative dcache write-through
555 TODO (in no specific order):
556 * See list in icache.vhdl
557 * Complete load misses on the cycle when WB data comes instead of
558 at the end of line (this requires dealing with requests coming in
559 while not idle...)
560 """
561 def __init__(self):
562 self.d_in = LoadStore1ToDCacheType("d_in")
563 self.d_out = DCacheToLoadStore1Type("d_out")
564
565 self.m_in = MMUToDCacheType("m_in")
566 self.m_out = DCacheToMMUType("m_out")
567
568 self.stall_out = Signal()
569
570 self.wb_out = WBMasterOut()
571 self.wb_in = WBSlaveOut()
572
573 self.log_out = Signal(20)
574
575 def stage_0(self, m, r0, r1, r0_full):
576 """Latch the request in r0.req as long as we're not stalling
577 """
578 comb = m.d.comb
579 sync = m.d.sync
580 d_in, d_out, m_in = self.d_in, self.d_out, self.m_in
581
582 r = RegStage0("stage0")
583
584 # TODO, this goes in unit tests and formal proofs
585 with m.If(~(d_in.valid & m_in.valid)):
586 #sync += Display("request collision loadstore vs MMU")
587 pass
588
589 with m.If(m_in.valid):
590 sync += r.req.valid.eq(1)
591 sync += r.req.load.eq(~(m_in.tlbie | m_in.tlbld))
592 sync += r.req.dcbz.eq(0)
593 sync += r.req.nc.eq(0)
594 sync += r.req.reserve.eq(0)
595 sync += r.req.virt_mode.eq(1)
596 sync += r.req.priv_mode.eq(1)
597 sync += r.req.addr.eq(m_in.addr)
598 sync += r.req.data.eq(m_in.pte)
599 sync += r.req.byte_sel.eq(~0) # Const -1 sets all to 0b111....
600 sync += r.tlbie.eq(m_in.tlbie)
601 sync += r.doall.eq(m_in.doall)
602 sync += r.tlbld.eq(m_in.tlbld)
603 sync += r.mmu_req.eq(1)
604 with m.Else():
605 sync += r.req.eq(d_in)
606 sync += r.tlbie.eq(0)
607 sync += r.doall.eq(0)
608 sync += r.tlbld.eq(0)
609 sync += r.mmu_req.eq(0)
610 with m.If(~(r1.full & r0_full)):
611 sync += r0.eq(r)
612 sync += r0_full.eq(r.req.valid)
613
614 def tlb_read(self, m, r0_stall, tlb_valid_way,
615 tlb_tag_way, tlb_pte_way, dtlb_valid_bits,
616 dtlb_tags, dtlb_ptes):
617 """TLB
618 Operates in the second cycle on the request latched in r0.req.
619 TLB updates write the entry at the end of the second cycle.
620 """
621 comb = m.d.comb
622 sync = m.d.sync
623 m_in, d_in = self.m_in, self.d_in
624
625 index = Signal(TLB_SET_BITS)
626 addrbits = Signal(TLB_SET_BITS)
627
628 amin = TLB_LG_PGSZ
629 amax = TLB_LG_PGSZ + TLB_SET_BITS
630
631 with m.If(m_in.valid):
632 comb += addrbits.eq(m_in.addr[amin : amax])
633 with m.Else():
634 comb += addrbits.eq(d_in.addr[amin : amax])
635 comb += index.eq(addrbits)
636
637 # If we have any op and the previous op isn't finished,
638 # then keep the same output for next cycle.
639 with m.If(~r0_stall):
640 sync += tlb_valid_way.eq(dtlb_valid_bits[index])
641 sync += tlb_tag_way.eq(dtlb_tags[index])
642 sync += tlb_pte_way.eq(dtlb_ptes[index])
643
644 def maybe_tlb_plrus(self, m, r1, tlb_plru_victim):
645 """Generate TLB PLRUs
646 """
647 comb = m.d.comb
648 sync = m.d.sync
649
650 if TLB_NUM_WAYS == 0:
651 return
652 for i in range(TLB_SET_SIZE):
653 # TLB PLRU interface
654 tlb_plru = PLRU(WAY_BITS)
655 setattr(m.submodules, "maybe_plru_%d" % i, tlb_plru)
656 tlb_plru_acc_en = Signal()
657
658 comb += tlb_plru_acc_en.eq(r1.tlb_hit & (r1.tlb_hit_index == i))
659 comb += tlb_plru.acc_en.eq(tlb_plru_acc_en)
660 comb += tlb_plru.acc.eq(r1.tlb_hit_way)
661 comb += tlb_plru_victim[i].eq(tlb_plru.lru_o)
662
663 def tlb_search(self, m, tlb_req_index, r0, r0_valid,
664 tlb_valid_way, tlb_tag_way, tlb_hit_way,
665 tlb_pte_way, pte, tlb_hit, valid_ra, perm_attr, ra):
666
667 comb = m.d.comb
668 sync = m.d.sync
669
670 hitway = Signal(TLB_WAY_BITS)
671 hit = Signal()
672 eatag = Signal(TLB_EA_TAG_BITS)
673
674 TLB_LG_END = TLB_LG_PGSZ + TLB_SET_BITS
675 comb += tlb_req_index.eq(r0.req.addr[TLB_LG_PGSZ : TLB_LG_END])
676 comb += eatag.eq(r0.req.addr[TLB_LG_END : 64 ])
677
678 for i in range(TLB_NUM_WAYS):
679 is_tag_hit = Signal()
680 comb += is_tag_hit.eq(tlb_valid_way[i]
681 & read_tlb_tag(i, tlb_tag_way) == eatag)
682 with m.If(is_tag_hit):
683 comb += hitway.eq(i)
684 comb += hit.eq(1)
685
686 comb += tlb_hit.eq(hit & r0_valid)
687 comb += tlb_hit_way.eq(hitway)
688
689 with m.If(tlb_hit):
690 comb += pte.eq(read_tlb_pte(hitway, tlb_pte_way))
691 with m.Else():
692 comb += pte.eq(0)
693 comb += valid_ra.eq(tlb_hit | ~r0.req.virt_mode)
694 with m.If(r0.req.virt_mode):
695 comb += ra.eq(Cat(Const(0, ROW_OFF_BITS),
696 r0.req.addr[ROW_OFF_BITS:TLB_LG_PGSZ],
697 pte[TLB_LG_PGSZ:REAL_ADDR_BITS]))
698 comb += perm_attr.eq(extract_perm_attr(pte))
699 with m.Else():
700 comb += ra.eq(Cat(Const(0, ROW_OFF_BITS),
701 r0.req.addr[ROW_OFF_BITS:REAL_ADDR_BITS]))
702
703 comb += perm_attr.reference.eq(1)
704 comb += perm_attr.changed.eq(1)
705 comb += perm_attr.priv.eq(1)
706 comb += perm_attr.nocache.eq(0)
707 comb += perm_attr.rd_perm.eq(1)
708 comb += perm_attr.wr_perm.eq(1)
709
710 def tlb_update(self, m, r0_valid, r0, dtlb_valid_bits, tlb_req_index,
711 tlb_hit_way, tlb_hit, tlb_plru_victim, tlb_tag_way,
712 dtlb_tags, tlb_pte_way, dtlb_ptes):
713
714 comb = m.d.comb
715 sync = m.d.sync
716
717 tlbie = Signal()
718 tlbwe = Signal()
719
720 comb += tlbie.eq(r0_valid & r0.tlbie)
721 comb += tlbwe.eq(r0_valid & r0.tlbld)
722
723 m.submodules.tlb_update = d = DTLBUpdate()
724 with m.If(tlbie & r0.doall):
725 # clear all valid bits at once
726 for i in range(TLB_SET_SIZE):
727 sync += dtlb_valid_bits[i].eq(0)
728 with m.If(d.updated):
729 sync += dtlb_tags[tlb_req_index].eq(d.tb_out)
730 sync += dtlb_ptes[tlb_req_index].eq(d.pb_out)
731 with m.If(d.v_updated):
732 sync += dtlb_valid_bits[tlb_req_index].eq(d.db_out)
733
734 comb += d.dv.eq(dtlb_valid_bits[tlb_req_index])
735
736 comb += d.tlbie.eq(tlbie)
737 comb += d.tlbwe.eq(tlbwe)
738 comb += d.doall.eq(r0.doall)
739 comb += d.tlb_hit.eq(tlb_hit)
740 comb += d.tlb_hit_way.eq(tlb_hit_way)
741 comb += d.tlb_tag_way.eq(tlb_tag_way)
742 comb += d.tlb_pte_way.eq(tlb_pte_way)
743 comb += d.tlb_req_index.eq(tlb_req_index)
744
745 with m.If(tlb_hit):
746 comb += d.repl_way.eq(tlb_hit_way)
747 with m.Else():
748 comb += d.repl_way.eq(tlb_plru_victim[tlb_req_index])
749 comb += d.eatag.eq(r0.req.addr[TLB_LG_PGSZ + TLB_SET_BITS:64])
750 comb += d.pte_data.eq(r0.req.data)
751
752 def maybe_plrus(self, m, r1, plru_victim):
753 """Generate PLRUs
754 """
755 comb = m.d.comb
756 sync = m.d.sync
757
758 if TLB_NUM_WAYS == 0:
759 return
760
761 for i in range(NUM_LINES):
762 # PLRU interface
763 plru = PLRU(WAY_BITS)
764 setattr(m.submodules, "plru%d" % i, plru)
765 plru_acc_en = Signal()
766
767 comb += plru_acc_en.eq(r1.cache_hit & (r1.hit_index == i))
768 comb += plru.acc_en.eq(plru_acc_en)
769 comb += plru.acc.eq(r1.hit_way)
770 comb += plru_victim[i].eq(plru.lru_o)
771
772 def cache_tag_read(self, m, r0_stall, req_index, cache_tag_set, cache_tags):
773 """Cache tag RAM read port
774 """
775 comb = m.d.comb
776 sync = m.d.sync
777 m_in, d_in = self.m_in, self.d_in
778
779 index = Signal(INDEX_BITS)
780
781 with m.If(r0_stall):
782 comb += index.eq(req_index)
783 with m.Elif(m_in.valid):
784 comb += index.eq(get_index(m_in.addr))
785 with m.Else():
786 comb += index.eq(get_index(d_in.addr))
787 sync += cache_tag_set.eq(cache_tags[index])
788
789 def dcache_request(self, m, r0, ra, req_index, req_row, req_tag,
790 r0_valid, r1, cache_valid_bits, replace_way,
791 use_forward1_next, use_forward2_next,
792 req_hit_way, plru_victim, rc_ok, perm_attr,
793 valid_ra, perm_ok, access_ok, req_op, req_go,
794 tlb_pte_way,
795 tlb_hit, tlb_hit_way, tlb_valid_way, cache_tag_set,
796 cancel_store, req_same_tag, r0_stall, early_req_row):
797 """Cache request parsing and hit detection
798 """
799
800 comb = m.d.comb
801 sync = m.d.sync
802 m_in, d_in = self.m_in, self.d_in
803
804 is_hit = Signal()
805 hit_way = Signal(WAY_BITS)
806 op = Signal(Op)
807 opsel = Signal(3)
808 go = Signal()
809 nc = Signal()
810 hit_set = Array(Signal() for i in range(TLB_NUM_WAYS))
811 cache_valid_idx = Signal(INDEX_BITS)
812
813 # Extract line, row and tag from request
814 comb += req_index.eq(get_index(r0.req.addr))
815 comb += req_row.eq(get_row(r0.req.addr))
816 comb += req_tag.eq(get_tag(ra))
817
818 comb += go.eq(r0_valid & ~(r0.tlbie | r0.tlbld) & ~r1.ls_error)
819 comb += cache_valid_idx.eq(cache_valid_bits[req_index])
820
821 m.submodules.dcache_pend = dc = DCachePendingHit(tlb_pte_way,
822 tlb_valid_way, tlb_hit_way,
823 cache_valid_idx, cache_tag_set,
824 r0.req.addr,
825 hit_set)
826
827 comb += dc.tlb_hit.eq(tlb_hit)
828 comb += dc.reload_tag.eq(r1.reload_tag)
829 comb += dc.virt_mode.eq(r0.req.virt_mode)
830 comb += dc.go.eq(go)
831 comb += dc.req_index.eq(req_index)
832 comb += is_hit.eq(dc.is_hit)
833 comb += hit_way.eq(dc.hit_way)
834 comb += req_same_tag.eq(dc.rel_match)
835
836 # See if the request matches the line currently being reloaded
837 with m.If((r1.state == State.RELOAD_WAIT_ACK) &
838 (req_index == r1.store_index) & req_same_tag):
839 # For a store, consider this a hit even if the row isn't
840 # valid since it will be by the time we perform the store.
841 # For a load, check the appropriate row valid bit.
842 valid = r1.rows_valid[req_row % ROW_PER_LINE]
843 comb += is_hit.eq(~r0.req.load | valid)
844 comb += hit_way.eq(replace_way)
845
846 # Whether to use forwarded data for a load or not
847 comb += use_forward1_next.eq(0)
848 with m.If((get_row(r1.req.real_addr) == req_row) &
849 (r1.req.hit_way == hit_way)):
850 # Only need to consider r1.write_bram here, since if we
851 # are writing refill data here, then we don't have a
852 # cache hit this cycle on the line being refilled.
853 # (There is the possibility that the load following the
854 # load miss that started the refill could be to the old
855 # contents of the victim line, since it is a couple of
856 # cycles after the refill starts before we see the updated
857 # cache tag. In that case we don't use the bypass.)
858 comb += use_forward1_next.eq(r1.write_bram)
859 comb += use_forward2_next.eq(0)
860 with m.If((r1.forward_row1 == req_row) & (r1.forward_way1 == hit_way)):
861 comb += use_forward2_next.eq(r1.forward_valid1)
862
863 # The way that matched on a hit
864 comb += req_hit_way.eq(hit_way)
865
866 # The way to replace on a miss
867 with m.If(r1.write_tag):
868 comb += replace_way.eq(plru_victim[r1.store_index])
869 with m.Else():
870 comb += replace_way.eq(r1.store_way)
871
872 # work out whether we have permission for this access
873 # NB we don't yet implement AMR, thus no KUAP
874 comb += rc_ok.eq(perm_attr.reference
875 & (r0.req.load | perm_attr.changed)
876 )
877 comb += perm_ok.eq((r0.req.priv_mode | ~perm_attr.priv)
878 & perm_attr.wr_perm
879 | (r0.req.load & perm_attr.rd_perm)
880 )
881 comb += access_ok.eq(valid_ra & perm_ok & rc_ok)
882 # Combine the request and cache hit status to decide what
883 # operation needs to be done
884 comb += nc.eq(r0.req.nc | perm_attr.nocache)
885 comb += op.eq(Op.OP_NONE)
886 with m.If(go):
887 with m.If(~access_ok):
888 comb += op.eq(Op.OP_BAD)
889 with m.Elif(cancel_store):
890 comb += op.eq(Op.OP_STCX_FAIL)
891 with m.Else():
892 comb += opsel.eq(Cat(is_hit, nc, r0.req.load))
893 with m.Switch(opsel):
894 with m.Case(0b101):
895 comb += op.eq(Op.OP_LOAD_HIT)
896 with m.Case(0b100):
897 comb += op.eq(Op.OP_LOAD_MISS)
898 with m.Case(0b110):
899 comb += op.eq(Op.OP_LOAD_NC)
900 with m.Case(0b001):
901 comb += op.eq(Op.OP_STORE_HIT)
902 with m.Case(0b000):
903 comb += op.eq(Op.OP_STORE_MISS)
904 with m.Case(0b010):
905 comb += op.eq(Op.OP_STORE_MISS)
906 with m.Case(0b011):
907 comb += op.eq(Op.OP_BAD)
908 with m.Case(0b111):
909 comb += op.eq(Op.OP_BAD)
910 with m.Default():
911 comb += op.eq(Op.OP_NONE)
912 comb += req_op.eq(op)
913 comb += req_go.eq(go)
914
915 # Version of the row number that is valid one cycle earlier
916 # in the cases where we need to read the cache data BRAM.
917 # If we're stalling then we need to keep reading the last
918 # row requested.
919 with m.If(~r0_stall):
920 with m.If(m_in.valid):
921 comb += early_req_row.eq(get_row(m_in.addr))
922 with m.Else():
923 comb += early_req_row.eq(get_row(d_in.addr))
924 with m.Else():
925 comb += early_req_row.eq(req_row)
926
927 def reservation_comb(self, m, cancel_store, set_rsrv, clear_rsrv,
928 r0_valid, r0, reservation):
929 """Handle load-with-reservation and store-conditional instructions
930 """
931 comb = m.d.comb
932 sync = m.d.sync
933
934 with m.If(r0_valid & r0.req.reserve):
935
936 # XXX generate alignment interrupt if address
937 # is not aligned XXX or if r0.req.nc = '1'
938 with m.If(r0.req.load):
939 comb += set_rsrv.eq(1) # load with reservation
940 with m.Else():
941 comb += clear_rsrv.eq(1) # store conditional
942 with m.If(~reservation.valid | r0.req.addr[LINE_OFF_BITS:64]):
943 comb += cancel_store.eq(1)
944
945 def reservation_reg(self, m, r0_valid, access_ok, set_rsrv, clear_rsrv,
946 reservation, r0):
947
948 comb = m.d.comb
949 sync = m.d.sync
950
951 with m.If(r0_valid & access_ok):
952 with m.If(clear_rsrv):
953 sync += reservation.valid.eq(0)
954 with m.Elif(set_rsrv):
955 sync += reservation.valid.eq(1)
956 sync += reservation.addr.eq(r0.req.addr[LINE_OFF_BITS:64])
957
958 def writeback_control(self, m, r1, cache_out):
959 """Return data for loads & completion control logic
960 """
961 comb = m.d.comb
962 sync = m.d.sync
963 d_out, m_out = self.d_out, self.m_out
964
965 data_out = Signal(64)
966 data_fwd = Signal(64)
967
968 # Use the bypass if are reading the row that was
969 # written 1 or 2 cycles ago, including for the
970 # slow_valid = 1 case (i.e. completing a load
971 # miss or a non-cacheable load).
972 with m.If(r1.use_forward1):
973 comb += data_fwd.eq(r1.forward_data1)
974 with m.Else():
975 comb += data_fwd.eq(r1.forward_data2)
976
977 comb += data_out.eq(cache_out[r1.hit_way])
978
979 for i in range(8):
980 with m.If(r1.forward_sel[i]):
981 dsel = data_fwd.word_select(i, 8)
982 comb += data_out.word_select(i, 8).eq(dsel)
983
984 comb += d_out.valid.eq(r1.ls_valid)
985 comb += d_out.data.eq(data_out)
986 comb += d_out.store_done.eq(~r1.stcx_fail)
987 comb += d_out.error.eq(r1.ls_error)
988 comb += d_out.cache_paradox.eq(r1.cache_paradox)
989
990 # Outputs to MMU
991 comb += m_out.done.eq(r1.mmu_done)
992 comb += m_out.err.eq(r1.mmu_error)
993 comb += m_out.data.eq(data_out)
994
995 # We have a valid load or store hit or we just completed
996 # a slow op such as a load miss, a NC load or a store
997 #
998 # Note: the load hit is delayed by one cycle. However it
999 # can still not collide with r.slow_valid (well unless I
1000 # miscalculated) because slow_valid can only be set on a
1001 # subsequent request and not on its first cycle (the state
1002 # machine must have advanced), which makes slow_valid
1003 # at least 2 cycles from the previous hit_load_valid.
1004
1005 # Sanity: Only one of these must be set in any given cycle
1006
1007 if False: # TODO: need Display to get this to work
1008 assert (r1.slow_valid & r1.stcx_fail) != 1, \
1009 "unexpected slow_valid collision with stcx_fail"
1010
1011 assert ((r1.slow_valid | r1.stcx_fail) | r1.hit_load_valid) != 1, \
1012 "unexpected hit_load_delayed collision with slow_valid"
1013
1014 with m.If(~r1.mmu_req):
1015 # Request came from loadstore1...
1016 # Load hit case is the standard path
1017 with m.If(r1.hit_load_valid):
1018 #Display(f"completing load hit data={data_out}")
1019 pass
1020
1021 # error cases complete without stalling
1022 with m.If(r1.ls_error):
1023 # Display("completing ld/st with error")
1024 pass
1025
1026 # Slow ops (load miss, NC, stores)
1027 with m.If(r1.slow_valid):
1028 #Display(f"completing store or load miss data={data_out}")
1029 pass
1030
1031 with m.Else():
1032 # Request came from MMU
1033 with m.If(r1.hit_load_valid):
1034 # Display(f"completing load hit to MMU, data={m_out.data}")
1035 pass
1036 # error cases complete without stalling
1037 with m.If(r1.mmu_error):
1038 #Display("combpleting MMU ld with error")
1039 pass
1040
1041 # Slow ops (i.e. load miss)
1042 with m.If(r1.slow_valid):
1043 #Display("completing MMU load miss, data={m_out.data}")
1044 pass
1045
1046 def rams(self, m, r1, early_req_row, cache_out, replace_way):
1047 """rams
1048 Generate a cache RAM for each way. This handles the normal
1049 reads, writes from reloads and the special store-hit update
1050 path as well.
1051
1052 Note: the BRAMs have an extra read buffer, meaning the output
1053 is pipelined an extra cycle. This differs from the
1054 icache. The writeback logic needs to take that into
1055 account by using 1-cycle delayed signals for load hits.
1056 """
1057 comb = m.d.comb
1058 wb_in = self.wb_in
1059
1060 for i in range(NUM_WAYS):
1061 do_read = Signal()
1062 rd_addr = Signal(ROW_BITS)
1063 do_write = Signal()
1064 wr_addr = Signal(ROW_BITS)
1065 wr_data = Signal(WB_DATA_BITS)
1066 wr_sel = Signal(ROW_SIZE)
1067 wr_sel_m = Signal(ROW_SIZE)
1068 _d_out = Signal(WB_DATA_BITS)
1069
1070 way = CacheRam(ROW_BITS, WB_DATA_BITS, True)
1071 setattr(m.submodules, "cacheram_%d" % i, way)
1072
1073 comb += way.rd_en.eq(do_read)
1074 comb += way.rd_addr.eq(rd_addr)
1075 comb += _d_out.eq(way.rd_data_o)
1076 comb += way.wr_sel.eq(wr_sel_m)
1077 comb += way.wr_addr.eq(wr_addr)
1078 comb += way.wr_data.eq(wr_data)
1079
1080 # Cache hit reads
1081 comb += do_read.eq(1)
1082 comb += rd_addr.eq(early_req_row)
1083 comb += cache_out[i].eq(_d_out)
1084
1085 # Write mux:
1086 #
1087 # Defaults to wishbone read responses (cache refill)
1088 #
1089 # For timing, the mux on wr_data/sel/addr is not
1090 # dependent on anything other than the current state.
1091
1092 with m.If(r1.write_bram):
1093 # Write store data to BRAM. This happens one
1094 # cycle after the store is in r0.
1095 comb += wr_data.eq(r1.req.data)
1096 comb += wr_sel.eq(r1.req.byte_sel)
1097 comb += wr_addr.eq(get_row(r1.req.real_addr))
1098
1099 with m.If(i == r1.req.hit_way):
1100 comb += do_write.eq(1)
1101 with m.Else():
1102 # Otherwise, we might be doing a reload or a DCBZ
1103 with m.If(r1.dcbz):
1104 comb += wr_data.eq(0)
1105 with m.Else():
1106 comb += wr_data.eq(wb_in.dat)
1107 comb += wr_addr.eq(r1.store_row)
1108 comb += wr_sel.eq(~0) # all 1s
1109
1110 with m.If((r1.state == State.RELOAD_WAIT_ACK)
1111 & wb_in.ack & (replace_way == i)):
1112 comb += do_write.eq(1)
1113
1114 # Mask write selects with do_write since BRAM
1115 # doesn't have a global write-enable
1116 with m.If(do_write):
1117 comb += wr_sel_m.eq(wr_sel)
1118
1119 # Cache hit synchronous machine for the easy case.
1120 # This handles load hits.
1121 # It also handles error cases (TLB miss, cache paradox)
1122 def dcache_fast_hit(self, m, req_op, r0_valid, r0, r1,
1123 req_hit_way, req_index, access_ok,
1124 tlb_hit, tlb_hit_way, tlb_req_index):
1125
1126 comb = m.d.comb
1127 sync = m.d.sync
1128
1129 with m.If(req_op != Op.OP_NONE):
1130 #Display(f"op:{req_op} addr:{r0.req.addr} nc: {r0.req.nc}" \
1131 # f"idx:{req_index} tag:{req_tag} way: {req_hit_way}"
1132 # )
1133 pass
1134
1135 with m.If(r0_valid):
1136 sync += r1.mmu_req.eq(r0.mmu_req)
1137
1138 # Fast path for load/store hits.
1139 # Set signals for the writeback controls.
1140 sync += r1.hit_way.eq(req_hit_way)
1141 sync += r1.hit_index.eq(req_index)
1142
1143 with m.If(req_op == Op.OP_LOAD_HIT):
1144 sync += r1.hit_load_valid.eq(1)
1145 with m.Else():
1146 sync += r1.hit_load_valid.eq(0)
1147
1148 with m.If((req_op == Op.OP_LOAD_HIT) | (req_op == Op.OP_STORE_HIT)):
1149 sync += r1.cache_hit.eq(1)
1150 with m.Else():
1151 sync += r1.cache_hit.eq(0)
1152
1153 with m.If(req_op == Op.OP_BAD):
1154 # Display(f"Signalling ld/st error valid_ra={valid_ra}"
1155 # f"rc_ok={rc_ok} perm_ok={perm_ok}"
1156 sync += r1.ls_error.eq(~r0.mmu_req)
1157 sync += r1.mmu_error.eq(r0.mmu_req)
1158 sync += r1.cache_paradox.eq(access_ok)
1159
1160 with m.Else():
1161 sync += r1.ls_error.eq(0)
1162 sync += r1.mmu_error.eq(0)
1163 sync += r1.cache_paradox.eq(0)
1164
1165 with m.If(req_op == Op.OP_STCX_FAIL):
1166 r1.stcx_fail.eq(1)
1167 with m.Else():
1168 sync += r1.stcx_fail.eq(0)
1169
1170 # Record TLB hit information for updating TLB PLRU
1171 sync += r1.tlb_hit.eq(tlb_hit)
1172 sync += r1.tlb_hit_way.eq(tlb_hit_way)
1173 sync += r1.tlb_hit_index.eq(tlb_req_index)
1174
1175 # Memory accesses are handled by this state machine:
1176 #
1177 # * Cache load miss/reload (in conjunction with "rams")
1178 # * Load hits for non-cachable forms
1179 # * Stores (the collision case is handled in "rams")
1180 #
1181 # All wishbone requests generation is done here.
1182 # This machine operates at stage 1.
1183 def dcache_slow(self, m, r1, use_forward1_next, use_forward2_next,
1184 cache_valid_bits, r0, replace_way,
1185 req_hit_way, req_same_tag,
1186 r0_valid, req_op, cache_tag, req_go, ra):
1187
1188 comb = m.d.comb
1189 sync = m.d.sync
1190 wb_in = self.wb_in
1191
1192 req = MemAccessRequest("mreq_ds")
1193 acks = Signal(3)
1194 adjust_acks = Signal(3)
1195 stbs_done = Signal()
1196
1197 sync += r1.use_forward1.eq(use_forward1_next)
1198 sync += r1.forward_sel.eq(0)
1199
1200 with m.If(use_forward1_next):
1201 sync += r1.forward_sel.eq(r1.req.byte_sel)
1202 with m.Elif(use_forward2_next):
1203 sync += r1.forward_sel.eq(r1.forward_sel1)
1204
1205 sync += r1.forward_data2.eq(r1.forward_data1)
1206 with m.If(r1.write_bram):
1207 sync += r1.forward_data1.eq(r1.req.data)
1208 sync += r1.forward_sel1.eq(r1.req.byte_sel)
1209 sync += r1.forward_way1.eq(r1.req.hit_way)
1210 sync += r1.forward_row1.eq(get_row(r1.req.real_addr))
1211 sync += r1.forward_valid1.eq(1)
1212 with m.Else():
1213 with m.If(r1.dcbz):
1214 sync += r1.forward_data1.eq(0)
1215 with m.Else():
1216 sync += r1.forward_data1.eq(wb_in.dat)
1217 sync += r1.forward_sel1.eq(~0) # all 1s
1218 sync += r1.forward_way1.eq(replace_way)
1219 sync += r1.forward_row1.eq(r1.store_row)
1220 sync += r1.forward_valid1.eq(0)
1221
1222 # One cycle pulses reset
1223 sync += r1.slow_valid.eq(0)
1224 sync += r1.write_bram.eq(0)
1225 sync += r1.inc_acks.eq(0)
1226 sync += r1.dec_acks.eq(0)
1227
1228 sync += r1.ls_valid.eq(0)
1229 # complete tlbies and TLB loads in the third cycle
1230 sync += r1.mmu_done.eq(r0_valid & (r0.tlbie | r0.tlbld))
1231
1232 with m.If((req_op == Op.OP_LOAD_HIT)
1233 | (req_op == Op.OP_STCX_FAIL)):
1234 with m.If(~r0.mmu_req):
1235 sync += r1.ls_valid.eq(1)
1236 with m.Else():
1237 sync += r1.mmu_done.eq(1)
1238
1239 with m.If(r1.write_tag):
1240 # Store new tag in selected way
1241 for i in range(NUM_WAYS):
1242 with m.If(i == replace_way):
1243 ct = Signal(TAG_RAM_WIDTH)
1244 comb += ct.eq(cache_tag[r1.store_index])
1245 comb += ct.word_select(i, TAG_WIDTH).eq(r1.reload_tag)
1246 sync += cache_tag[r1.store_index].eq(ct)
1247 sync += r1.store_way.eq(replace_way)
1248 sync += r1.write_tag.eq(0)
1249
1250 # Take request from r1.req if there is one there,
1251 # else from req_op, ra, etc.
1252 with m.If(r1.full):
1253 comb += req.eq(r1.req)
1254 with m.Else():
1255 comb += req.op.eq(req_op)
1256 comb += req.valid.eq(req_go)
1257 comb += req.mmu_req.eq(r0.mmu_req)
1258 comb += req.dcbz.eq(r0.req.dcbz)
1259 comb += req.real_addr.eq(ra)
1260
1261 with m.If(~r0.req.dcbz):
1262 comb += req.data.eq(r0.req.data)
1263 with m.Else():
1264 comb += req.data.eq(0)
1265
1266 # Select all bytes for dcbz
1267 # and for cacheable loads
1268 with m.If(r0.req.dcbz | (r0.req.load & ~r0.req.nc)):
1269 comb += req.byte_sel.eq(~0) # all 1s
1270 with m.Else():
1271 comb += req.byte_sel.eq(r0.req.byte_sel)
1272 comb += req.hit_way.eq(req_hit_way)
1273 comb += req.same_tag.eq(req_same_tag)
1274
1275 # Store the incoming request from r0,
1276 # if it is a slow request
1277 # Note that r1.full = 1 implies req_op = OP_NONE
1278 with m.If((req_op == Op.OP_LOAD_MISS)
1279 | (req_op == Op.OP_LOAD_NC)
1280 | (req_op == Op.OP_STORE_MISS)
1281 | (req_op == Op.OP_STORE_HIT)):
1282 sync += r1.req.eq(req)
1283 sync += r1.full.eq(1)
1284
1285 # Main state machine
1286 with m.Switch(r1.state):
1287
1288 with m.Case(State.IDLE):
1289 # XXX check 'left downto. probably means len(r1.wb.adr)
1290 # r1.wb.adr <= req.real_addr(
1291 # r1.wb.adr'left downto 0
1292 # );
1293 sync += r1.wb.adr.eq(req.real_addr)
1294 sync += r1.wb.sel.eq(req.byte_sel)
1295 sync += r1.wb.dat.eq(req.data)
1296 sync += r1.dcbz.eq(req.dcbz)
1297
1298 # Keep track of our index and way
1299 # for subsequent stores.
1300 sync += r1.store_index.eq(get_index(req.real_addr))
1301 sync += r1.store_row.eq(get_row(req.real_addr))
1302 sync += r1.end_row_ix.eq(
1303 get_row_of_line(get_row(req.real_addr))
1304 )
1305 sync += r1.reload_tag.eq(get_tag(req.real_addr))
1306 sync += r1.req.same_tag.eq(1)
1307
1308 with m.If(req.op == Op.OP_STORE_HIT):
1309 sync += r1.store_way.eq(req.hit_way)
1310
1311 # Reset per-row valid bits,
1312 # ready for handling OP_LOAD_MISS
1313 for i in range(ROW_PER_LINE):
1314 sync += r1.rows_valid[i].eq(0)
1315
1316 sync += Display("cache op %d", req.op)
1317
1318 with m.Switch(req.op):
1319 with m.Case(Op.OP_LOAD_HIT):
1320 # stay in IDLE state
1321 pass
1322
1323 with m.Case(Op.OP_LOAD_MISS):
1324 #Display(f"cache miss real addr:" \
1325 # f"{req_real_addr}" \
1326 # f" idx:{get_index(req_real_addr)}" \
1327 # f" tag:{get_tag(req.real_addr)}")
1328 pass
1329
1330 # Start the wishbone cycle
1331 sync += r1.wb.we.eq(0)
1332 sync += r1.wb.cyc.eq(1)
1333 sync += r1.wb.stb.eq(1)
1334
1335 # Track that we had one request sent
1336 sync += r1.state.eq(State.RELOAD_WAIT_ACK)
1337 sync += r1.write_tag.eq(1)
1338
1339 with m.Case(Op.OP_LOAD_NC):
1340 sync += r1.wb.cyc.eq(1)
1341 sync += r1.wb.stb.eq(1)
1342 sync += r1.wb.we.eq(0)
1343 sync += r1.state.eq(State.NC_LOAD_WAIT_ACK)
1344
1345 with m.Case(Op.OP_STORE_HIT, Op.OP_STORE_MISS):
1346 with m.If(~req.dcbz):
1347 sync += r1.state.eq(State.STORE_WAIT_ACK)
1348 sync += r1.acks_pending.eq(1)
1349 sync += r1.full.eq(0)
1350 sync += r1.slow_valid.eq(1)
1351
1352 with m.If(~req.mmu_req):
1353 sync += r1.ls_valid.eq(1)
1354 with m.Else():
1355 sync += r1.mmu_done.eq(1)
1356
1357 with m.If(req.op == Op.OP_STORE_HIT):
1358 sync += r1.write_bram.eq(1)
1359 with m.Else():
1360 sync += r1.state.eq(State.RELOAD_WAIT_ACK)
1361
1362 with m.If(req.op == Op.OP_STORE_MISS):
1363 sync += r1.write_tag.eq(1)
1364
1365 sync += r1.wb.we.eq(1)
1366 sync += r1.wb.cyc.eq(1)
1367 sync += r1.wb.stb.eq(1)
1368
1369 # OP_NONE and OP_BAD do nothing
1370 # OP_BAD & OP_STCX_FAIL were
1371 # handled above already
1372 with m.Case(Op.OP_NONE):
1373 pass
1374 with m.Case(Op.OP_BAD):
1375 pass
1376 with m.Case(Op.OP_STCX_FAIL):
1377 pass
1378
1379 with m.Case(State.RELOAD_WAIT_ACK):
1380 # Requests are all sent if stb is 0
1381 comb += stbs_done.eq(~r1.wb.stb)
1382
1383 with m.If(~wb_in.stall & ~stbs_done):
1384 # That was the last word?
1385 # We are done sending.
1386 # Clear stb and set stbs_done
1387 # so we can handle an eventual
1388 # last ack on the same cycle.
1389 with m.If(is_last_row_addr(
1390 r1.wb.adr, r1.end_row_ix)):
1391 sync += r1.wb.stb.eq(0)
1392 comb += stbs_done.eq(0)
1393
1394 # Calculate the next row address in the current cache line
1395 rarange = r1.wb.adr[ROW_OFF_BITS : LINE_OFF_BITS]
1396 sync += rarange.eq(rarange + 1)
1397
1398 # Incoming acks processing
1399 sync += r1.forward_valid1.eq(wb_in.ack)
1400 with m.If(wb_in.ack):
1401 # XXX needs an Array bit-accessor here
1402 sync += r1.rows_valid[r1.store_row % ROW_PER_LINE].eq(1)
1403
1404 # If this is the data we were looking for,
1405 # we can complete the request next cycle.
1406 # Compare the whole address in case the
1407 # request in r1.req is not the one that
1408 # started this refill.
1409 with m.If(r1.full & r1.req.same_tag &
1410 ((r1.dcbz & r1.req.dcbz) |
1411 (~r1.dcbz & (r1.req.op == Op.OP_LOAD_MISS))) &
1412 (r1.store_row == get_row(r1.req.real_addr))):
1413 sync += r1.full.eq(0)
1414 sync += r1.slow_valid.eq(1)
1415 with m.If(~r1.mmu_req):
1416 sync += r1.ls_valid.eq(1)
1417 with m.Else():
1418 sync += r1.mmu_done.eq(1)
1419 sync += r1.forward_sel.eq(~0) # all 1s
1420 sync += r1.use_forward1.eq(1)
1421
1422 # Check for completion
1423 with m.If(stbs_done & is_last_row(r1.store_row,
1424 r1.end_row_ix)):
1425 # Complete wishbone cycle
1426 sync += r1.wb.cyc.eq(0)
1427
1428 # Cache line is now valid
1429 cv = Signal(INDEX_BITS)
1430 sync += cv.eq(cache_valid_bits[r1.store_index])
1431 sync += cv.bit_select(r1.store_way, 1).eq(1)
1432 sync += r1.state.eq(State.IDLE)
1433
1434 # Increment store row counter
1435 sync += r1.store_row.eq(next_row(r1.store_row))
1436
1437 with m.Case(State.STORE_WAIT_ACK):
1438 comb += stbs_done.eq(~r1.wb.stb)
1439 comb += acks.eq(r1.acks_pending)
1440
1441 with m.If(r1.inc_acks != r1.dec_acks):
1442 with m.If(r1.inc_acks):
1443 comb += adjust_acks.eq(acks + 1)
1444 with m.Else():
1445 comb += adjust_acks.eq(acks - 1)
1446 with m.Else():
1447 comb += adjust_acks.eq(acks)
1448
1449 sync += r1.acks_pending.eq(adjust_acks)
1450
1451 # Clear stb when slave accepted request
1452 with m.If(~wb_in.stall):
1453 # See if there is another store waiting
1454 # to be done which is in the same real page.
1455 with m.If(req.valid):
1456 ra = req.real_addr[0:SET_SIZE_BITS]
1457 sync += r1.wb.adr[0:SET_SIZE_BITS].eq(ra)
1458 sync += r1.wb.dat.eq(req.data)
1459 sync += r1.wb.sel.eq(req.byte_sel)
1460
1461 with m.Elif((adjust_acks < 7) & req.same_tag &
1462 ((req.op == Op.OP_STORE_MISS)
1463 | (req.op == Op.OP_STORE_HIT))):
1464 sync += r1.wb.stb.eq(1)
1465 comb += stbs_done.eq(0)
1466
1467 with m.If(req.op == Op.OP_STORE_HIT):
1468 sync += r1.write_bram.eq(1)
1469 sync += r1.full.eq(0)
1470 sync += r1.slow_valid.eq(1)
1471
1472 # Store requests never come from the MMU
1473 sync += r1.ls_valid.eq(1)
1474 comb += stbs_done.eq(0)
1475 sync += r1.inc_acks.eq(1)
1476 with m.Else():
1477 sync += r1.wb.stb.eq(0)
1478 comb += stbs_done.eq(1)
1479
1480 # Got ack ? See if complete.
1481 with m.If(wb_in.ack):
1482 with m.If(stbs_done & (adjust_acks == 1)):
1483 sync += r1.state.eq(State.IDLE)
1484 sync += r1.wb.cyc.eq(0)
1485 sync += r1.wb.stb.eq(0)
1486 sync += r1.dec_acks.eq(1)
1487
1488 with m.Case(State.NC_LOAD_WAIT_ACK):
1489 # Clear stb when slave accepted request
1490 with m.If(~wb_in.stall):
1491 sync += r1.wb.stb.eq(0)
1492
1493 # Got ack ? complete.
1494 with m.If(wb_in.ack):
1495 sync += r1.state.eq(State.IDLE)
1496 sync += r1.full.eq(0)
1497 sync += r1.slow_valid.eq(1)
1498
1499 with m.If(~r1.mmu_req):
1500 sync += r1.ls_valid.eq(1)
1501 with m.Else():
1502 sync += r1.mmu_done.eq(1)
1503
1504 sync += r1.forward_sel.eq(~0) # all 1s
1505 sync += r1.use_forward1.eq(1)
1506 sync += r1.wb.cyc.eq(0)
1507 sync += r1.wb.stb.eq(0)
1508
1509 def dcache_log(self, m, r1, valid_ra, tlb_hit_way, stall_out):
1510
1511 sync = m.d.sync
1512 d_out, wb_in, log_out = self.d_out, self.wb_in, self.log_out
1513
1514 sync += log_out.eq(Cat(r1.state[:3], valid_ra, tlb_hit_way[:3],
1515 stall_out, req_op[:3], d_out.valid, d_out.error,
1516 r1.wb.cyc, r1.wb.stb, wb_in.ack, wb_in.stall,
1517 r1.wb.adr[3:6]))
1518
1519 def elaborate(self, platform):
1520
1521 m = Module()
1522 comb = m.d.comb
1523
1524 # Storage. Hopefully "cache_rows" is a BRAM, the rest is LUTs
1525 cache_tags = CacheTagArray()
1526 cache_tag_set = Signal(TAG_RAM_WIDTH)
1527 cache_valid_bits = CacheValidBitsArray()
1528
1529 # TODO attribute ram_style : string;
1530 # TODO attribute ram_style of cache_tags : signal is "distributed";
1531
1532 """note: these are passed to nmigen.hdl.Memory as "attributes".
1533 don't know how, just that they are.
1534 """
1535 dtlb_valid_bits = TLBValidBitsArray()
1536 dtlb_tags = TLBTagsArray()
1537 dtlb_ptes = TLBPtesArray()
1538 # TODO attribute ram_style of
1539 # dtlb_tags : signal is "distributed";
1540 # TODO attribute ram_style of
1541 # dtlb_ptes : signal is "distributed";
1542
1543 r0 = RegStage0("r0")
1544 r0_full = Signal()
1545
1546 r1 = RegStage1("r1")
1547
1548 reservation = Reservation()
1549
1550 # Async signals on incoming request
1551 req_index = Signal(INDEX_BITS)
1552 req_row = Signal(ROW_BITS)
1553 req_hit_way = Signal(WAY_BITS)
1554 req_tag = Signal(TAG_BITS)
1555 req_op = Signal(Op)
1556 req_data = Signal(64)
1557 req_same_tag = Signal()
1558 req_go = Signal()
1559
1560 early_req_row = Signal(ROW_BITS)
1561
1562 cancel_store = Signal()
1563 set_rsrv = Signal()
1564 clear_rsrv = Signal()
1565
1566 r0_valid = Signal()
1567 r0_stall = Signal()
1568
1569 use_forward1_next = Signal()
1570 use_forward2_next = Signal()
1571
1572 cache_out = CacheRamOut()
1573
1574 plru_victim = PLRUOut()
1575 replace_way = Signal(WAY_BITS)
1576
1577 # Wishbone read/write/cache write formatting signals
1578 bus_sel = Signal(8)
1579
1580 # TLB signals
1581 tlb_tag_way = Signal(TLB_TAG_WAY_BITS)
1582 tlb_pte_way = Signal(TLB_PTE_WAY_BITS)
1583 tlb_valid_way = Signal(TLB_NUM_WAYS)
1584 tlb_req_index = Signal(TLB_SET_BITS)
1585 tlb_hit = Signal()
1586 tlb_hit_way = Signal(TLB_WAY_BITS)
1587 pte = Signal(TLB_PTE_BITS)
1588 ra = Signal(REAL_ADDR_BITS)
1589 valid_ra = Signal()
1590 perm_attr = PermAttr()
1591 rc_ok = Signal()
1592 perm_ok = Signal()
1593 access_ok = Signal()
1594
1595 tlb_plru_victim = TLBPLRUOut()
1596
1597 # we don't yet handle collisions between loadstore1 requests
1598 # and MMU requests
1599 comb += self.m_out.stall.eq(0)
1600
1601 # Hold off the request in r0 when r1 has an uncompleted request
1602 comb += r0_stall.eq(r0_full & r1.full)
1603 comb += r0_valid.eq(r0_full & ~r1.full)
1604 comb += self.stall_out.eq(r0_stall)
1605
1606 # Wire up wishbone request latch out of stage 1
1607 comb += self.wb_out.eq(r1.wb)
1608
1609 # call sub-functions putting everything together, using shared
1610 # signals established above
1611 self.stage_0(m, r0, r1, r0_full)
1612 self.tlb_read(m, r0_stall, tlb_valid_way,
1613 tlb_tag_way, tlb_pte_way, dtlb_valid_bits,
1614 dtlb_tags, dtlb_ptes)
1615 self.tlb_search(m, tlb_req_index, r0, r0_valid,
1616 tlb_valid_way, tlb_tag_way, tlb_hit_way,
1617 tlb_pte_way, pte, tlb_hit, valid_ra, perm_attr, ra)
1618 self.tlb_update(m, r0_valid, r0, dtlb_valid_bits, tlb_req_index,
1619 tlb_hit_way, tlb_hit, tlb_plru_victim, tlb_tag_way,
1620 dtlb_tags, tlb_pte_way, dtlb_ptes)
1621 self.maybe_plrus(m, r1, plru_victim)
1622 self.maybe_tlb_plrus(m, r1, tlb_plru_victim)
1623 self.cache_tag_read(m, r0_stall, req_index, cache_tag_set, cache_tags)
1624 self.dcache_request(m, r0, ra, req_index, req_row, req_tag,
1625 r0_valid, r1, cache_valid_bits, replace_way,
1626 use_forward1_next, use_forward2_next,
1627 req_hit_way, plru_victim, rc_ok, perm_attr,
1628 valid_ra, perm_ok, access_ok, req_op, req_go,
1629 tlb_pte_way,
1630 tlb_hit, tlb_hit_way, tlb_valid_way, cache_tag_set,
1631 cancel_store, req_same_tag, r0_stall, early_req_row)
1632 self.reservation_comb(m, cancel_store, set_rsrv, clear_rsrv,
1633 r0_valid, r0, reservation)
1634 self.reservation_reg(m, r0_valid, access_ok, set_rsrv, clear_rsrv,
1635 reservation, r0)
1636 self.writeback_control(m, r1, cache_out)
1637 self.rams(m, r1, early_req_row, cache_out, replace_way)
1638 self.dcache_fast_hit(m, req_op, r0_valid, r0, r1,
1639 req_hit_way, req_index, access_ok,
1640 tlb_hit, tlb_hit_way, tlb_req_index)
1641 self.dcache_slow(m, r1, use_forward1_next, use_forward2_next,
1642 cache_valid_bits, r0, replace_way,
1643 req_hit_way, req_same_tag,
1644 r0_valid, req_op, cache_tags, req_go, ra)
1645 #self.dcache_log(m, r1, valid_ra, tlb_hit_way, stall_out)
1646
1647 return m
1648
1649
1650 def dcache_sim(dut):
1651 # clear stuff
1652 yield dut.d_in.valid.eq(0)
1653 yield dut.d_in.load.eq(0)
1654 yield dut.d_in.nc.eq(0)
1655 yield dut.d_in.addr.eq(0)
1656 yield dut.d_in.data.eq(0)
1657 yield dut.m_in.valid.eq(0)
1658 yield dut.m_in.addr.eq(0)
1659 yield dut.m_in.pte.eq(0)
1660 # wait 4 * clk_period
1661 yield
1662 yield
1663 yield
1664 yield
1665
1666 # Cacheable read of address 30
1667 yield dut.d_in.load.eq(1)
1668 yield dut.d_in.nc.eq(0)
1669 yield dut.d_in.addr.eq(0x0000000000000030)
1670 yield dut.d_in.valid.eq(1)
1671 yield
1672 yield dut.d_in.valid.eq(0)
1673 yield
1674 while not (yield dut.d_out.valid):
1675 yield
1676 data = yield dut.d_out.data
1677 addr = yield dut.d_in.addr
1678 assert data == 0x0000000D0000000C, \
1679 f"data @%x=%x expected 0000000D0000000C" % (addr, data)
1680
1681 # Cacheable read of address 4
1682 yield dut.d_in.load.eq(1)
1683 yield dut.d_in.nc.eq(0)
1684 yield dut.d_in.addr.eq(0x0000000000000004)
1685 yield dut.d_in.valid.eq(1)
1686 yield
1687 yield dut.d_in.valid.eq(0)
1688 yield
1689 while not (yield dut.d_out.valid):
1690 yield
1691 data = yield dut.d_out.data
1692 addr = yield dut.d_in.addr
1693 assert data == 0x0000000100000000, \
1694 f"data @%x=%x expected 0x0000000100000000" % (addr, data)
1695
1696 # Non-cacheable read of address 100
1697 yield dut.d_in.load.eq(1)
1698 yield dut.d_in.nc.eq(1)
1699 yield dut.d_in.addr.eq(Const(0x0000000000000100, 64))
1700 yield dut.d_in.valid.eq(1)
1701 yield
1702 yield dut.d_in.valid.eq(0)
1703 yield
1704 while not (yield dut.d_out.valid):
1705 yield
1706 data = yield dut.d_out.data
1707 addr = yield dut.d_in.addr
1708 assert data == 0x0000004100000040, \
1709 f"data @%x=%x expected 0000004100000040" % (addr, data)
1710
1711 yield
1712 yield
1713 yield
1714 yield
1715
1716
1717 def test_dcache():
1718 dut = DCache()
1719 vl = rtlil.convert(dut, ports=[])
1720 with open("test_dcache.il", "w") as f:
1721 f.write(vl)
1722
1723 memory = Memory(width=64, depth=16*8, init=range(128))
1724 sram = SRAM(memory=memory, granularity=8)
1725
1726 m = Module()
1727 m.submodules.dcache = dut
1728 m.submodules.sram = sram
1729
1730 m.d.comb += sram.bus.cyc.eq(dut.wb_out.cyc)
1731 m.d.comb += sram.bus.stb.eq(dut.wb_out.stb)
1732 m.d.comb += sram.bus.we.eq(dut.wb_out.we)
1733 m.d.comb += sram.bus.sel.eq(dut.wb_out.sel)
1734 m.d.comb += sram.bus.adr.eq(dut.wb_out.adr)
1735 m.d.comb += sram.bus.dat_w.eq(dut.wb_out.dat)
1736
1737 m.d.comb += dut.wb_in.ack.eq(sram.bus.ack)
1738 m.d.comb += dut.wb_in.dat.eq(sram.bus.dat_r)
1739
1740 # nmigen Simulation
1741 sim = Simulator(m)
1742 sim.add_clock(1e-6)
1743
1744 sim.add_sync_process(wrap(dcache_sim(dut)))
1745 with sim.write_vcd('test_dcache.vcd'):
1746 sim.run()
1747
1748 if __name__ == '__main__':
1749 test_dcache()
1750