7eb98f57ffb64a0df2b37a1bd184487497479006
1 """Computation Unit (aka "ALU Manager").
3 Manages a Pipeline or FSM, ensuring that the start and end time are 100%
4 monitored. At no time may the ALU proceed without this module notifying
5 the Dependency Matrices. At no time is a result production "abandoned".
6 This module blocks (indicates busy) starting from when it first receives
7 an opcode until it receives notification that
8 its result(s) have been successfully stored in the regfile(s)
10 Documented at http://libre-soc.org/3d_gpu/architecture/compunit
13 from soc
.experiment
.alu_fsm
import Shifter
, CompFSMOpSubset
14 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
15 from soc
.fu
.cr
.cr_input_record
import CompCROpSubset
16 from soc
.experiment
.alu_hier
import ALU
, DummyALU
17 from soc
.experiment
.compalu_multi
import MultiCompUnit
18 from soc
.decoder
.power_enums
import MicrOp
19 from nmutil
.gtkw
import write_gtkw
20 from nmigen
import Module
, Signal
21 from nmigen
.cli
import rtlil
23 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
24 # Also, check out the cxxsim nmigen branch, and latest yosys from git
25 from nmutil
.sim_tmp_alternative
import (Simulator
, Settle
, is_engine_pysim
,
35 class OperandProducer
:
37 Produces an operand when requested by the Computation Unit
38 (`dut` parameter), using the `rel_o` / `go_i` handshake.
40 Attaches itself to the `dut` operand indexed by `op_index`.
42 Has a programmable delay between the assertion of `rel_o` and the
45 Data is presented only during the cycle in which `go_i` is active.
47 It adds itself as a passive process to the simulation (`sim` parameter).
48 Since it is passive, it will not hang the simulation, and does not need a
49 flag to terminate itself.
51 def __init__(self
, sim
, dut
, op_index
):
52 self
.count
= Signal(8, name
=f
"src{op_index + 1}_count")
53 """ transaction counter"""
54 # data and handshake signals from the DUT
55 self
.port
= dut
.src_i
[op_index
]
56 self
.go_i
= dut
.rd
.go_i
[op_index
]
57 self
.rel_o
= dut
.rd
.rel_o
[op_index
]
58 # transaction parameters, passed via signals
59 self
.delay
= Signal(8)
60 self
.data
= Signal
.like(self
.port
)
61 # add ourselves to the simulation process list
62 sim
.add_sync_process(self
._process
)
67 # Settle() is needed to give a quick response to
70 # wait for rel_o to become active
71 while not (yield self
.rel_o
):
74 # read the transaction parameters
75 delay
= (yield self
.delay
)
76 data
= (yield self
.data
)
77 # wait for `delay` cycles
78 for _
in range(delay
):
80 # activate go_i and present data, for one cycle
82 yield self
.port
.eq(data
)
83 yield self
.count
.eq(self
.count
+ 1)
88 def send(self
, data
, delay
):
90 Schedules the module to send some `data`, counting `delay` cycles after
91 `rel_i` becomes active.
93 To be called from the main test-bench process,
94 it returns in the same cycle.
96 Communication with the worker process is done by means of
97 combinatorial simulation-only signals.
100 yield self
.data
.eq(data
)
101 yield self
.delay
.eq(delay
)
104 class ResultConsumer
:
106 Consumes a result when requested by the Computation Unit
107 (`dut` parameter), using the `rel_o` / `go_i` handshake.
109 Attaches itself to the `dut` result indexed by `op_index`.
111 Has a programmable delay between the assertion of `rel_o` and the
114 Data is retrieved only during the cycle in which `go_i` is active.
116 It adds itself as a passive process to the simulation (`sim` parameter).
117 Since it is passive, it will not hang the simulation, and does not need a
118 flag to terminate itself.
120 def __init__(self
, sim
, dut
, op_index
):
121 self
.count
= Signal(8, name
=f
"dest{op_index + 1}_count")
122 """ transaction counter"""
123 # data and handshake signals from the DUT
124 self
.port
= dut
.dest
[op_index
]
125 self
.go_i
= dut
.wr
.go_i
[op_index
]
126 self
.rel_o
= dut
.wr
.rel_o
[op_index
]
127 # transaction parameters, passed via signals
128 self
.delay
= Signal(8)
129 self
.expected
= Signal
.like(self
.port
)
130 # add ourselves to the simulation process list
131 sim
.add_sync_process(self
._process
)
136 # Settle() is needed to give a quick response to
137 # the zero delay case
139 # wait for rel_o to become active
140 while not (yield self
.rel_o
):
143 # read the transaction parameters
144 delay
= (yield self
.delay
)
145 expected
= (yield self
.expected
)
146 # wait for `delay` cycles
147 for _
in range(delay
):
149 # activate go_i for one cycle
150 yield self
.go_i
.eq(1)
151 yield self
.count
.eq(self
.count
+ 1)
153 # check received data against the expected value
154 result
= (yield self
.port
)
155 assert result
== expected
,\
156 f
"expected {expected}, received {result}"
157 yield self
.go_i
.eq(0)
158 yield self
.port
.eq(0)
160 def receive(self
, expected
, delay
):
162 Schedules the module to receive some result,
163 counting `delay` cycles after `rel_i` becomes active.
164 As 'go_i' goes active, check the result with `expected`.
166 To be called from the main test-bench process,
167 it returns in the same cycle.
169 Communication with the worker process is done by means of
170 combinatorial simulation-only signals.
172 yield self
.expected
.eq(expected
)
173 yield self
.delay
.eq(delay
)
176 def op_sim(dut
, a
, b
, op
, inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0):
177 yield dut
.issue_i
.eq(0)
179 yield dut
.src_i
[0].eq(a
)
180 yield dut
.src_i
[1].eq(b
)
181 yield dut
.oper_i
.insn_type
.eq(op
)
182 yield dut
.oper_i
.invert_in
.eq(inv_a
)
183 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
184 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
185 yield dut
.oper_i
.zero_a
.eq(zero_a
)
186 yield dut
.issue_i
.eq(1)
188 yield dut
.issue_i
.eq(0)
190 if not imm_ok
or not zero_a
:
191 yield dut
.rd
.go_i
.eq(0b11)
194 rd_rel_o
= yield dut
.rd
.rel_o
195 print("rd_rel", rd_rel_o
)
198 yield dut
.rd
.go_i
.eq(0)
202 if len(dut
.src_i
) == 3:
203 yield dut
.rd
.go_i
.eq(0b100)
206 rd_rel_o
= yield dut
.rd
.rel_o
207 print("rd_rel", rd_rel_o
)
210 yield dut
.rd
.go_i
.eq(0)
214 req_rel_o
= yield dut
.wr
.rel_o
215 result
= yield dut
.data_o
216 print("req_rel", req_rel_o
, result
)
218 req_rel_o
= yield dut
.wr
.rel_o
219 result
= yield dut
.data_o
220 print("req_rel", req_rel_o
, result
)
224 yield dut
.wr
.go_i
[0].eq(1)
226 result
= yield dut
.data_o
228 print("result", result
)
229 yield dut
.wr
.go_i
[0].eq(0)
234 def scoreboard_sim_fsm(dut
, producers
, consumers
):
236 # stores the operation count
239 def op_sim_fsm(a
, b
, direction
, expected
, delays
):
240 print("op_sim_fsm", a
, b
, direction
, expected
)
241 yield dut
.issue_i
.eq(0)
243 # forward data and delays to the producers and consumers
244 yield from producers
[0].send(a
, delays
[0])
245 yield from producers
[1].send(b
, delays
[1])
246 yield from consumers
[0].receive(expected
, delays
[2])
247 # submit operation, and assert issue_i for one cycle
248 yield dut
.oper_i
.sdir
.eq(direction
)
249 yield dut
.issue_i
.eq(1)
251 yield dut
.issue_i
.eq(0)
252 # wait for busy to be negated
254 while (yield dut
.busy_o
):
257 # update the operation count
259 op_count
= (op_count
+ 1) & 255
260 # check that producers and consumers have the same count
261 # this assures that no data was left unused or was lost
262 assert (yield producers
[0].count
) == op_count
263 assert (yield producers
[1].count
) == op_count
264 assert (yield consumers
[0].count
) == op_count
267 # operand 1 arrives immediately
268 # operand 2 arrives after operand 1
269 # write data is accepted immediately
270 yield from op_sim_fsm(13, 2, 1, 3, [0, 2, 0])
272 # operand 2 arrives immediately
273 # operand 1 arrives after operand 2
274 # write data is accepted after some delay
275 yield from op_sim_fsm(3, 4, 0, 48, [2, 0, 2])
277 # operands 1 and 2 arrive at the same time
278 # write data is accepted after some delay
279 yield from op_sim_fsm(21, 0, 0, 21, [1, 1, 1])
282 def scoreboard_sim_dummy(op
):
283 yield from op
.issue([5, 2, 0], MicrOp
.OP_NOP
, [5],
284 src_delays
=[0, 2, 1], dest_delays
=[0])
285 yield from op
.issue([9, 2, 0], MicrOp
.OP_NOP
, [9],
286 src_delays
=[2, 1, 0], dest_delays
=[2])
287 # test all combinations of masked input ports
288 yield from op
.issue([5, 2, 0], MicrOp
.OP_NOP
, [0],
290 src_delays
=[0, 2, 1], dest_delays
=[0])
291 yield from op
.issue([9, 2, 0], MicrOp
.OP_NOP
, [9],
293 src_delays
=[2, 1, 0], dest_delays
=[2])
294 yield from op
.issue([5, 2, 0], MicrOp
.OP_NOP
, [5],
296 src_delays
=[2, 1, 0], dest_delays
=[2])
297 yield from op
.issue([9, 2, 0], MicrOp
.OP_NOP
, [9],
299 src_delays
=[2, 1, 0], dest_delays
=[2])
300 yield from op
.issue([9, 2, 0], MicrOp
.OP_NOP
, [0],
302 src_delays
=[2, 1, 0], dest_delays
=[2])
303 yield from op
.issue([9, 2, 0], MicrOp
.OP_NOP
, [0],
305 src_delays
=[2, 1, 0], dest_delays
=[2])
309 """ALU Operation issuer
311 Issues operations to the DUT"""
312 def __init__(self
, dut
, sim
):
314 self
.zero_a_count
= 0
315 self
.imm_ok_count
= 0
316 self
.rdmaskn_count
= [0] * len(dut
.src_i
)
318 # create one operand producer for each input port
319 self
.producers
= list()
320 for i
in range(len(dut
.src_i
)):
321 self
.producers
.append(OperandProducer(sim
, dut
, i
))
322 # create one result consumer for each output port
323 self
.consumers
= list()
324 for i
in range(len(dut
.dest
)):
325 self
.consumers
.append(ResultConsumer(sim
, dut
, i
))
326 def issue(self
, src_i
, op
, expected
, src_delays
, dest_delays
,
327 inv_a
=0, imm
=0, imm_ok
=0, zero_a
=0, rdmaskn
=None):
328 """Executes the issue operation"""
330 producers
= self
.producers
331 consumers
= self
.consumers
333 rdmaskn
= [0] * len(src_i
)
334 yield dut
.issue_i
.eq(0)
336 # forward data and delays to the producers and consumers
337 # first, send special cases (with zero_a and/or imm_ok)
339 yield from producers
[0].send(src_i
[0], src_delays
[0])
341 yield from producers
[1].send(src_i
[1], src_delays
[1])
342 # then, send the rest (if any)
343 for i
in range(2, len(producers
)):
344 yield from producers
[i
].send(src_i
[i
], src_delays
[i
])
345 for i
in range(len(consumers
)):
346 yield from consumers
[i
].receive(expected
[i
], dest_delays
[i
])
347 # submit operation, and assert issue_i for one cycle
348 yield dut
.oper_i
.insn_type
.eq(op
)
349 if hasattr(dut
.oper_i
, "invert_in"):
350 yield dut
.oper_i
.invert_in
.eq(inv_a
)
351 if hasattr(dut
.oper_i
, "imm_data"):
352 yield dut
.oper_i
.imm_data
.data
.eq(imm
)
353 yield dut
.oper_i
.imm_data
.ok
.eq(imm_ok
)
354 if hasattr(dut
.oper_i
, "zero_a"):
355 yield dut
.oper_i
.zero_a
.eq(zero_a
)
356 if hasattr(dut
, "rdmaskn"):
358 for i
in range(len(rdmaskn
)):
359 rdmaskn_bits |
= rdmaskn
[i
] << i
360 yield dut
.rdmaskn
.eq(rdmaskn_bits
)
361 yield dut
.issue_i
.eq(1)
363 yield dut
.issue_i
.eq(0)
364 # deactivate decoder inputs along with issue_i, so we can be sure they
365 # were latched at the correct cycle
366 # note: rdmaskn is not latched, and must be held as long as
368 # See: https://bugs.libre-soc.org/show_bug.cgi?id=336#c44
369 yield self
.dut
.oper_i
.insn_type
.eq(0)
370 if hasattr(dut
.oper_i
, "invert_in"):
371 yield self
.dut
.oper_i
.invert_in
.eq(0)
372 if hasattr(dut
.oper_i
, "imm_data"):
373 yield self
.dut
.oper_i
.imm_data
.data
.eq(0)
374 yield self
.dut
.oper_i
.imm_data
.ok
.eq(0)
375 if hasattr(dut
.oper_i
, "zero_a"):
376 yield self
.dut
.oper_i
.zero_a
.eq(0)
377 # wait for busy to be negated
379 while (yield dut
.busy_o
):
382 # now, deactivate rdmaskn
383 if hasattr(dut
, "rdmaskn"):
384 yield dut
.rdmaskn
.eq(0)
385 # update the operation count
386 self
.op_count
= (self
.op_count
+ 1) & 255
387 # On zero_a, imm_ok and rdmaskn executions, the producer counters will
388 # fall behind. But, by summing the following counts, the invariant is
390 if zero_a
and not rdmaskn
[0]:
391 self
.zero_a_count
= self
.zero_a_count
+ 1
392 if imm_ok
and not rdmaskn
[1]:
393 self
.imm_ok_count
= self
.imm_ok_count
+ 1
394 for i
in range(len(rdmaskn
)):
396 self
.rdmaskn_count
[i
] = self
.rdmaskn_count
[i
] + 1
397 # check that producers and consumers have the same count
398 # this assures that no data was left unused or was lost
399 # first, check special cases (zero_a and imm_ok)
401 (yield producers
[0].count
) \
402 + self
.zero_a_count \
403 + self
.rdmaskn_count
[0]
405 (yield producers
[1].count
) \
406 + self
.imm_ok_count \
407 + self
.rdmaskn_count
[1]
408 assert port_a_cnt
== self
.op_count
409 assert port_b_cnt
== self
.op_count
410 # then, check the rest (if any)
411 for i
in range(2, len(producers
)):
412 port_cnt
= (yield producers
[i
].count
) + self
.rdmaskn_count
[i
]
413 assert port_cnt
== self
.op_count
414 # check write counter
415 for i
in range(len(consumers
)):
416 assert (yield consumers
[i
].count
) == self
.op_count
419 def scoreboard_sim(op
):
420 # zero (no) input operands test
422 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, [8],
423 zero_a
=1, imm
=8, imm_ok
=1,
424 src_delays
=[0, 2], dest_delays
=[0])
426 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, [13],
427 inv_a
=0, imm
=8, imm_ok
=1,
428 src_delays
=[2, 0], dest_delays
=[2])
430 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, [7],
431 src_delays
=[1, 1], dest_delays
=[1])
433 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, [65532],
435 src_delays
=[1, 2], dest_delays
=[0])
437 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, [2],
439 src_delays
=[2, 0], dest_delays
=[1])
441 # test combinatorial zero-delay operation
442 # In the test ALU, any operation other than ADD, MUL or SHR
443 # is zero-delay, and do a subtraction.
445 yield from op
.issue([5, 2], MicrOp
.OP_NOP
, [3],
446 src_delays
=[0, 1], dest_delays
=[2])
447 # test all combinations of masked input ports
449 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, [5],
451 src_delays
=[2, 1], dest_delays
=[0])
453 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, [2],
455 src_delays
=[1, 2], dest_delays
=[1])
456 # 0 (masked) + 0 (masked) = 0
457 yield from op
.issue([5, 2], MicrOp
.OP_ADD
, [0],
459 src_delays
=[1, 2], dest_delays
=[1])
462 def test_compunit_fsm():
464 'in': {'color': 'orange'},
465 'out': {'color': 'yellow'},
469 ('operation port', {'color': 'red'}, [
470 'cu_issue_i', 'cu_busy_o',
471 {'comment': 'operation'},
472 'oper_i_None__sdir']),
473 ('operand 1 port', 'in', [
474 ('cu_rd__rel_o[1:0]', {'bit': 1}),
475 ('cu_rd__go_i[1:0]', {'bit': 1}),
477 ('operand 2 port', 'in', [
478 ('cu_rd__rel_o[1:0]', {'bit': 0}),
479 ('cu_rd__go_i[1:0]', {'bit': 0}),
481 ('result port', 'out', [
482 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[7:0]']),
483 ('alu', {'submodule': 'alu'}, [
484 ('prev port', 'in', [
485 'op__sdir', 'p_data_i[7:0]', 'p_shift_i[7:0]',
487 ['p_valid_i', 'p_ready_o'])]),
488 ('next port', 'out', [
491 ['n_valid_o', 'n_ready_i'])])]),
492 ('debug', {'module': 'top'},
493 ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
496 "test_compunit_fsm1.gtkw",
497 "test_compunit_fsm1.vcd",
503 dut
= MultiCompUnit(8, alu
, CompFSMOpSubset
)
504 m
.submodules
.cu
= dut
506 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
507 with
open("test_compunit_fsm1.il", "w") as f
:
513 # create one operand producer for each input port
514 prod_a
= OperandProducer(sim
, dut
, 0)
515 prod_b
= OperandProducer(sim
, dut
, 1)
516 # create an result consumer for the output port
517 cons
= ResultConsumer(sim
, dut
, 0)
518 sim
.add_sync_process(wrap(scoreboard_sim_fsm(dut
,
521 sim_writer
= sim
.write_vcd('test_compunit_fsm1.vcd',
522 traces
=[prod_a
.count
,
533 dut
= MultiCompUnit(16, alu
, CompALUOpSubset
)
534 m
.submodules
.cu
= dut
536 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
537 with
open("test_compunit1.il", "w") as f
:
543 # create an operation issuer
545 sim
.add_sync_process(wrap(scoreboard_sim(op
)))
546 sim_writer
= sim
.write_vcd('test_compunit1.vcd')
551 def test_compunit_regspec2_fsm():
553 inspec
= [('INT', 'data', '0:15'),
554 ('INT', 'shift', '0:15')]
555 outspec
= [('INT', 'data', '0:15')]
557 regspec
= (inspec
, outspec
)
561 dut
= MultiCompUnit(regspec
, alu
, CompFSMOpSubset
)
562 m
.submodules
.cu
= dut
567 # create one operand producer for each input port
568 prod_a
= OperandProducer(sim
, dut
, 0)
569 prod_b
= OperandProducer(sim
, dut
, 1)
570 # create an result consumer for the output port
571 cons
= ResultConsumer(sim
, dut
, 0)
572 sim
.add_sync_process(wrap(scoreboard_sim_fsm(dut
,
575 sim_writer
= sim
.write_vcd('test_compunit_regspec2_fsm.vcd',
576 traces
=[prod_a
.count
,
583 def test_compunit_regspec3():
586 'in': {'color': 'orange'},
587 'out': {'color': 'yellow'},
591 ('operation port', {'color': 'red'}, [
592 'cu_issue_i', 'cu_busy_o',
593 {'comment': 'operation'},
594 ('oper_i_None__insn_type'
595 + ('' if is_engine_pysim() else '[6:0]'),
596 {'display': 'insn_type'})]),
597 ('operand 1 port', 'in', [
598 ('cu_rd__rel_o[2:0]', {'bit': 2}),
599 ('cu_rd__go_i[2:0]', {'bit': 2}),
601 ('operand 2 port', 'in', [
602 ('cu_rd__rel_o[2:0]', {'bit': 1}),
603 ('cu_rd__go_i[2:0]', {'bit': 1}),
605 ('operand 3 port', 'in', [
606 ('cu_rd__rel_o[2:0]', {'bit': 0}),
607 ('cu_rd__go_i[2:0]', {'bit': 0}),
609 ('result port', 'out', [
610 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
611 ('alu', {'submodule': 'alu'}, [
612 ('prev port', 'in', [
613 'oper_i_None__insn_type', 'i1[15:0]',
614 'valid_i', 'ready_o']),
615 ('next port', 'out', [
616 'alu_o[15:0]', 'valid_o', 'ready_i'])])]
618 write_gtkw("test_compunit_regspec3.gtkw",
619 "test_compunit_regspec3.vcd",
624 inspec
= [('INT', 'a', '0:15'),
625 ('INT', 'b', '0:15'),
626 ('INT', 'c', '0:15')]
627 outspec
= [('INT', 'o', '0:15')]
629 regspec
= (inspec
, outspec
)
633 dut
= MultiCompUnit(regspec
, alu
, CompCROpSubset
)
634 m
.submodules
.cu
= dut
639 # create an operation issuer
641 sim
.add_sync_process(wrap(scoreboard_sim_dummy(op
)))
642 sim_writer
= sim
.write_vcd('test_compunit_regspec3.vcd')
647 def test_compunit_regspec1():
650 'in': {'color': 'orange'},
651 'out': {'color': 'yellow'},
655 ('operation port', {'color': 'red'}, [
656 'cu_issue_i', 'cu_busy_o',
657 {'comment': 'operation'},
658 ('oper_i_None__insn_type'
659 + ('' if is_engine_pysim() else '[6:0]'),
660 {'display': 'insn_type'}),
661 ('oper_i_None__invert_in', {'display': 'invert_in'}),
662 ('oper_i_None__imm_data__data[63:0]', {'display': 'data[63:0]'}),
663 ('oper_i_None__imm_data__ok', {'display': 'imm_ok'}),
664 ('oper_i_None__zero_a', {'display': 'zero_a'})]),
665 ('operand 1 port', 'in', [
666 ('cu_rd__rel_o[1:0]', {'bit': 1}),
667 ('cu_rd__go_i[1:0]', {'bit': 1}),
669 ('operand 2 port', 'in', [
670 ('cu_rd__rel_o[1:0]', {'bit': 0}),
671 ('cu_rd__go_i[1:0]', {'bit': 0}),
673 ('result port', 'out', [
674 'cu_wr__rel_o', 'cu_wr__go_i', 'dest1_o[15:0]']),
675 ('alu', {'submodule': 'alu'}, [
676 ('prev port', 'in', [
677 'op__insn_type', 'op__invert_in', 'a[15:0]', 'b[15:0]',
678 'valid_i', 'ready_o']),
679 ('next port', 'out', [
680 'alu_o[15:0]', 'valid_o', 'ready_i'])]),
681 ('debug', {'module': 'top'},
682 ['src1_count[7:0]', 'src2_count[7:0]', 'dest1_count[7:0]'])]
684 write_gtkw("test_compunit_regspec1.gtkw",
685 "test_compunit_regspec1.vcd",
690 inspec
= [('INT', 'a', '0:15'),
691 ('INT', 'b', '0:15')]
692 outspec
= [('INT', 'o', '0:15')]
694 regspec
= (inspec
, outspec
)
698 dut
= MultiCompUnit(regspec
, alu
, CompALUOpSubset
)
699 m
.submodules
.cu
= dut
701 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
702 with
open("test_compunit_regspec1.il", "w") as f
:
708 # create an operation issuer
710 sim
.add_sync_process(wrap(scoreboard_sim(op
)))
711 sim_writer
= sim
.write_vcd('test_compunit_regspec1.vcd',
712 traces
=[op
.producers
[0].count
,
713 op
.producers
[1].count
,
714 op
.consumers
[0].count
])
719 if __name__
== '__main__':
722 test_compunit_regspec1()
723 test_compunit_regspec2_fsm()
724 test_compunit_regspec3()