src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.compat.sim import run_simulation
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from soc.fu.regspec import RegSpecAPI
  12
  13 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  14 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  15 from openpower.decoder.power_decoder2 import Data
  16 from openpower.consts import MSR
  17
  18 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  19 from soc.experiment.l0_cache import PortInterface
  20 from soc.experiment.pimem import LDSTException
  21 from soc.experiment.compldst_multi import LDSTCompUnit
  22 from soc.config.test.test_loadstore import TestMemPspec
  23
  24 ########################################
  25
  26 def dcbz(dut, src1, src2, src3, imm, imm_ok=True, update=False,
  27           byterev=True):
  28     print("DCBZ", src1, src2, src3, imm, imm_ok, update)
  29     yield dut.oper_i.insn_type.eq(MicrOp.OP_DCBZ)
  30     yield dut.oper_i.data_len.eq(2)  # half-word
  31     yield dut.oper_i.byte_reverse.eq(byterev)
  32     yield dut.src1_i.eq(src1)
  33     yield dut.src2_i.eq(src2)
  34     yield dut.src3_i.eq(src3)
  35     yield dut.oper_i.imm_data.data.eq(imm)
  36     yield dut.oper_i.imm_data.ok.eq(imm_ok)
  37     #FIXME: -- yield dut.oper_i.update.eq(update)
  38     yield dut.issue_i.eq(1)
  39     yield
  40     yield dut.issue_i.eq(0)
  41
  42     if imm_ok:
  43         active_rel = 0b101
  44     else:
  45         active_rel = 0b111
  46      # wait for all active rel signals to come up
  47     # guess: bug is here
  48     #while True:
  49     #    rel = yield dut.rd.rel_o
  50     #    if rel == active_rel:
  51     #        break
  52     #    yield
  53     #yield dut.rd.go_i.eq(active_rel)
  54     #yield
  55     #yield dut.rd.go_i.eq(0)
  56
  57     #yield from wait_for(dut.adr_rel_o, False, test1st=True)
  58     # yield from wait_for(dut.adr_rel_o)
  59     # yield dut.ad.go.eq(1)
  60     # yield
  61     # yield dut.ad.go.eq(0)
  62
  63     #if update:
  64     #    yield from wait_for(dut.wr.rel_o[1])
  65     #    yield dut.wr.go.eq(0b10)
  66     #    yield
  67     #    addr = yield dut.addr_o
  68     #    print("addr", addr)
  69     #    yield dut.wr.go.eq(0)
  70     #else:
  71     #    addr = None
  72
  73     # commented out for debugging
  74     #yield from wait_for(dut.sto_rel_o)
  75     #yield dut.go_st_i.eq(1)
  76     #yield
  77     #yield dut.go_st_i.eq(0)
  78     #yield from wait_for(dut.busy_o, False)
  79     # wait_for(dut.stwd_mem_o)
  80     #yield
  81     #return addr
  82
  83
  84 def ldst_sim(dut):
  85     yield from dcbz(dut, 4, 0, 3, 2) # FIXME
  86     yield
  87
  88 ########################################
  89
  90
  91 class TestLDSTCompUnitMMU(LDSTCompUnit):
  92
  93     def __init__(self, rwid, pspec):
  94         from soc.experiment.l0_cache import TstL0CacheBuffer
  95         self.l0 = l0 = TstL0CacheBuffer(pspec)
  96         pi = l0.l0.dports[0]
  97         LDSTCompUnit.__init__(self, pi, rwid, 4)
  98
  99     def elaborate(self, platform):
 100         m = LDSTCompUnit.elaborate(self, platform)
 101         m.submodules.l0 = self.l0
 102         # link addr-go direct to rel
 103         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 104         return m
 105
 106
 107 def test_scoreboard_mmu():
 108
 109     units = {}
 110     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 111                          imem_ifacetype='bare_wb',
 112                          addr_wid=48,
 113                          mask_wid=8,
 114                          reg_wid=64,
 115                          units=units)
 116
 117     dut = TestLDSTCompUnitMMU(16,pspec)
 118     vl = rtlil.convert(dut, ports=dut.ports())
 119     with open("test_ldst_comp_mmu1.il", "w") as f:
 120         f.write(vl)
 121
 122     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
 123
 124 ########################################
 125 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
 126
 127     def __init__(self, pspec):
 128         from soc.experiment.l0_cache import TstL0CacheBuffer
 129         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 130         regspec = LDSTPipeSpec.regspec
 131         self.l0 = l0 = TstL0CacheBuffer(pspec)
 132         pi = l0.l0.dports[0]
 133         LDSTCompUnit.__init__(self, pi, regspec, 4)
 134
 135     def elaborate(self, platform):
 136         m = LDSTCompUnit.elaborate(self, platform)
 137         m.submodules.l0 = self.l0
 138         # link addr-go direct to rel
 139         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 140         return m
 141
 142
 143 def test_scoreboard_regspec_mmu():
 144
 145     units = {}
 146     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 147                          imem_ifacetype='bare_wb',
 148                          addr_wid=48,
 149                          mask_wid=8,
 150                          reg_wid=64,
 151                          units=units)
 152
 153     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 154     vl = rtlil.convert(dut, ports=dut.ports())
 155     with open("test_ldst_comp_mmu2.il", "w") as f:
 156         f.write(vl)
 157
 158     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_regspec.vcd')
 159
 160
 161 if __name__ == '__main__':
 162     test_scoreboard_regspec_mmu()
 163     #only one test for now -- test_scoreboard_mmu()