src/soc/experiment/test/test_compldst_multi_mmu.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from nmutil.util import wrap
  12 from soc.fu.regspec import RegSpecAPI
  13
  14 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  15 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  16 from openpower.decoder.power_decoder2 import Data
  17 from openpower.consts import MSR
  18
  19 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  20 from soc.experiment.l0_cache import PortInterface
  21 from soc.experiment.pimem import LDSTException
  22 from soc.experiment.compldst_multi import LDSTCompUnit, load, store
  23 from soc.config.test.test_loadstore import TestMemPspec
  24
  25 from soc.experiment.mmu import MMU
  26 from nmutil.util import Display
  27
  28 from soc.config.loadstore import ConfigMemoryPortInterface
  29 from soc.experiment.test import pagetables
  30 from soc.experiment.test.test_wishbone import wb_get
  31
  32 ########################################
  33
  34 # same thing as soc/src/soc/experiment/test/test_dcbz_pi.py
  35 def ldst_sim(dut):
  36     yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table
  37     addr = 0x100e0
  38     data = 0xf553b658ba7e1f51
  39
  40     yield from store(dut, addr, 0, data, 0)
  41     yield
  42     #TODO
  43     dut.stop = True # stop simulation
  44
  45 ########################################
  46
  47
  48 class TestLDSTCompUnitMMU(LDSTCompUnit):
  49
  50     def __init__(self, rwid, pspec):
  51         from soc.experiment.l0_cache import TstL0CacheBuffer
  52         self.l0 = l0 = TstL0CacheBuffer(pspec)
  53         pi = l0.l0.dports[0]
  54         LDSTCompUnit.__init__(self, pi, rwid, 4)
  55
  56     def elaborate(self, platform):
  57         m = LDSTCompUnit.elaborate(self, platform)
  58         m.submodules.l0 = self.l0
  59         # link addr-go direct to rel
  60         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  61         return m
  62
  63
  64 def test_scoreboard_mmu():
  65
  66     units = {}
  67     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  68                          imem_ifacetype='bare_wb',
  69                          addr_wid=48,
  70                          mask_wid=8,
  71                          reg_wid=64,
  72                          units=units)
  73
  74     dut = TestLDSTCompUnitMMU(16,pspec)
  75     vl = rtlil.convert(dut, ports=dut.ports())
  76     with open("test_ldst_comp_mmu1.il", "w") as f:
  77         f.write(vl)
  78
  79     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
  80
  81 ########################################
  82 class TestLDSTCompUnitRegSpecMMU(LDSTCompUnit):
  83
  84     def __init__(self, pspec):
  85         from soc.experiment.l0_cache import TstL0CacheBuffer
  86         from soc.fu.ldst.pipe_data import LDSTPipeSpec
  87         regspec = LDSTPipeSpec.regspec
  88
  89         # use a LoadStore1 here
  90
  91         cmpi = ConfigMemoryPortInterface(pspec)
  92         self.cmpi = cmpi
  93         ldst = cmpi.pi
  94         self.l0 = ldst
  95
  96         self.mmu = MMU()
  97         LDSTCompUnit.__init__(self, ldst.pi, regspec, 4)
  98
  99     def elaborate(self, platform):
 100         m = LDSTCompUnit.elaborate(self, platform)
 101         m.submodules.l0 = self.l0
 102         m.submodules.mmu = self.mmu
 103         # link addr-go direct to rel
 104         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 105
 106         # link mmu and dcache together
 107         dcache = self.l0.dcache
 108         mmu = self.mmu
 109         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 110         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 111
 112         return m
 113
 114
 115
 116
 117 def test_scoreboard_regspec_mmu():
 118
 119     m = Module()
 120
 121     units = {}
 122     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 123                          imem_ifacetype='bare_wb',
 124                          addr_wid=48,
 125                          mask_wid=8,
 126                          reg_wid=64,
 127                          units=units)
 128
 129     dut = TestLDSTCompUnitRegSpecMMU(pspec)
 130
 131     m.submodules.dut = dut
 132
 133     sim = Simulator(m)
 134     sim.add_clock(1e-6)
 135
 136     dut.mem = pagetables.test1
 137     dut.stop = False
 138
 139     sim.add_sync_process(wrap(ldst_sim(dut)))
 140     sim.add_sync_process(wrap(wb_get(dut)))
 141     with sim.write_vcd('test_scoreboard_regspec_mmu'):
 142         sim.run()
 143
 144
 145 if __name__ == '__main__':
 146     test_scoreboard_regspec_mmu()
 147     #only one test for now -- test_scoreboard_mmu()