src/soc/experiment/test/test_compldst_multi_mmu_fsm.py

   1 # test case for LOAD / STORE Computation Unit using MMU
   2
   3 from nmigen.back.pysim import Simulator, Delay, Settle, Tick
   4 from nmigen.cli import verilog, rtlil
   5 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
   6 from nmigen.hdl.rec import Record, Layout
   7
   8 from nmutil.latch import SRLatch, latchregister
   9 from nmutil.byterev import byte_reverse
  10 from nmutil.extend import exts
  11 from nmutil.util import wrap
  12 from soc.fu.regspec import RegSpecAPI
  13
  14 from openpower.decoder.power_enums import MicrOp, Function, LDSTMode
  15 from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
  16 from openpower.decoder.power_decoder2 import Data
  17 from openpower.consts import MSR
  18
  19 from soc.experiment.compalu_multi import go_record, CompUnitRecord
  20 from soc.experiment.l0_cache import PortInterface
  21 from soc.experiment.pimem import LDSTException
  22 from soc.experiment.compldst_multi import LDSTCompUnit, load, store
  23 from soc.config.test.test_loadstore import TestMemPspec
  24
  25 from soc.experiment.mmu import MMU
  26 from nmutil.util import Display
  27
  28 from soc.config.loadstore import ConfigMemoryPortInterface
  29 from soc.experiment.test import pagetables
  30 from soc.experiment.test.test_wishbone import wb_get
  31
  32 #new unit added to this test case
  33 from soc.fu.mmu.pipe_data import MMUPipeSpec
  34 from soc.fu.mmu.fsm import FSMMMUStage
  35
  36 def ldst_sim(dut):
  37     yield dut.mmu.rin.prtbl.eq(0x1000000) # set process table
  38     addr = 0x100e0
  39     data = 0xFF #just a single byte for this test
  40     #data = 0xf553b658ba7e1f51
  41
  42     yield from store(dut, addr, 0, data, 0)
  43     yield
  44     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
  45     print(data,data_ok,ld_addr)
  46     assert(ld_data==data)
  47     yield
  48
  49     data = 0
  50
  51     print("doing dcbz/store with data 0 .....")
  52     yield from store_debug(dut, addr, 0, data, 0, dcbz=True) #hangs
  53
  54     ld_data, data_ok, ld_addr = yield from load(dut, addr, 0, 0)
  55     print(data,data_ok,ld_addr)
  56     print("ld_data is")
  57     print(ld_data)
  58     assert(ld_data==data)
  59     print("dzbz test passed")
  60
  61     dut.stop = True # stop simulation
  62
  63 ########################################
  64
  65
  66 class TestLDSTCompUnitMMUFSM(LDSTCompUnit):
  67
  68     def __init__(self, rwid, pspec):
  69         from soc.experiment.l0_cache import TstL0CacheBuffer
  70         self.l0 = l0 = TstL0CacheBuffer(pspec)
  71         pi = l0.l0.dports[0]
  72         LDSTCompUnit.__init__(self, pi, rwid, 4)
  73
  74     def elaborate(self, platform):
  75         m = LDSTCompUnit.elaborate(self, platform)
  76         m.submodules.l0 = self.l0
  77         # link addr-go direct to rel
  78         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
  79         return m
  80
  81
  82 def test_scoreboard_mmu():
  83
  84     units = {}
  85     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  86                          imem_ifacetype='bare_wb',
  87                          addr_wid=48,
  88                          mask_wid=8,
  89                          reg_wid=64,
  90                          units=units)
  91
  92     dut = TestLDSTCompUnit(16,pspec)
  93     vl = rtlil.convertMMUFSM(dut, ports=dut.ports())
  94     with open("test_ldst_comp_mmu1.il", "w") as f:
  95         f.write(vl)
  96
  97     run_simulation(dut, ldst_sim(dut), vcd_name='test_ldst_comp.vcd')
  98
  99 ########################################
 100 class TestLDSTCompUnitRegSpecMMUFSM(LDSTCompUnit):
 101
 102     def __init__(self, pspec):
 103         from soc.experiment.l0_cache import TstL0CacheBuffer
 104         from soc.fu.ldst.pipe_data import LDSTPipeSpec
 105         regspec = LDSTPipeSpec.regspec
 106
 107         # use a LoadStore1 here
 108
 109         cmpi = ConfigMemoryPortInterface(pspec)
 110         self.cmpi = cmpi
 111         ldst = cmpi.pi
 112         self.l0 = ldst
 113
 114         self.mmu = MMU()
 115
 116         pipe_spec = MMUPipeSpec(id_wid=2)
 117         self.fsm = FSMMMUStage(pipe_spec)
 118
 119         self.fsm.set_ldst_interface(ldst)
 120
 121         LDSTCompUnit.__init__(self, ldst.pi, regspec, 4)
 122
 123     def elaborate(self, platform):
 124         m = LDSTCompUnit.elaborate(self, platform)
 125         m.submodules.l0 = self.l0
 126         m.submodules.mmu = self.mmu
 127         m.submodules.fsm = self.fsm
 128         # link addr-go direct to rel
 129         m.d.comb += self.ad.go_i.eq(self.ad.rel_o)
 130
 131         # link mmu and dcache together
 132         dcache = self.l0.dcache
 133         mmu = self.mmu
 134         m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
 135         m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
 136
 137         return m
 138
 139 def test_scoreboard_regspec_mmufsm():
 140
 141     m = Module()
 142
 143     units = {}
 144     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
 145                          imem_ifacetype='bare_wb',
 146                          addr_wid=48,
 147                          mask_wid=8,
 148                          reg_wid=64,
 149                          units=units)
 150
 151     dut = TestLDSTCompUnitRegSpecMMUFSM(pspec)
 152
 153     m.submodules.dut = dut
 154
 155     sim = Simulator(m)
 156     sim.add_clock(1e-6)
 157
 158     dut.mem = pagetables.test1
 159     dut.stop = False
 160
 161     sim.add_sync_process(wrap(ldst_sim(dut))) # rename ?
 162     sim.add_sync_process(wrap(wb_get(dut)))
 163     with sim.write_vcd('test_scoreboard_regspec_mmufsm.vcd'):
 164         sim.run()
 165
 166
 167 if __name__ == '__main__':
 168     test_scoreboard_regspec_mmufsm()
 169     #only one test for now -- test_scoreboard_mmu()