src/soc/experiment/test/test_ldst_pi_misalign.py

   1 """MMU PortInterface Test
   2
   3 quite basic, goes directly to the MMU to assert signals (does not
   4 yet use PortInterface)
   5 """
   6
   7 from nmigen import (C, Module, Signal, Elaboratable, Mux, Cat, Repl, Signal)
   8 from nmigen.cli import main
   9 from nmigen.cli import rtlil
  10 from nmutil.mask import Mask, masked
  11 from nmutil.util import Display
  12
  13 if True:
  14     from nmigen.back.pysim import Simulator, Delay, Settle
  15 else:
  16     from nmigen.sim.cxxsim import Simulator, Delay, Settle
  17 from nmutil.util import wrap
  18
  19 from soc.config.test.test_pi2ls import pi_ld, pi_st, pi_ldst
  20 from soc.config.test.test_loadstore import TestMemPspec
  21 from soc.config.loadstore import ConfigMemoryPortInterface
  22
  23 from soc.fu.ldst.loadstore import LoadStore1
  24 from soc.experiment.mmu import MMU
  25
  26 from nmigen.compat.sim import run_simulation
  27 from openpower.test.wb_get import wb_get
  28 from openpower.test import wb_get as wbget
  29 from openpower.decoder.power_enums import MSRSpec
  30
  31 msr_default = MSRSpec(pr=0, dr=0, sf=1) # 64 bit by default
  32
  33
  34 wbget.stop = False
  35
  36 def b(x): # byte-reverse function
  37     return int.from_bytes(x.to_bytes(8, byteorder='little'),
  38                           byteorder='big', signed=False)
  39
  40
  41 def setup_mmu():
  42
  43     pspec = TestMemPspec(ldst_ifacetype='mmu_cache_wb',
  44                          imem_ifacetype='',
  45                          addr_wid=48,
  46                          #disable_cache=True, # hmmm...
  47                          mask_wid=8,
  48                          reg_wid=64)
  49
  50     m = Module()
  51     comb = m.d.comb
  52     cmpi = ConfigMemoryPortInterface(pspec)
  53     m.submodules.ldst = ldst = cmpi.pi
  54     m.submodules.mmu = mmu = MMU()
  55     dcache = ldst.dcache
  56
  57     l_in, l_out = mmu.l_in, mmu.l_out
  58     d_in, d_out = dcache.d_in, dcache.d_out
  59
  60     # link mmu and dcache together
  61     m.d.comb += dcache.m_in.eq(mmu.d_out) # MMUToDCacheType
  62     m.d.comb += mmu.d_in.eq(dcache.m_out) # DCacheToMMUType
  63
  64     # link ldst and MMU together
  65     comb += l_in.eq(ldst.m_out)
  66     comb += ldst.m_in.eq(l_out)
  67
  68     return m, cmpi
  69
  70
  71
  72 def ldst_sim_misalign(dut):
  73     mmu = dut.submodules.mmu
  74     wbget.stop = False
  75
  76     yield mmu.rin.prtbl.eq(0x1000000) # set process table
  77     yield
  78
  79     # load 8 bytes at aligned address
  80     align_addr = 0x1000
  81     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  82                                           align_addr, 8, msr=msr_default)
  83     print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
  84     assert data == 0xdeadbeef01234567
  85
  86     # load 4 bytes at aligned address
  87     align_addr = 0x1004
  88     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  89                                           align_addr, 4, msr=msr_default)
  90     print ("ldst_sim_misalign (aligned)", hex(data), exctype, exc)
  91     assert data == 0xdeadbeef
  92
  93     # load 8 bytes at *mis*-aligned address
  94     misalign_addr = 0x1004
  95     data, exctype, exc = yield from pi_ld(dut.submodules.ldst.pi,
  96                                           misalign_addr, 8, msr=msr_default)
  97     print ("ldst_sim_misalign", data, exctype, exc)
  98     yield
  99     dar = yield dut.submodules.ldst.dar
 100     print ("DAR", hex(dar))
 101     assert dar == misalign_addr
 102     # check exception bits
 103     assert exc.happened
 104     assert exc.alignment
 105     assert not exc.segment_fault
 106     assert not exc.instr_fault
 107     assert not exc.invalid
 108     assert not exc.perm_error
 109     assert not exc.rc_error
 110     assert not exc.badtree
 111
 112     wbget.stop = True
 113
 114
 115 def test_misalign_mmu():
 116
 117     m, cmpi = setup_mmu()
 118
 119     # virtual "memory" to use for this test
 120
 121     mem = {0x10000:    # PARTITION_TABLE_2
 122                        # PATB_GR=1 PRTB=0x1000 PRTS=0xb
 123            b(0x800000000100000b),
 124
 125            0x30000:     # RADIX_ROOT_PTE
 126                         # V = 1 L = 0 NLB = 0x400 NLS = 9
 127            b(0x8000000000040009),
 128
 129            0x40000:     # RADIX_SECOND_LEVEL
 130                         #          V = 1 L = 1 SW = 0 RPN = 0
 131                            # R = 1 C = 1 ATT = 0 EAA 0x7
 132            b(0xc000000000000183),
 133
 134           0x1000000:   # PROCESS_TABLE_3
 135                        # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
 136            b(0x40000000000300ad),
 137
 138          # data to return
 139           0x1000: 0xdeadbeef01234567,
 140           0x1008: 0xfeedf00ff001a5a5
 141           }
 142
 143
 144     # nmigen Simulation
 145     sim = Simulator(m)
 146     sim.add_clock(1e-6)
 147
 148     sim.add_sync_process(wrap(ldst_sim_misalign(m)))
 149     sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
 150     with sim.write_vcd('test_ldst_pi_misalign.vcd'):
 151         sim.run()
 152
 153
 154 if __name__ == '__main__':
 155     test_misalign_mmu()