src/soc/fu/alu/test/svp64_cases.py

   1 from soc.fu.test.common import (TestAccumulatorBase, skip_case)
   2 from soc.config.endian import bigendian
   3 from soc.simulator.program import Program
   4 from soc.decoder.isa.caller import SVP64State
   5 from soc.sv.trans.svp64 import SVP64Asm
   6
   7
   8 class SVP64ALUTestCase(TestAccumulatorBase):
   9
  10     def case_1_sv_add(self):
  11         # adds:
  12         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
  13         #       2 = 6 + 10  => 0x3334 = 0x2223 + 0x1111
  14         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
  15         lst = list(isa)
  16         print("listing", lst)
  17
  18         # initial values in GPR regfile
  19         initial_regs = [0] * 32
  20         initial_regs[9] = 0x1234
  21         initial_regs[10] = 0x1111
  22         initial_regs[5] = 0x4321
  23         initial_regs[6] = 0x2223
  24         # SVSTATE (in this case, VL=2)
  25         svstate = SVP64State()
  26         svstate.vl[0:7] = 2  # VL
  27         svstate.maxvl[0:7] = 2  # MAXVL
  28         print("SVSTATE", bin(svstate.spr.asint()))
  29
  30         self.add_case(Program(lst, bigendian), initial_regs,
  31                       initial_svstate=svstate)
  32
  33     def case_2_sv_add_scalar(self):
  34         # adds:
  35         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
  36         isa = SVP64Asm(['sv.add 1, 5, 9'])
  37         lst = list(isa)
  38         print("listing", lst)
  39
  40         # initial values in GPR regfile
  41         initial_regs = [0] * 32
  42         initial_regs[9] = 0x1234
  43         initial_regs[5] = 0x4321
  44         svstate = SVP64State()
  45         # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
  46         svstate.vl[0:7] = 1  # VL
  47         svstate.maxvl[0:7] = 1  # MAXVL
  48         print("SVSTATE", bin(svstate.spr.asint()))
  49
  50         self.add_case(Program(lst, bigendian), initial_regs,
  51                       initial_svstate=svstate)
  52
  53     # This case helps checking the encoding of the Extra field
  54     # It was built so the v3.0b registers are: 3, 2, 1
  55     # and the Extra field is: 101.110.111
  56     # The expected SVP64 register numbers are: 13, 10, 7
  57     # Any mistake in decoding will probably give a different answer
  58     def case_3_sv_check_extra(self):
  59         # adds:
  60         #       13 = 10 + 7   => 0x4242 = 0x1230 + 0x3012
  61         isa = SVP64Asm(['sv.add 13.v, 10.v, 7.v'])
  62         lst = list(isa)
  63         print("listing", lst)
  64
  65         # initial values in GPR regfile
  66         initial_regs = [0] * 32
  67         initial_regs[7] = 0x3012
  68         initial_regs[10] = 0x1230
  69         svstate = SVP64State()
  70         # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
  71         svstate.vl[0:7] = 1  # VL
  72         svstate.maxvl[0:7] = 1  # MAXVL
  73         print("SVSTATE", bin(svstate.spr.asint()))
  74
  75         self.add_case(Program(lst, bigendian), initial_regs,
  76                       initial_svstate=svstate)
  77
  78     @skip_case("VL hardware loop is not yet implemented")
  79     def case_4_sv_check_vl_0(self):
  80         # adds:
  81         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
  82         isa = SVP64Asm([
  83             'sv.add 13.v, 10.v, 7.v',  # skipped, because VL == 0
  84             'add 1, 5, 9'
  85         ])
  86         lst = list(isa)
  87         print("listing", lst)
  88
  89         # initial values in GPR regfile
  90         initial_regs = [0] * 32
  91         initial_regs[9] = 0x1234
  92         initial_regs[5] = 0x4321
  93         initial_regs[7] = 0x3012
  94         initial_regs[10] = 0x1230
  95         svstate = SVP64State()
  96         # SVSTATE (in this case, VL=0, so vector instructions are skipped)
  97         svstate.vl[0:7] = 0  # VL
  98         svstate.maxvl[0:7] = 0  # MAXVL
  99         print("SVSTATE", bin(svstate.spr.asint()))
 100
 101         self.add_case(Program(lst, bigendian), initial_regs,
 102                       initial_svstate=svstate)