src/soc/fu/compunits/test/test_alu_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.alu.test.test_pipe_caller import ALUTestCase # creates the tests
   6 from soc.fu.alu.test.test_pipe_caller import test_data # imports the data
   7
   8 from soc.fu.compunits.compunits import ALUFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10
  11
  12 class ALUTestRunner(TestRunner):
  13     def __init__(self, test_data):
  14         super().__init__(test_data, ALUFunctionUnit, self,
  15                          Function.ALU)
  16
  17     def get_cu_inputs(self, dec2, sim):
  18         """naming (res) must conform to ALUFunctionUnit input regspec
  19         """
  20         res = {}
  21
  22         # RA (or RC)
  23         reg1_ok = yield dec2.e.read_reg1.ok
  24         if reg1_ok:
  25             data1 = yield dec2.e.read_reg1.data
  26             res['ra'] = sim.gpr(data1).value
  27
  28         # RB (or immediate)
  29         reg2_ok = yield dec2.e.read_reg2.ok
  30         if reg2_ok:
  31             data2 = yield dec2.e.read_reg2.data
  32             res['rb'] = sim.gpr(data2).value
  33
  34         # XER.ca
  35         cry_in = yield dec2.e.input_carry
  36         if True: #cry_in:
  37             carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  38             carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  39             res['xer_ca'] = carry | (carry32<<1)
  40
  41         # XER.so
  42         oe = yield dec2.e.oe.data & dec2.e.oe.ok
  43         if True: #oe:
  44             so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  45             res['xer_so'] = so
  46
  47         return res
  48
  49     def check_cu_outputs(self, res, dec2, sim, code):
  50         """naming (res) must conform to ALUFunctionUnit output regspec
  51         """
  52
  53         # RT
  54         out_reg_valid = yield dec2.e.write_reg.ok
  55         if out_reg_valid:
  56             write_reg_idx = yield dec2.e.write_reg.data
  57             expected = sim.gpr(write_reg_idx).value
  58             cu_out = res['o']
  59             print(f"expected {expected:x}, actual: {cu_out:x}")
  60             self.assertEqual(expected, cu_out, code)
  61
  62         rc = yield dec2.e.rc.data
  63         op = yield dec2.e.insn_type
  64         cridx_ok = yield dec2.e.write_cr.ok
  65         cridx = yield dec2.e.write_cr.data
  66
  67         print ("check extra output", repr(code), cridx_ok, cridx)
  68
  69         if rc:
  70             self.assertEqual(cridx_ok, 1, code)
  71             self.assertEqual(cridx, 0, code)
  72
  73         # CR (CR0-7)
  74         if cridx_ok:
  75             cr_expected = sim.crl[cridx].get_range().value
  76             cr_actual = res['cr_a']
  77             print ("CR", cridx, cr_expected, cr_actual)
  78             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  79
  80         # XER.ca
  81         cry_out = yield dec2.e.output_carry
  82         if cry_out:
  83             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  84             xer_ca = res['xer_ca']
  85             real_carry = xer_ca & 0b1 # XXX CO not CO32
  86             self.assertEqual(expected_carry, real_carry, code)
  87             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  88             real_carry32 = bool(xer_ca & 0b10) # XXX CO32
  89             self.assertEqual(expected_carry32, real_carry32, code)
  90
  91         # TODO: XER.ov and XER.so
  92         oe = yield dec2.e.oe.data
  93         if oe:
  94             xer_ov = res['xer_ov']
  95             xer_so = res['xer_so']
  96
  97
  98 if __name__ == "__main__":
  99     unittest.main(exit=False)
 100     suite = unittest.TestSuite()
 101     suite.addTest(ALUTestRunner(test_data))
 102
 103     runner = unittest.TextTestRunner()
 104     runner.run(suite)