4c8ee38765961fdf0eebb8959e9ac0f4fdf96ae4
[soc.git] / src / soc / fu / div / test / test_pipe_caller.py
1 import random
2 import unittest
3 from soc.simulator.program import Program
4 from soc.config.endian import bigendian
5
6 from soc.fu.test.common import (TestCase, TestAccumulatorBase, skip_case)
7 from soc.fu.div.pipe_data import DivPipeKind
8
9 from soc.fu.div.test.helper import (log_rand, get_cu_inputs,
10 set_alu_inputs, DivTestHelper)
11
12
13 class DivTestCases(TestAccumulatorBase):
14 def case_divw_regression(self):
15 # simulator is wrong, FSM and power-instruction-analyzer both correct
16 lst = [f"divw 0, 1, 2"]
17 initial_regs = [0] * 32
18 initial_regs[2] = 0x2
19 initial_regs[1] = 0x80000000
20 with Program(lst, bigendian) as prog:
21 self.add_case(prog, initial_regs)
22
23 # modulo
24 def case_modsd_regression2(self):
25 lst = [f"modsd 0, 1, 2"]
26 initial_regs = [0] * 32
27 initial_regs[2] = 0xff
28 initial_regs[1] = 0x7fffffffffffffff
29 with Program(lst, bigendian) as prog:
30 self.add_case(prog, initial_regs)
31
32 # modulo
33 def case_modsd_regression(self):
34 lst = [f"modsd 17, 27, 0"]
35 initial_regs = [0] * 32
36 initial_regs[0] = 0xff
37 initial_regs[27] = 0x7fffffffffffffff
38 with Program(lst, bigendian) as prog:
39 self.add_case(prog, initial_regs)
40
41 def case_divduo_regression(self):
42 lst = [f"divduo. 11, 20, 6"]
43 initial_regs = [0] * 32
44 # gpr: 00ff00ff00ff0080 <- r6
45 # gpr: 000000000000007f <- r11
46 # gpr: 7f6e5d4c3b2a1908 <- r20
47 initial_regs[6] = 0x00ff00ff00ff0080
48 initial_regs[20] = 0x7f6e5d4c3b2a1908
49 with Program(lst, bigendian) as prog:
50 self.add_case(prog, initial_regs)
51
52 def case_0_regression(self):
53 for i in range(40):
54 lst = ["divwo 3, 1, 2"]
55 initial_regs = [0] * 32
56 initial_regs[1] = 0xbc716835f32ac00c
57 initial_regs[2] = 0xcdf69a7f7042db66
58 with Program(lst, bigendian) as prog:
59 self.add_case(prog, initial_regs)
60
61 def case_1_regression(self):
62 lst = ["divwo 3, 1, 2"]
63 initial_regs = [0] * 32
64 initial_regs[1] = 0x10000000000000000-4
65 initial_regs[2] = 0x10000000000000000-2
66 with Program(lst, bigendian) as prog:
67 self.add_case(prog, initial_regs)
68
69 def case_2_regression(self):
70 lst = ["divwo 3, 1, 2"]
71 initial_regs = [0] * 32
72 initial_regs[1] = 0xffffffffffff9321
73 initial_regs[2] = 0xffffffffffff7012
74 with Program(lst, bigendian) as prog:
75 self.add_case(prog, initial_regs)
76
77 def case_3_regression(self):
78 lst = ["divwo. 3, 1, 2"]
79 initial_regs = [0] * 32
80 initial_regs[1] = 0x1b8e32f2458746af
81 initial_regs[2] = 0x6b8aee2ccf7d62e9
82 with Program(lst, bigendian) as prog:
83 self.add_case(prog, initial_regs)
84
85 def case_4_regression(self):
86 lst = ["divw 3, 1, 2"]
87 initial_regs = [0] * 32
88 initial_regs[1] = 0x1c4e6c2f3aa4a05c
89 initial_regs[2] = 0xe730c2eed6cc8dd7
90 with Program(lst, bigendian) as prog:
91 self.add_case(prog, initial_regs)
92
93 def case_5_regression(self):
94 lst = ["divw 3, 1, 2",
95 "divwo. 6, 4, 5"]
96 initial_regs = [0] * 32
97 initial_regs[1] = 0x1c4e6c2f3aa4a05c
98 initial_regs[2] = 0xe730c2eed6cc8dd7
99 initial_regs[4] = 0x1b8e32f2458746af
100 initial_regs[5] = 0x6b8aee2ccf7d62e9
101 with Program(lst, bigendian) as prog:
102 self.add_case(prog, initial_regs)
103
104 def case_6_regression(self):
105 # CR0 not getting set properly for this one
106 # turns out that overflow is not set correctly in
107 # fu/div/output_stage.py calc_overflow
108 # https://bugs.libre-soc.org/show_bug.cgi?id=425
109 lst = ["divw. 3, 1, 2"]
110 initial_regs = [0] * 32
111 initial_regs[1] = 0x61c1cc3b80f2a6af
112 initial_regs[2] = 0x9dc66a7622c32bc0
113 with Program(lst, bigendian) as prog:
114 self.add_case(prog, initial_regs)
115
116 def case_7_regression(self):
117 # https://bugs.libre-soc.org/show_bug.cgi?id=425
118 lst = ["divw. 3, 1, 2"]
119 initial_regs = [0] * 32
120 initial_regs[1] = 0xf1791627e05e8096
121 initial_regs[2] = 0xffc868bf4573da0b
122 with Program(lst, bigendian) as prog:
123 self.add_case(prog, initial_regs)
124
125 def case_8_fsm_regression(self): # FSM result is "36" not 6
126 lst = ["divwu. 3, 1, 2"]
127 initial_regs = [0] * 32
128 initial_regs[1] = 18
129 initial_regs[2] = 3
130 with Program(lst, bigendian) as prog:
131 self.add_case(prog, initial_regs)
132
133 def case_9_regression(self): # CR0 fails: expected 0b10, actual 0b11
134 lst = ["divw. 3, 1, 2"]
135 initial_regs = [0] * 32
136 initial_regs[1] = 1
137 initial_regs[2] = 0
138 with Program(lst, bigendian) as prog:
139 self.add_case(prog, initial_regs)
140
141 @skip_case("causes test_issuer to go permanently busy!")
142 def case_10_regression(self): # overflow fails
143 lst = ["divwo 3, 1, 2"]
144 initial_regs = [0] * 32
145 initial_regs[1] = 0xbc716835f32ac00c
146 initial_regs[2] = 0xcdf69a7f7042db66
147 with Program(lst, bigendian) as prog:
148 self.add_case(prog, initial_regs)
149
150 def case_11_regression(self):
151 lst = ["divwo. 3, 1, 2"]
152 initial_regs = [0] * 32
153 initial_regs[1] = 0xffffffffffffffff
154 initial_regs[2] = 0xffffffffffffffff
155 with Program(lst, bigendian) as prog:
156 self.add_case(prog, initial_regs)
157
158 def case_divw_by_zero_1(self):
159 lst = ["divw. 3, 1, 2"]
160 initial_regs = [0] * 32
161 initial_regs[1] = 0x1
162 initial_regs[2] = 0x0
163 with Program(lst, bigendian) as prog:
164 self.add_case(prog, initial_regs)
165
166 def case_divw_overflow2(self):
167 lst = ["divw. 3, 1, 2"]
168 initial_regs = [0] * 32
169 initial_regs[1] = 0x80000000
170 initial_regs[2] = 0xffffffffffffffff # top bits don't seem to matter
171 with Program(lst, bigendian) as prog:
172 self.add_case(prog, initial_regs)
173
174 def case_divw_overflow3(self):
175 lst = ["divw. 3, 1, 2"]
176 initial_regs = [0] * 32
177 initial_regs[1] = 0x80000000
178 initial_regs[2] = 0xffffffff
179 with Program(lst, bigendian) as prog:
180 self.add_case(prog, initial_regs)
181
182 def case_divwuo_regression_1(self):
183 lst = ["divwuo. 3, 1, 2"]
184 initial_regs = [0] * 32
185 initial_regs[1] = 0x7591a398c4e32b68
186 initial_regs[2] = 0x48674ab432867d69
187 with Program(lst, bigendian) as prog:
188 self.add_case(prog, initial_regs)
189
190 def case_divwuo_1(self):
191 lst = ["divwuo. 3, 1, 2"]
192 initial_regs = [0] * 32
193 initial_regs[1] = 0x50
194 initial_regs[2] = 0x2
195 with Program(lst, bigendian) as prog:
196 self.add_case(prog, initial_regs)
197
198 def case_rand_divwu(self):
199 insns = ["divwu", "divwu.", "divwuo", "divwuo."]
200 for i in range(40):
201 choice = random.choice(insns)
202 lst = [f"{choice} 3, 1, 2"]
203 initial_regs = [0] * 32
204 initial_regs[1] = log_rand(32)
205 initial_regs[2] = log_rand(32)
206 with Program(lst, bigendian) as prog:
207 self.add_case(prog, initial_regs)
208
209 def case_rand_divw(self):
210 insns = ["divw", "divw.", "divwo", "divwo."]
211 for i in range(40):
212 choice = random.choice(insns)
213 lst = [f"{choice} 3, 1, 2"]
214 initial_regs = [0] * 32
215 initial_regs[1] = log_rand(32)
216 initial_regs[2] = log_rand(32)
217 with Program(lst, bigendian) as prog:
218 self.add_case(prog, initial_regs)
219
220
221 class TestPipe(DivTestHelper):
222 def test_div_pipe_core(self):
223 self.run_all(DivTestCases().test_data,
224 DivPipeKind.DivPipeCore, "div_pipe_caller")
225
226 def test_fsm_div_core(self):
227 self.run_all(DivTestCases().test_data,
228 DivPipeKind.FSMDivCore, "div_pipe_caller")
229
230 def test_sim_only(self):
231 self.run_all(DivTestCases().test_data,
232 DivPipeKind.SimOnly, "div_pipe_caller")
233
234
235 if __name__ == "__main__":
236 unittest.main()