5e41cbf33eb6ee7d97036aa8a6a7e4e5870f84b0
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
, CryIn
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import TestCase
16 from soc
.fu
.ldst
.pipe_data
import LDSTPipeSpec
20 def get_cu_inputs(dec2
, sim
):
21 """naming (res) must conform to LDSTFunctionUnit input regspec
26 reg1_ok
= yield dec2
.e
.read_reg1
.ok
28 data1
= yield dec2
.e
.read_reg1
.data
29 res
['ra'] = sim
.gpr(data1
).value
32 reg2_ok
= yield dec2
.e
.read_reg2
.ok
34 data2
= yield dec2
.e
.read_reg2
.data
35 res
['rb'] = sim
.gpr(data2
).value
38 reg3_ok
= yield dec2
.e
.read_reg3
.ok
40 data3
= yield dec2
.e
.read_reg3
.data
41 res
['rc'] = sim
.gpr(data3
).value
44 oe
= yield dec2
.e
.do
.oe
.data
[0] & dec2
.e
.do
.oe
.ok
46 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
52 class LDSTTestCase(FHDLTestCase
):
55 def __init__(self
, name
):
56 super().__init
__(name
)
59 def run_tst_program(self
, prog
, initial_regs
=None,
60 initial_sprs
=None, initial_mem
=None):
61 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
,
63 self
.test_data
.append(tc
)
65 def test_1_load(self
):
67 initial_regs
= [0] * 32
68 initial_regs
[1] = 0x0004
69 initial_regs
[2] = 0x0008
70 initial_mem
= {0x0000: (0x5432123412345678, 8),
71 0x0008: (0xabcdef0187654321, 8),
72 0x0020: (0x1828384822324252, 8),
74 self
.run_tst_program(Program(lst
), initial_regs
,
75 initial_mem
=initial_mem
)
77 def test_2_load_store(self
):
82 initial_regs
= [0] * 32
83 initial_regs
[1] = 0x0004
84 initial_regs
[2] = 0x0008
85 initial_regs
[3] = 0x00ee
86 initial_mem
= {0x0000: (0x5432123412345678, 8),
87 0x0008: (0xabcdef0187654321, 8),
88 0x0020: (0x1828384822324252, 8),
90 self
.run_tst_program(Program(lst
), initial_regs
,
91 initial_mem
=initial_mem
)
93 def test_3_load_store(self
):
96 initial_regs
= [0] * 32
97 initial_regs
[1] = 0x0004
98 initial_regs
[2] = 0x0002
99 initial_regs
[3] = 0x15eb
100 initial_mem
= {0x0000: (0x5432123412345678, 8),
101 0x0008: (0xabcdef0187654321, 8),
102 0x0020: (0x1828384822324252, 8),
104 self
.run_tst_program(Program(lst
), initial_regs
,
105 initial_mem
=initial_mem
)
107 def test_4_load_store_rev_ext(self
):
108 lst
= ["stwx 1, 4, 2",
110 initial_regs
= [0] * 32
111 initial_regs
[1] = 0x5678
112 initial_regs
[2] = 0x001c
113 initial_regs
[4] = 0x0008
114 initial_mem
= {0x0000: (0x5432123412345678, 8),
115 0x0008: (0xabcdef0187654321, 8),
116 0x0020: (0x1828384822324252, 8),
118 self
.run_tst_program(Program(lst
), initial_regs
,
119 initial_mem
=initial_mem
)
121 def test_5_load_store_rev_ext(self
):
122 lst
= ["stwbrx 1, 4, 2",
124 initial_regs
= [0] * 32
125 initial_regs
[1] = 0x5678
126 initial_regs
[2] = 0x001c
127 initial_regs
[4] = 0x0008
128 initial_mem
= {0x0000: (0x5432123412345678, 8),
129 0x0008: (0xabcdef0187654321, 8),
130 0x0020: (0x1828384822324252, 8),
132 self
.run_tst_program(Program(lst
), initial_regs
,
133 initial_mem
=initial_mem
)
135 def test_6_load_store_rev_ext(self
):
136 lst
= ["stwbrx 1, 4, 2",
138 initial_regs
= [0] * 32
139 initial_regs
[1] = 0x5678
140 initial_regs
[2] = 0x001c
141 initial_regs
[4] = 0x0008
142 initial_mem
= {0x0000: (0x5432123412345678, 8),
143 0x0008: (0xabcdef0187654321, 8),
144 0x0020: (0x1828384822324252, 8),
146 self
.run_tst_program(Program(lst
), initial_regs
,
147 initial_mem
=initial_mem
)