src/soc/fu/logical/logical_input_record.py

   1 from nmigen.hdl.rec import Record, Layout
   2
   3 from soc.decoder.power_enums import MicrOp, Function, CryIn
   4
   5
   6 class CompLogicalOpSubset(Record):
   7     """CompLogicalOpSubset
   8
   9     a copy of the relevant subset information from Decode2Execute1Type
  10     needed for Logical operations.  use with eq_from_execute1 (below) to
  11     grab subsets.
  12     """
  13     def __init__(self, name=None):
  14         layout = (('insn_type', MicrOp),
  15                   ('fn_unit', Function),
  16                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
  17                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
  18                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
  19                   ('invert_a', 1),
  20                   ('zero_a', 1),
  21                   ('input_carry', CryIn),
  22                   ('invert_out', 1),
  23                   ('write_cr0', 1),
  24                   ('output_carry', 1),
  25                   ('is_32bit', 1),
  26                   ('is_signed', 1),
  27                   ('data_len', 4),
  28                   ('insn', 32),
  29                   )
  30
  31         Record.__init__(self, Layout(layout), name=name)
  32
  33         # grrr.  Record does not have kwargs
  34         self.insn_type.reset_less = True
  35         self.fn_unit.reset_less = True
  36         self.zero_a.reset_less = True
  37         self.invert_a.reset_less = True
  38         self.invert_out.reset_less = True
  39         self.input_carry.reset_less = True
  40         self.output_carry.reset_less = True
  41         self.is_32bit.reset_less = True
  42         self.is_signed.reset_less = True
  43         self.data_len.reset_less = True
  44
  45     def eq_from_execute1(self, other):
  46         """ use this to copy in from Decode2Execute1Type
  47         """
  48         res = []
  49         for fname, sig in self.fields.items():
  50             eqfrom = other.do.fields[fname]
  51             res.append(sig.eq(eqfrom))
  52         return res
  53
  54     def ports(self):
  55         return [self.insn_type,
  56                 self.fn_unit,
  57                 self.invert_a,
  58                 self.invert_out,
  59                 self.input_carry,
  60                 self.output_carry,
  61                 self.is_32bit,
  62                 self.is_signed,
  63                 self.data_len,
  64         ]