src/soc/fu/mmu/test/test_issuer_mmu_data_path.py

   1 from nmigen import Module, Signal
   2 from soc.simple.test.test_issuer import TestRunner
   3 from openpower.simulator.program import Program
   4 from openpower.endian import bigendian
   5 import unittest
   6
   7 from openpower.test.common import (
   8     TestAccumulatorBase, skip_case, TestCase, ALUHelpers)
   9
  10 # this test case takes about half a minute to run on my Talos II
  11 class MMUTestCase(TestAccumulatorBase):
  12     # MMU on microwatt handles MTSPR, MFSPR, DCBZ and TLBIE.
  13     # libre-soc has own SPR unit
  14     # other instructions here -> must be load/store
  15
  16     def case_mmu_dar(self):
  17         lst = [
  18                  "mfspr 1, 720",     # DAR to reg 1
  19                 "addi 7, 0, 1",
  20                 "mtspr 19, 3",      # reg 3 to DAR
  21                 "mulli 7, 0, 1",
  22               ]
  23
  24         initial_regs = [0] * 32
  25         initial_regs[1] = 0x2
  26         initial_regs[3] = 0x5
  27
  28         initial_sprs = {'DAR': 0x87654321,
  29                         }
  30         self.add_case(Program(lst, bigendian),
  31                       initial_regs, initial_sprs)
  32
  33     def cse_mmu_ldst(self):
  34         lst = [
  35                 "dcbz 1,2",
  36                 "tlbie 0,0,0,0,0", # RB,RS,RIC,PRS,R
  37                 "mtspr 18, 1",     # reg 1 to DSISR
  38                 "mtspr 19, 2",     # reg 2 to DAR
  39                 "mfspr 5, 18",     # DSISR to reg 5
  40                 "mfspr 6, 19",     # DAR to reg 6
  41                 "mtspr 48, 3",    # set MMU PID
  42                 "mtspr 720, 4",    # set MMU PRTBL
  43                 "lhz 3, 0(1)",     # load some data
  44                 "addi 7, 0, 1"
  45               ]
  46
  47         initial_regs = [0] * 32
  48         initial_regs[1] = 0x2
  49         initial_regs[2] = 0x2020
  50         initial_regs[3] = 5
  51         initial_regs[4] = 0xDEADBEEF
  52
  53         initial_sprs = {'DSISR': 0x12345678, 'DAR': 0x87654321,
  54                         'PIDR': 0xabcd, 'PRTBL': 0x0def}
  55         self.add_case(Program(lst, bigendian),
  56                       initial_regs, initial_sprs)
  57
  58
  59 if __name__ == "__main__":
  60     mem = {}
  61     unittest.main(exit=False)
  62     suite = unittest.TestSuite()
  63     suite.addTest(TestRunner(MMUTestCase().test_data,
  64                              microwatt_mmu=True,
  65                              svp64=False,
  66                              rom=mem))
  67     runner = unittest.TextTestRunner()
  68     runner.run(suite)