a55e80d1d335d19bdb1ee04475291aaabc0d06fa
1 from soc
.fu
.mul
.mul_input_record
import CompMULOpSubset
2 from soc
.fu
.pipe_data
import FUBaseData
, CommonPipeSpec
3 from soc
.fu
.div
.pipe_data
import DivInputData
, DivMulOutputData
4 from nmigen
import Signal
7 class MulIntermediateData(DivInputData
):
8 def __init__(self
, pspec
):
9 super().__init
__(pspec
)
11 self
.neg_res
= Signal(reset_less
=True)
12 self
.neg_res32
= Signal(reset_less
=True)
13 self
.data
.append(self
.neg_res
)
14 self
.data
.append(self
.neg_res32
)
17 class MulOutputData(FUBaseData
):
18 regspec
= [('INT', 'o', '0:128'),
19 ('XER', 'xer_so', '32')] # XER bit 32: SO
20 def __init__(self
, pspec
):
21 super().__init
__(pspec
, False) # still input style
23 self
.neg_res
= Signal(reset_less
=True)
24 self
.neg_res32
= Signal(reset_less
=True)
25 self
.data
.append(self
.neg_res
)
26 self
.data
.append(self
.neg_res32
)
29 class MulPipeSpec(CommonPipeSpec
):
30 regspec
= (DivInputData
.regspec
, DivMulOutputData
.regspec
)
31 opsubsetkls
= CompMULOpSubset