src/soc/fu/pipe_data.py

   1 from nmutil.concurrentunit import PipeContext
   2 from nmutil.dynamicpipe import SimpleHandshakeRedir
   3 from nmigen import Signal
   4 from soc.decoder.power_decoder2 import Data
   5 from soc.fu.regspec import get_regspec_bitwidth
   6
   7
   8 class IntegerData:
   9
  10     def __init__(self, pspec, output):
  11         self.ctx = PipeContext(pspec) # context for ReservationStation usage
  12         self.muxid = self.ctx.muxid
  13         self.data = []
  14         self.is_output = output
  15         for i, (regfile, regname, widspec) in enumerate(self.regspec):
  16             wid = get_regspec_bitwidth([self.regspec], 0, i)
  17             if output:
  18                 sig = Data(wid, name=regname)
  19             else:
  20                 sig = Signal(wid, name=regname, reset_less=True)
  21             setattr(self, regname, sig)
  22             self.data.append(sig)
  23
  24     def __iter__(self):
  25         yield from self.ctx
  26         yield from self.data
  27
  28     def eq(self, i):
  29         eqs = [self.ctx.eq(i.ctx)]
  30         assert len(self.data) == len(i.data), \
  31                "length of %s mismatch against %s: %s %s" % \
  32                    (repr(self), repr(i), repr(self.data), repr(i.data))
  33         for j in range(len(self.data)):
  34             assert type(self.data[j]) == type(i.data[j]), \
  35                    "type mismatch in IntegerData %s %s" % \
  36                    (repr(self.data[j]), repr(i.data[j]))
  37             eqs.append(self.data[j].eq(i.data[j]))
  38         return eqs
  39
  40     def ports(self):
  41         return self.ctx.ports() # TODO: include self.data
  42
  43
  44 # hmmm there has to be a better way than this
  45 def get_rec_width(rec):
  46     recwidth = 0
  47     # Setup random inputs for dut.op
  48     for p in rec.ports():
  49         width = p.width
  50         recwidth += width
  51     return recwidth
  52
  53
  54 class CommonPipeSpec:
  55     def __init__(self, id_wid):
  56         self.pipekls = SimpleHandshakeRedir
  57         self.id_wid = id_wid
  58         self.opkls = lambda _: self.opsubsetkls(name="op")
  59         self.op_wid = get_rec_width(self.opkls(None)) # hmm..
  60         self.stage = None