src/soc/fu/spr/main_stage.py

   1 """SPR Pipeline
   2
   3 * https://bugs.libre-soc.org/show_bug.cgi?id=348
   4 * https://libre-soc.org/openpower/isa/sprset/
   5 """
   6
   7 from nmigen import (Module, Signal, Cat)
   8 from nmutil.pipemodbase import PipeModBase
   9 from soc.fu.spr.pipe_data import SPRInputData, SPROutputData
  10 from openpower.decoder.power_enums import MicrOp, SPRfull, SPRreduced, XER_bits
  11
  12 from openpower.decoder.power_fields import DecodeFields
  13 from openpower.decoder.power_fieldsn import SignalBitRange
  14 from openpower.decoder.power_decoder2 import decode_spr_num
  15
  16
  17 class SPRMainStage(PipeModBase):
  18     def __init__(self, pspec):
  19         super().__init__(pspec, "spr_main")
  20         # test if regfiles are reduced
  21         self.regreduce_en = (hasattr(pspec, "regreduce") and
  22                              (pspec.regreduce == True))
  23
  24         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
  25         self.fields.create_specs()
  26
  27     def ispec(self):
  28         return SPRInputData(self.pspec)
  29
  30     def ospec(self):
  31         return SPROutputData(self.pspec)
  32
  33     def elaborate(self, platform):
  34         if self.regreduce_en:
  35             SPR = SPRreduced
  36         else:
  37             SPR = SPRfull
  38         m = Module()
  39         comb = m.d.comb
  40         op = self.i.ctx.op
  41
  42         # convenience variables
  43         a_i, spr1_i, fast1_i = self.i.a, self.i.spr1, self.i.fast1
  44         so_i, ov_i, ca_i = self.i.xer_so, self.i.xer_ov, self.i.xer_ca
  45         so_o, ov_o, ca_o = self.o.xer_so, self.o.xer_ov, self.o.xer_ca
  46         o, spr1_o, fast1_o = self.o.o, self.o.spr1, self.o.fast1
  47
  48         # take copy of D-Form TO field
  49         x_fields = self.fields.FormXFX
  50         spr = Signal(len(x_fields.SPR))
  51         comb += spr.eq(decode_spr_num(x_fields.SPR))
  52
  53         # TODO: some #defines for the bits n stuff.
  54         with m.Switch(op.insn_type):
  55             #### MTSPR ####
  56             with m.Case(MicrOp.OP_MTSPR):
  57                 with m.Switch(spr):
  58                     # fast SPRs first
  59                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0,
  60                                 SPR.SRR1, SPR.XER, SPR.DEC, SPR.TB):
  61                         comb += fast1_o.data.eq(a_i)
  62                         comb += fast1_o.ok.eq(1)
  63                         # XER is constructed
  64                         with m.If(spr == SPR.XER):
  65                             # sticky
  66                             comb += so_o.data.eq(a_i[63-XER_bits['SO']])
  67                             comb += so_o.ok.eq(1)
  68                             # overflow
  69                             comb += ov_o.data[0].eq(a_i[63-XER_bits['OV']])
  70                             comb += ov_o.data[1].eq(a_i[63-XER_bits['OV32']])
  71                             comb += ov_o.ok.eq(1)
  72                             # carry
  73                             comb += ca_o.data[0].eq(a_i[63-XER_bits['CA']])
  74                             comb += ca_o.data[1].eq(a_i[63-XER_bits['CA32']])
  75                             comb += ca_o.ok.eq(1)
  76
  77                     # slow SPRs TODO
  78                     with m.Default():
  79                         comb += spr1_o.data.eq(a_i)
  80                         comb += spr1_o.ok.eq(1)
  81
  82             # move from SPRs
  83             with m.Case(MicrOp.OP_MFSPR):
  84                 comb += o.ok.eq(1)
  85                 with m.Switch(spr):
  86                     # fast SPRs first
  87                     with m.Case(SPR.CTR, SPR.LR, SPR.TAR, SPR.SRR0, SPR.SRR1,
  88                                 SPR.XER, SPR.DEC, SPR.TB):
  89                         comb += o.data.eq(fast1_i)
  90                         with m.If(spr == SPR.XER):
  91                             # bits 0:31 and 35:43 are treated as reserved
  92                             # and return 0s when read using mfxer
  93                             comb += o[32:64].eq(0)       # MBS0 bits 0-31
  94                             comb += o[63-43:64-35].eq(0)  # MSB0 bits 35-43
  95                             # sticky
  96                             comb += o[63-XER_bits['SO']].eq(so_i)
  97                             # overflow
  98                             comb += o[63-XER_bits['OV']].eq(ov_i[0])
  99                             comb += o[63-XER_bits['OV32']].eq(ov_i[1])
 100                             # carry
 101                             comb += o[63-XER_bits['CA']].eq(ca_i[0])
 102                             comb += o[63-XER_bits['CA32']].eq(ca_i[1])
 103                     with m.Case(SPR.TBU):
 104                         comb += o.data[0:32].eq(fast1_i[32:64])
 105
 106                     # slow SPRs TODO
 107                     with m.Default():
 108                         comb += o.data.eq(spr1_i)
 109
 110         comb += self.o.ctx.eq(self.i.ctx)
 111
 112         return m