ceac442cdf2f30ac10375f171d18addb30a16217
3 not in any way intended for production use. connects up FunctionUnits to
4 Register Files in a brain-dead fashion that only permits one and only one
5 Function Unit to be operational.
7 the principle here is to take the Function Units, analyse their regspecs,
8 and turn their requirements for access to register file read/write ports
9 into groupings by Register File and Register File Port name.
11 under each grouping - by regfile/port - a list of Function Units that
12 need to connect to that port is created. as these are a contended
13 resource a "Broadcast Bus" per read/write port is then also created,
14 with access to it managed by a PriorityPicker.
16 the brain-dead part of this module is that even though there is no
17 conflict of access, regfile read/write hazards are *not* analysed,
18 and consequently it is safer to wait for the Function Unit to complete
19 before allowing a new instruction to proceed.
22 from nmigen
import Elaboratable
, Module
, Signal
23 from nmigen
.cli
import rtlil
25 from nmutil
.picker
import PriorityPicker
26 from nmutil
.util
import treereduce
28 from soc
.fu
.compunits
.compunits
import AllFunctionUnits
29 from soc
.regfile
.regfiles
import RegFiles
30 from soc
.decoder
.power_decoder
import create_pdecode
31 from soc
.decoder
.power_decoder2
import PowerDecode2
32 from soc
.decoder
.decode2execute1
import Data
33 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
# test only
34 from soc
.config
.test
.test_loadstore
import TestMemPspec
35 from soc
.decoder
.power_enums
import InternalOp
39 # helper function for reducing a list of signals down to a parallel
41 def ortreereduce(tree
, attr
="data_o"):
42 return treereduce(tree
, operator
.or_
, lambda x
: getattr(x
, attr
))
44 def ortreereduce_sig(tree
):
45 return treereduce(tree
, operator
.or_
, lambda x
: x
)
48 # helper function to place full regs declarations first
49 def sort_fuspecs(fuspecs
):
51 for (regname
, fspec
) in fuspecs
.items():
52 if regname
.startswith("full"):
53 res
.append((regname
, fspec
))
54 for (regname
, fspec
) in fuspecs
.items():
55 if not regname
.startswith("full"):
56 res
.append((regname
, fspec
))
57 return res
# enumerate(res)
60 class NonProductionCore(Elaboratable
):
61 def __init__(self
, pspec
):
62 # single LD/ST funnel for memory access
63 self
.l0
= TstL0CacheBuffer(pspec
, n_units
=1)
64 pi
= self
.l0
.l0
.dports
[0]
66 # function units (only one each)
67 self
.fus
= AllFunctionUnits(pspec
, pilist
=[pi
])
69 # register files (yes plural)
70 self
.regs
= RegFiles()
73 pdecode
= create_pdecode()
74 self
.pdecode2
= PowerDecode2(pdecode
) # instruction decoder
76 # issue/valid/busy signalling
77 self
.ivalid_i
= self
.pdecode2
.valid
# instruction is valid
78 self
.issue_i
= Signal(reset_less
=True)
79 self
.busy_o
= Signal(name
="corebusy_o", reset_less
=True)
82 self
.bigendian_i
= self
.pdecode2
.dec
.bigendian
83 self
.raw_opcode_i
= self
.pdecode2
.dec
.raw_opcode_in
85 # start/stop and terminated signalling
86 self
.core_start_i
= Signal(reset_less
=True)
87 self
.core_stop_i
= Signal(reset_less
=True)
88 self
.core_terminated_o
= Signal(reset
=1) # indicates stopped
90 def elaborate(self
, platform
):
93 m
.submodules
.pdecode2
= dec2
= self
.pdecode2
94 m
.submodules
.fus
= self
.fus
95 m
.submodules
.l0
= l0
= self
.l0
96 self
.regs
.elaborate_into(m
, platform
)
100 # core start/stopped state
101 core_stopped
= Signal(reset
=1) # begins in stopped state
103 # start/stop signalling
104 with m
.If(self
.core_start_i
):
105 m
.d
.sync
+= core_stopped
.eq(0)
106 with m
.If(self
.core_stop_i
):
107 m
.d
.sync
+= core_stopped
.eq(1)
108 m
.d
.comb
+= self
.core_terminated_o
.eq(core_stopped
)
110 # connect up Function Units, then read/write ports
111 fu_bitdict
= self
.connect_instruction(m
, core_stopped
)
112 self
.connect_rdports(m
, fu_bitdict
)
113 self
.connect_wrports(m
, fu_bitdict
)
117 def connect_instruction(self
, m
, core_stopped
):
118 """connect_instruction
120 uses decoded (from PowerOp) function unit information from CSV files
121 to ascertain which Function Unit should deal with the current
124 some (such as OP_ATTN, OP_NOP) are dealt with here, including
125 ignoring it and halting the processor. OP_NOP is a bit annoying
126 because the issuer expects busy flag still to be raised then lowered.
127 (this requires a fake counter to be set).
129 comb
, sync
= m
.d
.comb
, m
.d
.sync
133 # enable-signals for each FU, get one bit for each FU (by name)
134 fu_enable
= Signal(len(fus
), reset_less
=True)
136 for i
, funame
in enumerate(fus
.keys()):
137 fu_bitdict
[funame
] = fu_enable
[i
]
138 # only run when allowed and when instruction is valid
139 can_run
= Signal(reset_less
=True)
140 comb
+= can_run
.eq(self
.ivalid_i
& ~core_stopped
)
142 # enable the required Function Unit based on the opcode decode
143 # note: this *only* works correctly for simple core when one and
144 # *only* one FU is allocated per instruction
145 for funame
, fu
in fus
.items():
146 fnunit
= fu
.fnunit
.value
147 enable
= Signal(name
="en_%s" % funame
, reset_less
=True)
148 comb
+= enable
.eq((dec2
.e
.do
.fn_unit
& fnunit
).bool())
149 comb
+= fu_bitdict
[funame
].eq(enable
)
151 # sigh - need a NOP counter
153 with m
.If(counter
!= 0):
154 sync
+= counter
.eq(counter
- 1)
155 comb
+= self
.busy_o
.eq(1)
158 with m
.Switch(dec2
.e
.do
.insn_type
):
159 # check for ATTN: halt if true
160 with m
.Case(InternalOp
.OP_ATTN
):
161 m
.d
.sync
+= core_stopped
.eq(1)
163 with m
.Case(InternalOp
.OP_NOP
):
164 sync
+= counter
.eq(2)
165 comb
+= self
.busy_o
.eq(1)
168 # connect up instructions. only one enabled at a time
169 for funame
, fu
in fus
.items():
170 enable
= fu_bitdict
[funame
]
172 # run this FunctionUnit if enabled
174 # route op, issue, busy, read flags and mask to FU
175 comb
+= fu
.oper_i
.eq_from_execute1(dec2
.e
)
176 comb
+= fu
.issue_i
.eq(self
.issue_i
)
177 comb
+= self
.busy_o
.eq(fu
.busy_o
)
178 rdmask
= dec2
.rdflags(fu
)
179 comb
+= fu
.rdmaskn
.eq(~rdmask
)
183 def connect_rdports(self
, m
, fu_bitdict
):
184 """connect read ports
186 orders the read regspecs into a dict-of-dicts, by regfile, by
187 regport name, then connects all FUs that want that regport by
188 way of a PriorityPicker.
190 comb
, sync
= m
.d
.comb
, m
.d
.sync
194 # dictionary of lists of regfile read ports
195 byregfiles_rd
, byregfiles_rdspec
= self
.get_byregfiles(True)
197 # okaay, now we need a PriorityPicker per regfile per regfile port
198 # loootta pickers... peter piper picked a pack of pickled peppers...
200 for regfile
, spec
in byregfiles_rd
.items():
201 fuspecs
= byregfiles_rdspec
[regfile
]
202 rdpickers
[regfile
] = {}
204 # for each named regfile port, connect up all FUs to that port
205 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
206 print ("connect rd", regname
, fspec
)
208 # get the regfile specs for this regfile port
209 (rf
, read
, write
, wid
, fuspec
) = fspec
210 name
= "rdflag_%s_%s" % (regfile
, regname
)
211 rdflag
= Signal(name
=name
, reset_less
=True)
212 comb
+= rdflag
.eq(rf
)
214 # select the required read port. these are pre-defined sizes
215 print (rpidx
, regfile
, regs
.rf
.keys())
216 rport
= regs
.rf
[regfile
.lower()].r_ports
[rpidx
]
218 # create a priority picker to manage this port
219 rdpickers
[regfile
][rpidx
] = rdpick
= PriorityPicker(len(fuspec
))
220 setattr(m
.submodules
, "rdpick_%s_%s" % (regfile
, rpidx
), rdpick
)
222 # connect the regspec "reg select" number to this port
223 with m
.If(rdpick
.en_o
):
224 comb
+= rport
.ren
.eq(read
)
226 # connect up the FU req/go signals, and the reg-read to the FU
227 # and create a Read Broadcast Bus
228 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
231 # connect request-read to picker input, and output to go-rd
232 fu_active
= fu_bitdict
[funame
]
233 pick
= fu
.rd_rel_o
[idx
] & fu_active
& rdflag
234 comb
+= rdpick
.i
[pi
].eq(pick
)
235 comb
+= fu
.go_rd_i
[idx
].eq(rdpick
.o
[pi
])
237 # connect regfile port to input, creating a Broadcast Bus
238 print ("reg connect widths",
239 regfile
, regname
, pi
, funame
,
240 src
.shape(), rport
.data_o
.shape())
241 comb
+= src
.eq(rport
.data_o
) # all FUs connect to same port
243 def connect_wrports(self
, m
, fu_bitdict
):
244 """connect write ports
246 orders the write regspecs into a dict-of-dicts, by regfile,
247 by regport name, then connects all FUs that want that regport
248 by way of a PriorityPicker.
250 note that the write-port wen, write-port data, and go_wr_i all need to
251 be on the exact same clock cycle. as there is a combinatorial loop bug
252 at the moment, these all use sync.
254 comb
, sync
= m
.d
.comb
, m
.d
.sync
257 # dictionary of lists of regfile write ports
258 byregfiles_wr
, byregfiles_wrspec
= self
.get_byregfiles(False)
260 # same for write ports.
261 # BLECH! complex code-duplication! BLECH!
263 for regfile
, spec
in byregfiles_wr
.items():
264 fuspecs
= byregfiles_wrspec
[regfile
]
265 wrpickers
[regfile
] = {}
266 for (regname
, fspec
) in sort_fuspecs(fuspecs
):
267 print ("connect wr", regname
, fspec
)
269 # get the regfile specs for this regfile port
270 (rf
, read
, write
, wid
, fuspec
) = fspec
272 # select the required write port. these are pre-defined sizes
273 print (regfile
, regs
.rf
.keys())
274 wport
= regs
.rf
[regfile
.lower()].w_ports
[rpidx
]
276 # create a priority picker to manage this port
277 wrpickers
[regfile
][rpidx
] = wrpick
= PriorityPicker(len(fuspec
))
278 setattr(m
.submodules
, "wrpick_%s_%s" % (regfile
, rpidx
), wrpick
)
280 # connect the regspec write "reg select" number to this port
281 # only if one FU actually requests (and is granted) the port
282 # will the write-enable be activated
283 with m
.If(wrpick
.en_o
):
284 comb
+= wport
.wen
.eq(write
)
286 comb
+= wport
.wen
.eq(0)
288 # connect up the FU req/go signals and the reg-read to the FU
289 # these are arbitrated by Data.ok signals
291 for pi
, (funame
, fu
, idx
) in enumerate(fuspec
):
292 # write-request comes from dest.ok
293 dest
= fu
.get_out(idx
)
294 fu_dest_latch
= fu
.get_fu_out(idx
) # latched output
295 name
= "wrflag_%s_%s_%d" % (funame
, regname
, idx
)
296 wrflag
= Signal(name
=name
, reset_less
=True)
297 comb
+= wrflag
.eq(dest
.ok
& fu
.busy_o
)
299 # connect request-read to picker input, and output to go-wr
300 fu_active
= fu_bitdict
[funame
]
301 pick
= fu
.wr
.rel
[idx
] & fu_active
#& wrflag
302 comb
+= wrpick
.i
[pi
].eq(pick
)
303 comb
+= fu
.go_wr_i
[idx
].eq(wrpick
.o
[pi
] & wrpick
.en_o
)
304 # connect regfile port to input
305 print ("reg connect widths",
306 regfile
, regname
, pi
, funame
,
307 dest
.shape(), wport
.data_i
.shape())
308 wsigs
.append(fu_dest_latch
)
310 # here is where we create the Write Broadcast Bus. simple, eh?
311 comb
+= wport
.data_i
.eq(ortreereduce_sig(wsigs
))
313 def get_byregfiles(self
, readmode
):
315 mode
= "read" if readmode
else "write"
320 # dictionary of lists of regfile ports
323 for (funame
, fu
) in fus
.items():
324 print ("%s ports for %s" % (mode
, funame
))
325 for idx
in range(fu
.n_src
if readmode
else fu
.n_dst
):
327 (regfile
, regname
, wid
) = fu
.get_in_spec(idx
)
329 (regfile
, regname
, wid
) = fu
.get_out_spec(idx
)
330 print (" %d %s %s %s" % (idx
, regfile
, regname
, str(wid
)))
332 rdflag
, read
= dec2
.regspecmap_read(regfile
, regname
)
335 rdflag
, read
= None, None
336 wrport
, write
= dec2
.regspecmap_write(regfile
, regname
)
337 if regfile
not in byregfiles
:
338 byregfiles
[regfile
] = {}
339 byregfiles_spec
[regfile
] = {}
340 if regname
not in byregfiles_spec
[regfile
]:
341 byregfiles_spec
[regfile
][regname
] = \
342 [rdflag
, read
, write
, wid
, []]
343 # here we start to create "lanes"
344 if idx
not in byregfiles
[regfile
]:
345 byregfiles
[regfile
][idx
] = []
346 fuspec
= (funame
, fu
, idx
)
347 byregfiles
[regfile
][idx
].append(fuspec
)
348 byregfiles_spec
[regfile
][regname
][4].append(fuspec
)
350 # ok just print that out, for convenience
351 for regfile
, spec
in byregfiles
.items():
352 print ("regfile %s ports:" % mode
, regfile
)
353 fuspecs
= byregfiles_spec
[regfile
]
354 for regname
, fspec
in fuspecs
.items():
355 [rdflag
, read
, write
, wid
, fuspec
] = fspec
356 print (" rf %s port %s lane: %s" % (mode
, regfile
, regname
))
357 print (" %s" % regname
, wid
, read
, write
, rdflag
)
358 for (funame
, fu
, idx
) in fuspec
:
359 fusig
= fu
.src_i
[idx
] if readmode
else fu
.dest
[idx
]
360 print (" ", funame
, fu
, idx
, fusig
)
363 return byregfiles
, byregfiles_spec
366 yield from self
.fus
.ports()
367 yield from self
.pdecode2
.ports()
368 yield from self
.l0
.ports()
375 if __name__
== '__main__':
376 pspec
= TestMemPspec(ldst_ifacetype
='testpi',
381 dut
= NonProductionCore(pspec
)
382 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
383 with
open("test_core.il", "w") as f
: