25eaa0360083d4a05dd84956bf45c6928d47e2f2
3 not in any way intended for production use. this runs a FSM that:
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
10 * does it all over again
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
18 from nmigen
import (Elaboratable
, Module
, Signal
, ClockSignal
, ResetSignal
,
19 ClockDomain
, DomainRenamer
, Mux
, Const
)
20 from nmigen
.cli
import rtlil
21 from nmigen
.cli
import main
24 from soc
.decoder
.power_decoder
import create_pdecode
25 from soc
.decoder
.power_decoder2
import PowerDecode2
, SVP64PrefixDecoder
26 from soc
.decoder
.decode2execute1
import IssuerDecode2ToOperand
27 from soc
.decoder
.decode2execute1
import Data
28 from soc
.experiment
.testmem
import TestMemory
# test only for instructions
29 from soc
.regfile
.regfiles
import StateRegs
, FastRegs
30 from soc
.simple
.core
import NonProductionCore
31 from soc
.config
.test
.test_loadstore
import TestMemPspec
32 from soc
.config
.ifetch
import ConfigFetchUnit
33 from soc
.decoder
.power_enums
import MicrOp
34 from soc
.debug
.dmi
import CoreDebug
, DMIInterface
35 from soc
.debug
.jtag
import JTAG
36 from soc
.config
.pinouts
import get_pinspecs
37 from soc
.config
.state
import CoreState
38 from soc
.interrupts
.xics
import XICS_ICP
, XICS_ICS
39 from soc
.bus
.simple_gpio
import SimpleGPIO
40 from soc
.bus
.SPBlock512W64B8W
import SPBlock512W64B8W
41 from soc
.clock
.select
import ClockSelect
42 from soc
.clock
.dummypll
import DummyPLL
43 from soc
.sv
.svstate
import SVSTATERec
46 from nmutil
.util
import rising_edge
48 def get_insn(f_instr_o
, pc
):
49 if f_instr_o
.width
== 32:
52 # 64-bit: bit 2 of pc decides which word to select
53 return f_instr_o
.word_select(pc
[2], 32)
56 class TestIssuerInternal(Elaboratable
):
57 """TestIssuer - reads instructions from TestMemory and issues them
59 efficiency and speed is not the main goal here: functional correctness is.
61 def __init__(self
, pspec
):
63 # JTAG interface. add this right at the start because if it's
64 # added it *modifies* the pspec, by adding enable/disable signals
65 # for parts of the rest of the core
66 self
.jtag_en
= hasattr(pspec
, "debug") and pspec
.debug
== 'jtag'
68 subset
= {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
70 self
.jtag
= JTAG(get_pinspecs(subset
=subset
))
71 # add signals to pspec to enable/disable icache and dcache
72 # (or data and intstruction wishbone if icache/dcache not included)
73 # https://bugs.libre-soc.org/show_bug.cgi?id=520
74 # TODO: do we actually care if these are not domain-synchronised?
75 # honestly probably not.
76 pspec
.wb_icache_en
= self
.jtag
.wb_icache_en
77 pspec
.wb_dcache_en
= self
.jtag
.wb_dcache_en
78 self
.wb_sram_en
= self
.jtag
.wb_sram_en
80 self
.wb_sram_en
= Const(1)
83 self
.sram4x4k
= (hasattr(pspec
, "sram4x4kblock") and
84 pspec
.sram4x4kblock
== True)
88 self
.sram4k
.append(SPBlock512W64B8W(name
="sram4k_%d" % i
,
91 # add interrupt controller?
92 self
.xics
= hasattr(pspec
, "xics") and pspec
.xics
== True
94 self
.xics_icp
= XICS_ICP()
95 self
.xics_ics
= XICS_ICS()
96 self
.int_level_i
= self
.xics_ics
.int_level_i
98 # add GPIO peripheral?
99 self
.gpio
= hasattr(pspec
, "gpio") and pspec
.gpio
== True
101 self
.simple_gpio
= SimpleGPIO()
102 self
.gpio_o
= self
.simple_gpio
.gpio_o
104 # main instruction core25
105 self
.core
= core
= NonProductionCore(pspec
)
107 # instruction decoder. goes into Trap Record
108 pdecode
= create_pdecode()
109 self
.cur_state
= CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
110 self
.pdecode2
= PowerDecode2(pdecode
, state
=self
.cur_state
,
111 opkls
=IssuerDecode2ToOperand
)
112 self
.svp64
= SVP64PrefixDecoder() # for decoding SVP64 prefix
114 # Test Instruction memory
115 self
.imem
= ConfigFetchUnit(pspec
).fu
116 # one-row cache of instruction read
117 self
.iline
= Signal(64) # one instruction line
118 self
.iprev_adr
= Signal(64) # previous address: if different, do read
121 self
.dbg
= CoreDebug()
123 # instruction go/monitor
124 self
.pc_o
= Signal(64, reset_less
=True)
125 self
.pc_i
= Data(64, "pc_i") # set "ok" to indicate "please change me"
126 self
.svstate_i
= Data(32, "svstate_i") # ditto
127 self
.core_bigendian_i
= Signal()
128 self
.busy_o
= Signal(reset_less
=True)
129 self
.memerr_o
= Signal(reset_less
=True)
131 # STATE regfile read /write ports for PC, MSR, SVSTATE
132 staterf
= self
.core
.regs
.rf
['state']
133 self
.state_r_pc
= staterf
.r_ports
['cia'] # PC rd
134 self
.state_w_pc
= staterf
.w_ports
['d_wr1'] # PC wr
135 self
.state_r_msr
= staterf
.r_ports
['msr'] # MSR rd
136 self
.state_r_sv
= staterf
.r_ports
['sv'] # SVSTATE rd
137 self
.state_w_sv
= staterf
.w_ports
['sv'] # SVSTATE wr
139 # DMI interface access
140 intrf
= self
.core
.regs
.rf
['int']
141 crrf
= self
.core
.regs
.rf
['cr']
142 xerrf
= self
.core
.regs
.rf
['xer']
143 self
.int_r
= intrf
.r_ports
['dmi'] # INT read
144 self
.cr_r
= crrf
.r_ports
['full_cr_dbg'] # CR read
145 self
.xer_r
= xerrf
.r_ports
['full_xer'] # XER read
147 # hack method of keeping an eye on whether branch/trap set the PC
148 self
.state_nia
= self
.core
.regs
.rf
['state'].w_ports
['nia']
149 self
.state_nia
.wen
.name
= 'state_nia_wen'
151 def fetch_fsm(self
, m
, core
, pc
, svstate
, nia
,
152 fetch_pc_ready_o
, fetch_pc_valid_i
,
153 fetch_insn_valid_o
, fetch_insn_ready_i
):
155 this FSM performs fetch of raw instruction data, partial-decodes
156 it 32-bit at a time to detect SVP64 prefixes, and will optionally
157 read a 2nd 32-bit quantity if that occurs.
161 pdecode2
= self
.pdecode2
163 cur_state
= self
.cur_state
164 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
166 msr_read
= Signal(reset
=1)
168 with m
.FSM(name
='fetch_fsm'):
171 with m
.State("IDLE"):
172 comb
+= fetch_pc_ready_o
.eq(1)
173 with m
.If(fetch_pc_valid_i
):
174 # instruction allowed to go: start by reading the PC
175 # capture the PC and also drop it into Insn Memory
176 # we have joined a pair of combinatorial memory
177 # lookups together. this is Generally Bad.
178 comb
+= self
.imem
.a_pc_i
.eq(pc
)
179 comb
+= self
.imem
.a_valid_i
.eq(1)
180 comb
+= self
.imem
.f_valid_i
.eq(1)
181 sync
+= cur_state
.pc
.eq(pc
)
182 sync
+= cur_state
.svstate
.eq(svstate
) # and svstate
184 # initiate read of MSR. arrives one clock later
185 comb
+= self
.state_r_msr
.ren
.eq(1 << StateRegs
.MSR
)
186 sync
+= msr_read
.eq(0)
188 m
.next
= "INSN_READ" # move to "wait for bus" phase
190 # dummy pause to find out why simulation is not keeping up
191 with m
.State("INSN_READ"):
192 # one cycle later, msr/sv read arrives. valid only once.
193 with m
.If(~msr_read
):
194 sync
+= msr_read
.eq(1) # yeah don't read it again
195 sync
+= cur_state
.msr
.eq(self
.state_r_msr
.data_o
)
196 with m
.If(self
.imem
.f_busy_o
): # zzz...
197 # busy: stay in wait-read
198 comb
+= self
.imem
.a_valid_i
.eq(1)
199 comb
+= self
.imem
.f_valid_i
.eq(1)
201 # not busy: instruction fetched
202 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
)
203 # decode the SVP64 prefix, if any
204 comb
+= svp64
.raw_opcode_in
.eq(insn
)
205 comb
+= svp64
.bigendian
.eq(self
.core_bigendian_i
)
206 # pass the decoded prefix (if any) to PowerDecoder2
207 sync
+= pdecode2
.sv_rm
.eq(svp64
.svp64_rm
)
208 # calculate the address of the following instruction
209 insn_size
= Mux(svp64
.is_svp64_mode
, 8, 4)
210 sync
+= nia
.eq(cur_state
.pc
+ insn_size
)
211 with m
.If(~svp64
.is_svp64_mode
):
212 # with no prefix, store the instruction
213 # and hand it directly to the next FSM
214 sync
+= dec_opcode_i
.eq(insn
)
215 m
.next
= "INSN_READY"
217 # fetch the rest of the instruction from memory
218 comb
+= self
.imem
.a_pc_i
.eq(cur_state
.pc
+ 4)
219 comb
+= self
.imem
.a_valid_i
.eq(1)
220 comb
+= self
.imem
.f_valid_i
.eq(1)
221 m
.next
= "INSN_READ2"
223 with m
.State("INSN_READ2"):
224 with m
.If(self
.imem
.f_busy_o
): # zzz...
225 # busy: stay in wait-read
226 comb
+= self
.imem
.a_valid_i
.eq(1)
227 comb
+= self
.imem
.f_valid_i
.eq(1)
229 # not busy: instruction fetched
230 insn
= get_insn(self
.imem
.f_instr_o
, cur_state
.pc
+4)
231 sync
+= dec_opcode_i
.eq(insn
)
232 m
.next
= "INSN_READY"
234 with m
.State("INSN_READY"):
235 # hand over the instruction, to be decoded
236 comb
+= fetch_insn_valid_o
.eq(1)
237 with m
.If(fetch_insn_ready_i
):
240 def issue_fsm(self
, m
, core
, pc_changed
, sv_changed
, nia
,
242 fetch_pc_ready_o
, fetch_pc_valid_i
,
243 fetch_insn_valid_o
, fetch_insn_ready_i
,
244 exec_insn_valid_i
, exec_insn_ready_o
,
245 exec_pc_valid_o
, exec_pc_ready_i
):
248 decode / issue FSM. this interacts with the "fetch" FSM
249 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
250 (outgoing). also interacts with the "execute" FSM
251 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
253 SVP64 RM prefixes have already been set up by the
254 "fetch" phase, so execute is fairly straightforward.
259 pdecode2
= self
.pdecode2
260 cur_state
= self
.cur_state
263 dec_opcode_i
= pdecode2
.dec
.raw_opcode_in
# raw opcode
265 # for updating svstate (things like srcstep etc.)
266 update_svstate
= Signal() # set this (below) if updating
267 new_svstate
= SVSTATERec("new_svstate")
268 comb
+= new_svstate
.eq(cur_state
.svstate
)
270 with m
.FSM(name
="issue_fsm"):
272 # Wait on "core stop" release, at reset
273 with m
.State("WAIT_RESET"):
274 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
275 m
.next
= "INSN_FETCH"
277 comb
+= core
.core_stopped_i
.eq(1)
278 comb
+= dbg
.core_stopped_i
.eq(1)
279 # while stopped, allow updating the PC and SVSTATE
280 with m
.If(self
.pc_i
.ok
):
281 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
282 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
283 sync
+= pc_changed
.eq(1)
284 with m
.If(self
.svstate_i
.ok
):
285 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
286 comb
+= update_svstate
.eq(1)
287 sync
+= sv_changed
.eq(1)
289 # go fetch the instruction at the current PC
290 # at this point, there is no instruction running, that
291 # could inadvertently update the PC.
292 with m
.State("INSN_FETCH"):
293 # TODO: update PC here, before fetch
294 comb
+= fetch_pc_valid_i
.eq(1)
295 with m
.If(fetch_pc_ready_o
):
298 # decode the instruction when it arrives
299 with m
.State("INSN_WAIT"):
300 comb
+= fetch_insn_ready_i
.eq(1)
301 with m
.If(fetch_insn_valid_o
):
302 # decode the instruction
303 sync
+= core
.e
.eq(pdecode2
.e
)
304 sync
+= core
.state
.eq(cur_state
)
305 sync
+= core
.raw_insn_i
.eq(dec_opcode_i
)
306 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
307 # loop into INSN_FETCH if it's a vector instruction
308 # and VL == 0. this because VL==0 is a for-loop
309 # from 0 to 0 i.e. always, always a NOP.
310 cur_vl
= cur_state
.svstate
.vl
311 with m
.If(~pdecode2
.no_out_vec
& (cur_vl
== 0)):
312 # update the PC before fetching the next instruction
313 # since we are in a VL==0 loop, no instruction was
314 # executed that we could be overwriting
315 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
316 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
317 m
.next
= "INSN_FETCH"
319 m
.next
= "INSN_EXECUTE" # move to "execute"
321 with m
.State("INSN_EXECUTE"):
322 comb
+= exec_insn_valid_i
.eq(1)
323 with m
.If(exec_insn_ready_o
):
324 m
.next
= "EXECUTE_WAIT"
326 with m
.State("EXECUTE_WAIT"):
327 # wait on "core stop" release, at instruction end
328 with m
.If(~dbg
.core_stop_o
& ~core_rst
):
329 comb
+= exec_pc_ready_i
.eq(1)
330 with m
.If(exec_pc_valid_o
):
331 # precalculate srcstep+1
332 next_srcstep
= Signal
.like(cur_state
.svstate
.srcstep
)
333 comb
+= next_srcstep
.eq(cur_state
.svstate
.srcstep
+1)
334 # was this the last loop iteration?
336 cur_vl
= cur_state
.svstate
.vl
337 comb
+= is_last
.eq(next_srcstep
== cur_vl
)
339 # if either PC or SVSTATE were changed by the previous
340 # instruction, go directly back to Fetch, without
341 # updating either PC or SVSTATE
342 with m
.If(pc_changed | sv_changed
):
343 m
.next
= "INSN_FETCH"
345 # also return to Fetch, when no output was a vector
346 # (regardless of SRCSTEP and VL), or when the last
347 # instruction was really the last one of the VL loop
348 with m
.Elif(pdecode2
.no_out_vec | is_last
):
349 # before going back to fetch, update the PC state
350 # register with the NIA.
351 # ok here we are not reading the branch unit.
352 # TODO: this just blithely overwrites whatever
353 # pipeline updated the PC
354 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
355 comb
+= self
.state_w_pc
.data_i
.eq(nia
)
356 # reset SRCSTEP before returning to Fetch
357 with m
.If(~pdecode2
.no_out_vec
):
358 comb
+= new_svstate
.srcstep
.eq(0)
359 comb
+= update_svstate
.eq(1)
360 m
.next
= "INSN_FETCH"
362 # returning to Execute? then, first update SRCSTEP
364 comb
+= new_svstate
.srcstep
.eq(next_srcstep
)
365 comb
+= update_svstate
.eq(1)
369 comb
+= core
.core_stopped_i
.eq(1)
370 comb
+= dbg
.core_stopped_i
.eq(1)
371 # while stopped, allow updating the PC and SVSTATE
372 with m
.If(self
.pc_i
.ok
):
373 comb
+= self
.state_w_pc
.wen
.eq(1 << StateRegs
.PC
)
374 comb
+= self
.state_w_pc
.data_i
.eq(self
.pc_i
.data
)
375 sync
+= pc_changed
.eq(1)
376 with m
.If(self
.svstate_i
.ok
):
377 comb
+= new_svstate
.eq(self
.svstate_i
.data
)
378 comb
+= update_svstate
.eq(1)
379 sync
+= sv_changed
.eq(1)
381 # need to decode the instruction again, after updating SRCSTEP
382 # in the previous state.
383 # mostly a copy of INSN_WAIT, but without the actual wait
384 with m
.State("DECODE_SV"):
385 # decode the instruction
386 sync
+= core
.e
.eq(pdecode2
.e
)
387 sync
+= core
.state
.eq(cur_state
)
388 sync
+= core
.bigendian_i
.eq(self
.core_bigendian_i
)
389 m
.next
= "INSN_EXECUTE" # move to "execute"
391 # check if svstate needs updating: if so, write it to State Regfile
392 with m
.If(update_svstate
):
393 comb
+= self
.state_w_sv
.wen
.eq(1<<StateRegs
.SVSTATE
)
394 comb
+= self
.state_w_sv
.data_i
.eq(new_svstate
)
395 sync
+= cur_state
.svstate
.eq(new_svstate
) # for next clock
397 def execute_fsm(self
, m
, core
, insn_done
, pc_changed
, sv_changed
,
398 exec_insn_valid_i
, exec_insn_ready_o
,
399 exec_pc_valid_o
, exec_pc_ready_i
):
402 execute FSM. this interacts with the "issue" FSM
403 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
404 (outgoing). SVP64 RM prefixes have already been set up by the
405 "issue" phase, so execute is fairly straightforward.
410 pdecode2
= self
.pdecode2
414 core_busy_o
= core
.busy_o
# core is busy
415 core_ivalid_i
= core
.ivalid_i
# instruction is valid
416 core_issue_i
= core
.issue_i
# instruction is issued
417 insn_type
= core
.e
.do
.insn_type
# instruction MicroOp type
419 with m
.FSM(name
="exec_fsm"):
421 # waiting for instruction bus (stays there until not busy)
422 with m
.State("INSN_START"):
423 comb
+= exec_insn_ready_o
.eq(1)
424 with m
.If(exec_insn_valid_i
):
425 comb
+= core_ivalid_i
.eq(1) # instruction is valid
426 comb
+= core_issue_i
.eq(1) # and issued
427 sync
+= sv_changed
.eq(0)
428 sync
+= pc_changed
.eq(0)
429 m
.next
= "INSN_ACTIVE" # move to "wait completion"
431 # instruction started: must wait till it finishes
432 with m
.State("INSN_ACTIVE"):
433 with m
.If(insn_type
!= MicrOp
.OP_NOP
):
434 comb
+= core_ivalid_i
.eq(1) # instruction is valid
435 # note changes to PC and SVSTATE
436 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.SVSTATE
)):
437 sync
+= sv_changed
.eq(1)
438 with m
.If(self
.state_nia
.wen
& (1<<StateRegs
.PC
)):
439 sync
+= pc_changed
.eq(1)
440 with m
.If(~core_busy_o
): # instruction done!
441 comb
+= insn_done
.eq(1)
442 comb
+= exec_pc_valid_o
.eq(1)
443 with m
.If(exec_pc_ready_i
):
444 m
.next
= "INSN_START" # back to fetch
446 def elaborate(self
, platform
):
448 comb
, sync
= m
.d
.comb
, m
.d
.sync
450 m
.submodules
.core
= core
= DomainRenamer("coresync")(self
.core
)
451 m
.submodules
.imem
= imem
= self
.imem
452 m
.submodules
.dbg
= dbg
= self
.dbg
454 m
.submodules
.jtag
= jtag
= self
.jtag
455 # TODO: UART2GDB mux, here, from external pin
456 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
457 sync
+= dbg
.dmi
.connect_to(jtag
.dmi
)
459 cur_state
= self
.cur_state
461 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
463 for i
, sram
in enumerate(self
.sram4k
):
464 m
.submodules
["sram4k_%d" % i
] = sram
465 comb
+= sram
.enable
.eq(self
.wb_sram_en
)
467 # XICS interrupt handler
469 m
.submodules
.xics_icp
= icp
= self
.xics_icp
470 m
.submodules
.xics_ics
= ics
= self
.xics_ics
471 comb
+= icp
.ics_i
.eq(ics
.icp_o
) # connect ICS to ICP
472 sync
+= cur_state
.eint
.eq(icp
.core_irq_o
) # connect ICP to core
474 # GPIO test peripheral
476 m
.submodules
.simple_gpio
= simple_gpio
= self
.simple_gpio
478 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
479 # XXX causes litex ECP5 test to get wrong idea about input and output
480 # (but works with verilator sim *sigh*)
481 #if self.gpio and self.xics:
482 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
484 # instruction decoder
485 pdecode
= create_pdecode()
486 m
.submodules
.dec2
= pdecode2
= self
.pdecode2
487 m
.submodules
.svp64
= svp64
= self
.svp64
490 dmi
, d_reg
, d_cr
, d_xer
, = dbg
.dmi
, dbg
.d_gpr
, dbg
.d_cr
, dbg
.d_xer
491 intrf
= self
.core
.regs
.rf
['int']
493 # clock delay power-on reset
494 cd_por
= ClockDomain(reset_less
=True)
495 cd_sync
= ClockDomain()
496 core_sync
= ClockDomain("coresync")
497 m
.domains
+= cd_por
, cd_sync
, core_sync
499 ti_rst
= Signal(reset_less
=True)
500 delay
= Signal(range(4), reset
=3)
501 with m
.If(delay
!= 0):
502 m
.d
.por
+= delay
.eq(delay
- 1)
503 comb
+= cd_por
.clk
.eq(ClockSignal())
505 # power-on reset delay
506 core_rst
= ResetSignal("coresync")
507 comb
+= ti_rst
.eq(delay
!= 0 | dbg
.core_rst_o |
ResetSignal())
508 comb
+= core_rst
.eq(ti_rst
)
510 # busy/halted signals from core
511 comb
+= self
.busy_o
.eq(core
.busy_o
)
512 comb
+= pdecode2
.dec
.bigendian
.eq(self
.core_bigendian_i
)
514 # temporary hack: says "go" immediately for both address gen and ST
516 ldst
= core
.fus
.fus
['ldst0']
517 st_go_edge
= rising_edge(m
, ldst
.st
.rel_o
)
518 m
.d
.comb
+= ldst
.ad
.go_i
.eq(ldst
.ad
.rel_o
) # link addr-go direct to rel
519 m
.d
.comb
+= ldst
.st
.go_i
.eq(st_go_edge
) # link store-go to rising rel
521 # PC and instruction from I-Memory
522 comb
+= self
.pc_o
.eq(cur_state
.pc
)
523 pc_changed
= Signal() # note write to PC
524 sv_changed
= Signal() # note write to SVSTATE
525 insn_done
= Signal() # fires just once
528 pc
= Signal(64, reset_less
=True)
529 pc_ok_delay
= Signal()
530 sync
+= pc_ok_delay
.eq(~self
.pc_i
.ok
)
531 with m
.If(self
.pc_i
.ok
):
532 # incoming override (start from pc_i)
533 comb
+= pc
.eq(self
.pc_i
.data
)
535 # otherwise read StateRegs regfile for PC...
536 comb
+= self
.state_r_pc
.ren
.eq(1<<StateRegs
.PC
)
537 # ... but on a 1-clock delay
538 with m
.If(pc_ok_delay
):
539 comb
+= pc
.eq(self
.state_r_pc
.data_o
)
542 svstate
= Signal(64, reset_less
=True)
543 svstate_ok_delay
= Signal()
544 sync
+= svstate_ok_delay
.eq(~self
.svstate_i
.ok
)
545 with m
.If(self
.svstate_i
.ok
):
546 # incoming override (start from svstate__i)
547 comb
+= svstate
.eq(self
.svstate_i
.data
)
549 # otherwise read StateRegs regfile for SVSTATE...
550 comb
+= self
.state_r_sv
.ren
.eq(1 << StateRegs
.SVSTATE
)
551 # ... but on a 1-clock delay
552 with m
.If(svstate_ok_delay
):
553 comb
+= svstate
.eq(self
.state_r_sv
.data_o
)
555 # don't write pc every cycle
556 comb
+= self
.state_w_pc
.wen
.eq(0)
557 comb
+= self
.state_w_pc
.data_i
.eq(0)
559 # don't read msr every cycle
560 comb
+= self
.state_r_msr
.ren
.eq(0)
562 # address of the next instruction, in the absence of a branch
563 # depends on the instruction size
564 nia
= Signal(64, reset_less
=True)
566 # connect up debug signals
567 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
568 comb
+= dbg
.terminate_i
.eq(core
.core_terminate_o
)
569 comb
+= dbg
.state
.pc
.eq(pc
)
570 comb
+= dbg
.state
.svstate
.eq(svstate
)
571 comb
+= dbg
.state
.msr
.eq(cur_state
.msr
)
573 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
574 # these are the handshake signals between fetch and decode/execute
576 # fetch FSM can run as soon as the PC is valid
577 fetch_pc_valid_i
= Signal() # Execute tells Fetch "start next read"
578 fetch_pc_ready_o
= Signal() # Fetch Tells SVSTATE "proceed"
580 # fetch FSM hands over the instruction to be decoded / issued
581 fetch_insn_valid_o
= Signal()
582 fetch_insn_ready_i
= Signal()
584 # issue FSM delivers the instruction to the be executed
585 exec_insn_valid_i
= Signal()
586 exec_insn_ready_o
= Signal()
588 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
589 exec_pc_valid_o
= Signal()
590 exec_pc_ready_i
= Signal()
592 # the FSMs here are perhaps unusual in that they detect conditions
593 # then "hold" information, combinatorially, for the core
594 # (as opposed to using sync - which would be on a clock's delay)
595 # this includes the actual opcode, valid flags and so on.
597 # Fetch, then Issue, then Execute. Issue is where the VL for-loop
598 # lives. the ready/valid signalling is used to communicate between
601 self
.fetch_fsm(m
, core
, pc
, svstate
, nia
,
602 fetch_pc_ready_o
, fetch_pc_valid_i
,
603 fetch_insn_valid_o
, fetch_insn_ready_i
)
605 self
.issue_fsm(m
, core
, pc_changed
, sv_changed
, nia
,
607 fetch_pc_ready_o
, fetch_pc_valid_i
,
608 fetch_insn_valid_o
, fetch_insn_ready_i
,
609 exec_insn_valid_i
, exec_insn_ready_o
,
610 exec_pc_ready_i
, exec_pc_valid_o
)
612 self
.execute_fsm(m
, core
, insn_done
, pc_changed
, sv_changed
,
613 exec_insn_valid_i
, exec_insn_ready_o
,
614 exec_pc_ready_i
, exec_pc_valid_o
)
616 # this bit doesn't have to be in the FSM: connect up to read
617 # regfiles on demand from DMI
618 with m
.If(d_reg
.req
): # request for regfile access being made
619 # TODO: error-check this
620 # XXX should this be combinatorial? sync better?
622 comb
+= self
.int_r
.ren
.eq(1<<d_reg
.addr
)
624 comb
+= self
.int_r
.addr
.eq(d_reg
.addr
)
625 comb
+= self
.int_r
.ren
.eq(1)
626 d_reg_delay
= Signal()
627 sync
+= d_reg_delay
.eq(d_reg
.req
)
628 with m
.If(d_reg_delay
):
629 # data arrives one clock later
630 comb
+= d_reg
.data
.eq(self
.int_r
.data_o
)
631 comb
+= d_reg
.ack
.eq(1)
633 # sigh same thing for CR debug
634 with m
.If(d_cr
.req
): # request for regfile access being made
635 comb
+= self
.cr_r
.ren
.eq(0b11111111) # enable all
636 d_cr_delay
= Signal()
637 sync
+= d_cr_delay
.eq(d_cr
.req
)
638 with m
.If(d_cr_delay
):
639 # data arrives one clock later
640 comb
+= d_cr
.data
.eq(self
.cr_r
.data_o
)
641 comb
+= d_cr
.ack
.eq(1)
644 with m
.If(d_xer
.req
): # request for regfile access being made
645 comb
+= self
.xer_r
.ren
.eq(0b111111) # enable all
646 d_xer_delay
= Signal()
647 sync
+= d_xer_delay
.eq(d_xer
.req
)
648 with m
.If(d_xer_delay
):
649 # data arrives one clock later
650 comb
+= d_xer
.data
.eq(self
.xer_r
.data_o
)
651 comb
+= d_xer
.ack
.eq(1)
653 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
654 # (which uses that in PowerDecoder2 to raise 0x900 exception)
655 self
.tb_dec_fsm(m
, cur_state
.dec
)
659 def tb_dec_fsm(self
, m
, spr_dec
):
662 this is a FSM for updating either dec or tb. it runs alternately
663 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
664 value to DEC, however the regfile has "passthrough" on it so this
667 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
670 comb
, sync
= m
.d
.comb
, m
.d
.sync
671 fast_rf
= self
.core
.regs
.rf
['fast']
672 fast_r_dectb
= fast_rf
.r_ports
['issue'] # DEC/TB
673 fast_w_dectb
= fast_rf
.w_ports
['issue'] # DEC/TB
677 # initiates read of current DEC
678 with m
.State("DEC_READ"):
679 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.DEC
)
680 comb
+= fast_r_dectb
.ren
.eq(1)
683 # waits for DEC read to arrive (1 cycle), updates with new value
684 with m
.State("DEC_WRITE"):
686 # TODO: MSR.LPCR 32-bit decrement mode
687 comb
+= new_dec
.eq(fast_r_dectb
.data_o
- 1)
688 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.DEC
)
689 comb
+= fast_w_dectb
.wen
.eq(1)
690 comb
+= fast_w_dectb
.data_i
.eq(new_dec
)
691 sync
+= spr_dec
.eq(new_dec
) # copy into cur_state for decoder
694 # initiates read of current TB
695 with m
.State("TB_READ"):
696 comb
+= fast_r_dectb
.addr
.eq(FastRegs
.TB
)
697 comb
+= fast_r_dectb
.ren
.eq(1)
700 # waits for read TB to arrive, initiates write of current TB
701 with m
.State("TB_WRITE"):
703 comb
+= new_tb
.eq(fast_r_dectb
.data_o
+ 1)
704 comb
+= fast_w_dectb
.addr
.eq(FastRegs
.TB
)
705 comb
+= fast_w_dectb
.wen
.eq(1)
706 comb
+= fast_w_dectb
.data_i
.eq(new_tb
)
712 yield from self
.pc_i
.ports()
715 yield from self
.core
.ports()
716 yield from self
.imem
.ports()
717 yield self
.core_bigendian_i
723 def external_ports(self
):
724 ports
= self
.pc_i
.ports()
725 ports
+= [self
.pc_o
, self
.memerr_o
, self
.core_bigendian_i
, self
.busy_o
,
729 ports
+= list(self
.jtag
.external_ports())
731 # don't add DMI if JTAG is enabled
732 ports
+= list(self
.dbg
.dmi
.ports())
734 ports
+= list(self
.imem
.ibus
.fields
.values())
735 ports
+= list(self
.core
.l0
.cmpi
.lsmem
.lsi
.slavebus
.fields
.values())
738 for sram
in self
.sram4k
:
739 ports
+= list(sram
.bus
.fields
.values())
742 ports
+= list(self
.xics_icp
.bus
.fields
.values())
743 ports
+= list(self
.xics_ics
.bus
.fields
.values())
744 ports
.append(self
.int_level_i
)
747 ports
+= list(self
.simple_gpio
.bus
.fields
.values())
748 ports
.append(self
.gpio_o
)
756 class TestIssuer(Elaboratable
):
757 def __init__(self
, pspec
):
758 self
.ti
= TestIssuerInternal(pspec
)
760 self
.pll
= DummyPLL()
762 # PLL direct clock or not
763 self
.pll_en
= hasattr(pspec
, "use_pll") and pspec
.use_pll
765 self
.pll_18_o
= Signal(reset_less
=True)
767 def elaborate(self
, platform
):
771 # TestIssuer runs at direct clock
772 m
.submodules
.ti
= ti
= self
.ti
773 cd_int
= ClockDomain("coresync")
776 # ClockSelect runs at PLL output internal clock rate
777 m
.submodules
.pll
= pll
= self
.pll
779 # add clock domains from PLL
780 cd_pll
= ClockDomain("pllclk")
783 # PLL clock established. has the side-effect of running clklsel
784 # at the PLL's speed (see DomainRenamer("pllclk") above)
785 pllclk
= ClockSignal("pllclk")
786 comb
+= pllclk
.eq(pll
.clk_pll_o
)
788 # wire up external 24mhz to PLL
789 comb
+= pll
.clk_24_i
.eq(ClockSignal())
791 # output 18 mhz PLL test signal
792 comb
+= self
.pll_18_o
.eq(pll
.pll_18_o
)
794 # now wire up ResetSignals. don't mind them being in this domain
795 pll_rst
= ResetSignal("pllclk")
796 comb
+= pll_rst
.eq(ResetSignal())
798 # internal clock is set to selector clock-out. has the side-effect of
799 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
800 intclk
= ClockSignal("coresync")
802 comb
+= intclk
.eq(pll
.clk_pll_o
)
804 comb
+= intclk
.eq(ClockSignal())
809 return list(self
.ti
.ports()) + list(self
.pll
.ports()) + \
810 [ClockSignal(), ResetSignal()]
812 def external_ports(self
):
813 ports
= self
.ti
.external_ports()
814 ports
.append(ClockSignal())
815 ports
.append(ResetSignal())
817 ports
.append(self
.pll
.clk_sel_i
)
818 ports
.append(self
.pll_18_o
)
819 ports
.append(self
.pll
.pll_lck_o
)
823 if __name__
== '__main__':
824 units
= {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
830 pspec
= TestMemPspec(ldst_ifacetype
='bare_wb',
831 imem_ifacetype
='bare_wb',
836 dut
= TestIssuer(pspec
)
837 vl
= main(dut
, ports
=dut
.ports(), name
="test_issuer")
839 if len(sys
.argv
) == 1:
840 vl
= rtlil
.convert(dut
, ports
=dut
.external_ports(), name
="test_issuer")
841 with
open("test_issuer.il", "w") as f
: