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[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const, Repl, Cat)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from nmigen.lib.coding import PriorityEncoder
25
26 from openpower.decoder.power_decoder import create_pdecode
27 from openpower.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
28 from openpower.decoder.decode2execute1 import IssuerDecode2ToOperand
29 from openpower.decoder.decode2execute1 import Data
30 from openpower.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
31 SVP64PredMode)
32 from openpower.state import CoreState
33 from openpower.consts import (CR, SVP64CROffs)
34 from soc.experiment.testmem import TestMemory # test only for instructions
35 from soc.regfile.regfiles import StateRegs, FastRegs
36 from soc.simple.core import NonProductionCore
37 from soc.config.test.test_loadstore import TestMemPspec
38 from soc.config.ifetch import ConfigFetchUnit
39 from soc.debug.dmi import CoreDebug, DMIInterface
40 from soc.debug.jtag import JTAG
41 from soc.config.pinouts import get_pinspecs
42 from soc.interrupts.xics import XICS_ICP, XICS_ICS
43 from soc.bus.simple_gpio import SimpleGPIO
44 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
45 from soc.clock.select import ClockSelect
46 from soc.clock.dummypll import DummyPLL
47 from openpower.sv.svstate import SVSTATERec
48
49
50 from nmutil.util import rising_edge
51
52 def get_insn(f_instr_o, pc):
53 if f_instr_o.width == 32:
54 return f_instr_o
55 else:
56 # 64-bit: bit 2 of pc decides which word to select
57 return f_instr_o.word_select(pc[2], 32)
58
59 # gets state input or reads from state regfile
60 def state_get(m, core_rst, state_i, name, regfile, regnum):
61 comb = m.d.comb
62 sync = m.d.sync
63 # read the PC
64 res = Signal(64, reset_less=True, name=name)
65 res_ok_delay = Signal(name="%s_ok_delay" % name)
66 with m.If(~core_rst):
67 sync += res_ok_delay.eq(~state_i.ok)
68 with m.If(state_i.ok):
69 # incoming override (start from pc_i)
70 comb += res.eq(state_i.data)
71 with m.Else():
72 # otherwise read StateRegs regfile for PC...
73 comb += regfile.ren.eq(1<<regnum)
74 # ... but on a 1-clock delay
75 with m.If(res_ok_delay):
76 comb += res.eq(regfile.data_o)
77 return res
78
79 def get_predint(m, mask, name):
80 """decode SVP64 predicate integer mask field to reg number and invert
81 this is identical to the equivalent function in ISACaller except that
82 it doesn't read the INT directly, it just decodes "what needs to be done"
83 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
84
85 * all1s is set to indicate that no mask is to be applied.
86 * regread indicates the GPR register number to be read
87 * invert is set to indicate that the register value is to be inverted
88 * unary indicates that the contents of the register is to be shifted 1<<r3
89 """
90 comb = m.d.comb
91 regread = Signal(5, name=name+"regread")
92 invert = Signal(name=name+"invert")
93 unary = Signal(name=name+"unary")
94 all1s = Signal(name=name+"all1s")
95 with m.Switch(mask):
96 with m.Case(SVP64PredInt.ALWAYS.value):
97 comb += all1s.eq(1) # use 0b1111 (all ones)
98 with m.Case(SVP64PredInt.R3_UNARY.value):
99 comb += regread.eq(3)
100 comb += unary.eq(1) # 1<<r3 - shift r3 (single bit)
101 with m.Case(SVP64PredInt.R3.value):
102 comb += regread.eq(3)
103 with m.Case(SVP64PredInt.R3_N.value):
104 comb += regread.eq(3)
105 comb += invert.eq(1)
106 with m.Case(SVP64PredInt.R10.value):
107 comb += regread.eq(10)
108 with m.Case(SVP64PredInt.R10_N.value):
109 comb += regread.eq(10)
110 comb += invert.eq(1)
111 with m.Case(SVP64PredInt.R30.value):
112 comb += regread.eq(30)
113 with m.Case(SVP64PredInt.R30_N.value):
114 comb += regread.eq(30)
115 comb += invert.eq(1)
116 return regread, invert, unary, all1s
117
118 def get_predcr(m, mask, name):
119 """decode SVP64 predicate CR to reg number field and invert status
120 this is identical to _get_predcr in ISACaller
121 """
122 comb = m.d.comb
123 idx = Signal(2, name=name+"idx")
124 invert = Signal(name=name+"crinvert")
125 with m.Switch(mask):
126 with m.Case(SVP64PredCR.LT.value):
127 comb += idx.eq(CR.LT)
128 comb += invert.eq(0)
129 with m.Case(SVP64PredCR.GE.value):
130 comb += idx.eq(CR.LT)
131 comb += invert.eq(1)
132 with m.Case(SVP64PredCR.GT.value):
133 comb += idx.eq(CR.GT)
134 comb += invert.eq(0)
135 with m.Case(SVP64PredCR.LE.value):
136 comb += idx.eq(CR.GT)
137 comb += invert.eq(1)
138 with m.Case(SVP64PredCR.EQ.value):
139 comb += idx.eq(CR.EQ)
140 comb += invert.eq(0)
141 with m.Case(SVP64PredCR.NE.value):
142 comb += idx.eq(CR.EQ)
143 comb += invert.eq(1)
144 with m.Case(SVP64PredCR.SO.value):
145 comb += idx.eq(CR.SO)
146 comb += invert.eq(0)
147 with m.Case(SVP64PredCR.NS.value):
148 comb += idx.eq(CR.SO)
149 comb += invert.eq(1)
150 return idx, invert
151
152
153 class TestIssuerInternal(Elaboratable):
154 """TestIssuer - reads instructions from TestMemory and issues them
155
156 efficiency and speed is not the main goal here: functional correctness
157 and code clarity is. optimisations (which almost 100% interfere with
158 easy understanding) come later.
159 """
160 def __init__(self, pspec):
161
162 # test is SVP64 is to be enabled
163 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
164
165 # and if regfiles are reduced
166 self.regreduce_en = (hasattr(pspec, "regreduce") and
167 (pspec.regreduce == True))
168
169 # JTAG interface. add this right at the start because if it's
170 # added it *modifies* the pspec, by adding enable/disable signals
171 # for parts of the rest of the core
172 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
173 if self.jtag_en:
174 # XXX MUST keep this up-to-date with litex, and
175 # soc-cocotb-sim, and err.. all needs sorting out, argh
176 subset = ['uart',
177 'mtwi',
178 'eint', 'gpio', 'mspi0',
179 # 'mspi1', - disabled for now
180 # 'pwm', 'sd0', - disabled for now
181 'sdr']
182 self.jtag = JTAG(get_pinspecs(subset=subset))
183 # add signals to pspec to enable/disable icache and dcache
184 # (or data and intstruction wishbone if icache/dcache not included)
185 # https://bugs.libre-soc.org/show_bug.cgi?id=520
186 # TODO: do we actually care if these are not domain-synchronised?
187 # honestly probably not.
188 pspec.wb_icache_en = self.jtag.wb_icache_en
189 pspec.wb_dcache_en = self.jtag.wb_dcache_en
190 self.wb_sram_en = self.jtag.wb_sram_en
191 else:
192 self.wb_sram_en = Const(1)
193
194 # add 4k sram blocks?
195 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
196 pspec.sram4x4kblock == True)
197 if self.sram4x4k:
198 self.sram4k = []
199 for i in range(4):
200 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
201 features={'err'}))
202
203 # add interrupt controller?
204 self.xics = hasattr(pspec, "xics") and pspec.xics == True
205 if self.xics:
206 self.xics_icp = XICS_ICP()
207 self.xics_ics = XICS_ICS()
208 self.int_level_i = self.xics_ics.int_level_i
209
210 # add GPIO peripheral?
211 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
212 if self.gpio:
213 self.simple_gpio = SimpleGPIO()
214 self.gpio_o = self.simple_gpio.gpio_o
215
216 # main instruction core. suitable for prototyping / demo only
217 self.core = core = NonProductionCore(pspec)
218
219 # instruction decoder. goes into Trap Record
220 pdecode = create_pdecode()
221 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
222 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
223 opkls=IssuerDecode2ToOperand,
224 svp64_en=self.svp64_en,
225 regreduce_en=self.regreduce_en)
226 if self.svp64_en:
227 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
228
229 # Test Instruction memory
230 self.imem = ConfigFetchUnit(pspec).fu
231
232 # DMI interface
233 self.dbg = CoreDebug()
234
235 # instruction go/monitor
236 self.pc_o = Signal(64, reset_less=True)
237 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
238 self.svstate_i = Data(32, "svstate_i") # ditto
239 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
240 self.busy_o = Signal(reset_less=True)
241 self.memerr_o = Signal(reset_less=True)
242
243 # STATE regfile read /write ports for PC, MSR, SVSTATE
244 staterf = self.core.regs.rf['state']
245 self.state_r_pc = staterf.r_ports['cia'] # PC rd
246 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
247 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
248 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
249 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
250
251 # DMI interface access
252 intrf = self.core.regs.rf['int']
253 crrf = self.core.regs.rf['cr']
254 xerrf = self.core.regs.rf['xer']
255 self.int_r = intrf.r_ports['dmi'] # INT read
256 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
257 self.xer_r = xerrf.r_ports['full_xer'] # XER read
258
259 if self.svp64_en:
260 # for predication
261 self.int_pred = intrf.r_ports['pred'] # INT predicate read
262 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
263
264 # hack method of keeping an eye on whether branch/trap set the PC
265 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
266 self.state_nia.wen.name = 'state_nia_wen'
267
268 # pulse to synchronize the simulator at instruction end
269 self.insn_done = Signal()
270
271 if self.svp64_en:
272 # store copies of predicate masks
273 self.srcmask = Signal(64)
274 self.dstmask = Signal(64)
275
276 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
277 fetch_pc_ready_o, fetch_pc_valid_i,
278 fetch_insn_valid_o, fetch_insn_ready_i):
279 """fetch FSM
280
281 this FSM performs fetch of raw instruction data, partial-decodes
282 it 32-bit at a time to detect SVP64 prefixes, and will optionally
283 read a 2nd 32-bit quantity if that occurs.
284 """
285 comb = m.d.comb
286 sync = m.d.sync
287 pdecode2 = self.pdecode2
288 cur_state = self.cur_state
289 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
290
291 msr_read = Signal(reset=1)
292
293 with m.FSM(name='fetch_fsm'):
294
295 # waiting (zzz)
296 with m.State("IDLE"):
297 comb += fetch_pc_ready_o.eq(1)
298 with m.If(fetch_pc_valid_i):
299 # instruction allowed to go: start by reading the PC
300 # capture the PC and also drop it into Insn Memory
301 # we have joined a pair of combinatorial memory
302 # lookups together. this is Generally Bad.
303 comb += self.imem.a_pc_i.eq(pc)
304 comb += self.imem.a_valid_i.eq(1)
305 comb += self.imem.f_valid_i.eq(1)
306 sync += cur_state.pc.eq(pc)
307 sync += cur_state.svstate.eq(svstate) # and svstate
308
309 # initiate read of MSR. arrives one clock later
310 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
311 sync += msr_read.eq(0)
312
313 m.next = "INSN_READ" # move to "wait for bus" phase
314
315 # dummy pause to find out why simulation is not keeping up
316 with m.State("INSN_READ"):
317 # one cycle later, msr/sv read arrives. valid only once.
318 with m.If(~msr_read):
319 sync += msr_read.eq(1) # yeah don't read it again
320 sync += cur_state.msr.eq(self.state_r_msr.data_o)
321 with m.If(self.imem.f_busy_o): # zzz...
322 # busy: stay in wait-read
323 comb += self.imem.a_valid_i.eq(1)
324 comb += self.imem.f_valid_i.eq(1)
325 with m.Else():
326 # not busy: instruction fetched
327 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
328 if self.svp64_en:
329 svp64 = self.svp64
330 # decode the SVP64 prefix, if any
331 comb += svp64.raw_opcode_in.eq(insn)
332 comb += svp64.bigendian.eq(self.core_bigendian_i)
333 # pass the decoded prefix (if any) to PowerDecoder2
334 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
335 # remember whether this is a prefixed instruction, so
336 # the FSM can readily loop when VL==0
337 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
338 # calculate the address of the following instruction
339 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
340 sync += nia.eq(cur_state.pc + insn_size)
341 with m.If(~svp64.is_svp64_mode):
342 # with no prefix, store the instruction
343 # and hand it directly to the next FSM
344 sync += dec_opcode_i.eq(insn)
345 m.next = "INSN_READY"
346 with m.Else():
347 # fetch the rest of the instruction from memory
348 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
349 comb += self.imem.a_valid_i.eq(1)
350 comb += self.imem.f_valid_i.eq(1)
351 m.next = "INSN_READ2"
352 else:
353 # not SVP64 - 32-bit only
354 sync += nia.eq(cur_state.pc + 4)
355 sync += dec_opcode_i.eq(insn)
356 m.next = "INSN_READY"
357
358 with m.State("INSN_READ2"):
359 with m.If(self.imem.f_busy_o): # zzz...
360 # busy: stay in wait-read
361 comb += self.imem.a_valid_i.eq(1)
362 comb += self.imem.f_valid_i.eq(1)
363 with m.Else():
364 # not busy: instruction fetched
365 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
366 sync += dec_opcode_i.eq(insn)
367 m.next = "INSN_READY"
368 # TODO: probably can start looking at pdecode2.rm_dec
369 # here or maybe even in INSN_READ state, if svp64_mode
370 # detected, in order to trigger - and wait for - the
371 # predicate reading.
372 if self.svp64_en:
373 pmode = pdecode2.rm_dec.predmode
374 """
375 if pmode != SVP64PredMode.ALWAYS.value:
376 fire predicate loading FSM and wait before
377 moving to INSN_READY
378 else:
379 sync += self.srcmask.eq(-1) # set to all 1s
380 sync += self.dstmask.eq(-1) # set to all 1s
381 m.next = "INSN_READY"
382 """
383
384 with m.State("INSN_READY"):
385 # hand over the instruction, to be decoded
386 comb += fetch_insn_valid_o.eq(1)
387 with m.If(fetch_insn_ready_i):
388 m.next = "IDLE"
389
390 def fetch_predicate_fsm(self, m,
391 pred_insn_valid_i, pred_insn_ready_o,
392 pred_mask_valid_o, pred_mask_ready_i):
393 """fetch_predicate_fsm - obtains (constructs in the case of CR)
394 src/dest predicate masks
395
396 https://bugs.libre-soc.org/show_bug.cgi?id=617
397 the predicates can be read here, by using IntRegs r_ports['pred']
398 or CRRegs r_ports['pred']. in the case of CRs it will have to
399 be done through multiple reads, extracting one relevant at a time.
400 later, a faster way would be to use the 32-bit-wide CR port but
401 this is more complex decoding, here. equivalent code used in
402 ISACaller is "from openpower.decoder.isa.caller import get_predcr"
403
404 note: this ENTIRE FSM is not to be called when svp64 is disabled
405 """
406 comb = m.d.comb
407 sync = m.d.sync
408 pdecode2 = self.pdecode2
409 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
410 predmode = rm_dec.predmode
411 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
412 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
413 # get src/dst step, so we can skip already used mask bits
414 cur_state = self.cur_state
415 srcstep = cur_state.svstate.srcstep
416 dststep = cur_state.svstate.dststep
417 cur_vl = cur_state.svstate.vl
418
419 # decode predicates
420 sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
421 dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
422 sidx, scrinvert = get_predcr(m, srcpred, 's')
423 didx, dcrinvert = get_predcr(m, dstpred, 'd')
424
425 with m.FSM(name="fetch_predicate"):
426
427 with m.State("FETCH_PRED_IDLE"):
428 comb += pred_insn_ready_o.eq(1)
429 with m.If(pred_insn_valid_i):
430 with m.If(predmode == SVP64PredMode.INT):
431 # skip fetching destination mask register, when zero
432 with m.If(dall1s):
433 sync += self.dstmask.eq(-1)
434 # directly go to fetch source mask register
435 # guaranteed not to be zero (otherwise predmode
436 # would be SVP64PredMode.ALWAYS, not INT)
437 comb += int_pred.addr.eq(sregread)
438 comb += int_pred.ren.eq(1)
439 m.next = "INT_SRC_READ"
440 # fetch destination predicate register
441 with m.Else():
442 comb += int_pred.addr.eq(dregread)
443 comb += int_pred.ren.eq(1)
444 m.next = "INT_DST_READ"
445 with m.Elif(predmode == SVP64PredMode.CR):
446 # go fetch masks from the CR register file
447 sync += self.srcmask.eq(0)
448 sync += self.dstmask.eq(0)
449 m.next = "CR_READ"
450 with m.Else():
451 sync += self.srcmask.eq(-1)
452 sync += self.dstmask.eq(-1)
453 m.next = "FETCH_PRED_DONE"
454
455 with m.State("INT_DST_READ"):
456 # store destination mask
457 inv = Repl(dinvert, 64)
458 new_dstmask = Signal(64)
459 with m.If(dunary):
460 # set selected mask bit for 1<<r3 mode
461 dst_shift = Signal(range(64))
462 comb += dst_shift.eq(self.int_pred.data_o & 0b111111)
463 comb += new_dstmask.eq(1 << dst_shift)
464 with m.Else():
465 # invert mask if requested
466 comb += new_dstmask.eq(self.int_pred.data_o ^ inv)
467 # shift-out already used mask bits
468 sync += self.dstmask.eq(new_dstmask >> dststep)
469 # skip fetching source mask register, when zero
470 with m.If(sall1s):
471 sync += self.srcmask.eq(-1)
472 m.next = "FETCH_PRED_DONE"
473 # fetch source predicate register
474 with m.Else():
475 comb += int_pred.addr.eq(sregread)
476 comb += int_pred.ren.eq(1)
477 m.next = "INT_SRC_READ"
478
479 with m.State("INT_SRC_READ"):
480 # store source mask
481 inv = Repl(sinvert, 64)
482 new_srcmask = Signal(64)
483 with m.If(sunary):
484 # set selected mask bit for 1<<r3 mode
485 src_shift = Signal(range(64))
486 comb += src_shift.eq(self.int_pred.data_o & 0b111111)
487 comb += new_srcmask.eq(1 << src_shift)
488 with m.Else():
489 # invert mask if requested
490 comb += new_srcmask.eq(self.int_pred.data_o ^ inv)
491 # shift-out already used mask bits
492 sync += self.srcmask.eq(new_srcmask >> srcstep)
493 m.next = "FETCH_PRED_DONE"
494
495 # fetch masks from the CR register file
496 # implements the following loop:
497 # idx, inv = get_predcr(mask)
498 # mask = 0
499 # for cr_idx in range(vl):
500 # cr = crl[cr_idx + SVP64CROffs.CRPred] # takes one cycle
501 # if cr[idx] ^ inv:
502 # mask |= 1 << cr_idx
503 # return mask
504 with m.State("CR_READ"):
505 # CR index to be read, which will be ready by the next cycle
506 cr_idx = Signal.like(cur_vl, reset_less=True)
507 # submit the read operation to the regfile
508 with m.If(cr_idx != cur_vl):
509 # the CR read port is unary ...
510 # ren = 1 << cr_idx
511 # ... in MSB0 convention ...
512 # ren = 1 << (7 - cr_idx)
513 # ... and with an offset:
514 # ren = 1 << (7 - off - cr_idx)
515 idx = SVP64CROffs.CRPred + cr_idx
516 comb += cr_pred.ren.eq(1 << (7 - idx))
517 # signal data valid in the next cycle
518 cr_read = Signal(reset_less=True)
519 sync += cr_read.eq(1)
520 # load the next index
521 sync += cr_idx.eq(cr_idx + 1)
522 with m.Else():
523 # exit on loop end
524 sync += cr_read.eq(0)
525 sync += cr_idx.eq(0)
526 m.next = "FETCH_PRED_DONE"
527 with m.If(cr_read):
528 # compensate for the one cycle delay on the regfile
529 cur_cr_idx = Signal.like(cur_vl)
530 comb += cur_cr_idx.eq(cr_idx - 1)
531 # read the CR field, select the appropriate bit
532 cr_field = Signal(4)
533 scr_bit = Signal()
534 dcr_bit = Signal()
535 comb += cr_field.eq(cr_pred.data_o)
536 comb += scr_bit.eq(cr_field.bit_select(sidx, 1) ^ scrinvert)
537 comb += dcr_bit.eq(cr_field.bit_select(didx, 1) ^ dcrinvert)
538 # set the corresponding mask bit
539 bit_to_set = Signal.like(self.srcmask)
540 comb += bit_to_set.eq(1 << cur_cr_idx)
541 with m.If(scr_bit):
542 sync += self.srcmask.eq(self.srcmask | bit_to_set)
543 with m.If(dcr_bit):
544 sync += self.dstmask.eq(self.dstmask | bit_to_set)
545
546 with m.State("FETCH_PRED_DONE"):
547 comb += pred_mask_valid_o.eq(1)
548 with m.If(pred_mask_ready_i):
549 m.next = "FETCH_PRED_IDLE"
550
551 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
552 dbg, core_rst, is_svp64_mode,
553 fetch_pc_ready_o, fetch_pc_valid_i,
554 fetch_insn_valid_o, fetch_insn_ready_i,
555 pred_insn_valid_i, pred_insn_ready_o,
556 pred_mask_valid_o, pred_mask_ready_i,
557 exec_insn_valid_i, exec_insn_ready_o,
558 exec_pc_valid_o, exec_pc_ready_i):
559 """issue FSM
560
561 decode / issue FSM. this interacts with the "fetch" FSM
562 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
563 (outgoing). also interacts with the "execute" FSM
564 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
565 (incoming).
566 SVP64 RM prefixes have already been set up by the
567 "fetch" phase, so execute is fairly straightforward.
568 """
569
570 comb = m.d.comb
571 sync = m.d.sync
572 pdecode2 = self.pdecode2
573 cur_state = self.cur_state
574
575 # temporaries
576 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
577
578 # for updating svstate (things like srcstep etc.)
579 update_svstate = Signal() # set this (below) if updating
580 new_svstate = SVSTATERec("new_svstate")
581 comb += new_svstate.eq(cur_state.svstate)
582
583 # precalculate srcstep+1 and dststep+1
584 cur_srcstep = cur_state.svstate.srcstep
585 cur_dststep = cur_state.svstate.dststep
586 next_srcstep = Signal.like(cur_srcstep)
587 next_dststep = Signal.like(cur_dststep)
588 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
589 comb += next_dststep.eq(cur_state.svstate.dststep+1)
590
591 with m.FSM(name="issue_fsm"):
592
593 # sync with the "fetch" phase which is reading the instruction
594 # at this point, there is no instruction running, that
595 # could inadvertently update the PC.
596 with m.State("ISSUE_START"):
597 # wait on "core stop" release, before next fetch
598 # need to do this here, in case we are in a VL==0 loop
599 with m.If(~dbg.core_stop_o & ~core_rst):
600 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
601 with m.If(fetch_pc_ready_o): # fetch acknowledged us
602 m.next = "INSN_WAIT"
603 with m.Else():
604 # tell core it's stopped, and acknowledge debug handshake
605 comb += dbg.core_stopped_i.eq(1)
606 # while stopped, allow updating the PC and SVSTATE
607 with m.If(self.pc_i.ok):
608 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
609 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
610 sync += pc_changed.eq(1)
611 with m.If(self.svstate_i.ok):
612 comb += new_svstate.eq(self.svstate_i.data)
613 comb += update_svstate.eq(1)
614 sync += sv_changed.eq(1)
615
616 # wait for an instruction to arrive from Fetch
617 with m.State("INSN_WAIT"):
618 comb += fetch_insn_ready_i.eq(1)
619 with m.If(fetch_insn_valid_o):
620 # loop into ISSUE_START if it's a SVP64 instruction
621 # and VL == 0. this because VL==0 is a for-loop
622 # from 0 to 0 i.e. always, always a NOP.
623 cur_vl = cur_state.svstate.vl
624 with m.If(is_svp64_mode & (cur_vl == 0)):
625 # update the PC before fetching the next instruction
626 # since we are in a VL==0 loop, no instruction was
627 # executed that we could be overwriting
628 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
629 comb += self.state_w_pc.data_i.eq(nia)
630 comb += self.insn_done.eq(1)
631 m.next = "ISSUE_START"
632 with m.Else():
633 if self.svp64_en:
634 m.next = "PRED_START" # start fetching predicate
635 else:
636 m.next = "DECODE_SV" # skip predication
637
638 with m.State("PRED_START"):
639 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
640 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
641 m.next = "MASK_WAIT"
642
643 with m.State("MASK_WAIT"):
644 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
645 with m.If(pred_mask_valid_o): # predication masks are ready
646 m.next = "PRED_SKIP"
647
648 # skip zeros in predicate
649 with m.State("PRED_SKIP"):
650 with m.If(~is_svp64_mode):
651 m.next = "DECODE_SV" # nothing to do
652 with m.Else():
653 if self.svp64_en:
654 pred_src_zero = pdecode2.rm_dec.pred_sz
655 pred_dst_zero = pdecode2.rm_dec.pred_dz
656
657 # new srcstep, after skipping zeros
658 skip_srcstep = Signal.like(cur_srcstep)
659 # value to be added to the current srcstep
660 src_delta = Signal.like(cur_srcstep)
661 # add leading zeros to srcstep, if not in zero mode
662 with m.If(~pred_src_zero):
663 # priority encoder (count leading zeros)
664 # append guard bit, in case the mask is all zeros
665 pri_enc_src = PriorityEncoder(65)
666 m.submodules.pri_enc_src = pri_enc_src
667 comb += pri_enc_src.i.eq(Cat(self.srcmask,
668 Const(1, 1)))
669 comb += src_delta.eq(pri_enc_src.o)
670 # apply delta to srcstep
671 comb += skip_srcstep.eq(cur_srcstep + src_delta)
672 # shift-out all leading zeros from the mask
673 # plus the leading "one" bit
674 # TODO count leading zeros and shift-out the zero
675 # bits, in the same step, in hardware
676 sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
677
678 # same as above, but for dststep
679 skip_dststep = Signal.like(cur_dststep)
680 dst_delta = Signal.like(cur_dststep)
681 with m.If(~pred_dst_zero):
682 pri_enc_dst = PriorityEncoder(65)
683 m.submodules.pri_enc_dst = pri_enc_dst
684 comb += pri_enc_dst.i.eq(Cat(self.dstmask,
685 Const(1, 1)))
686 comb += dst_delta.eq(pri_enc_dst.o)
687 comb += skip_dststep.eq(cur_dststep + dst_delta)
688 sync += self.dstmask.eq(self.dstmask >> (dst_delta+1))
689
690 # TODO: initialize mask[VL]=1 to avoid passing past VL
691 with m.If((skip_srcstep >= cur_vl) |
692 (skip_dststep >= cur_vl)):
693 # end of VL loop. Update PC and reset src/dst step
694 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
695 comb += self.state_w_pc.data_i.eq(nia)
696 comb += new_svstate.srcstep.eq(0)
697 comb += new_svstate.dststep.eq(0)
698 comb += update_svstate.eq(1)
699 # synchronize with the simulator
700 comb += self.insn_done.eq(1)
701 # go back to Issue
702 m.next = "ISSUE_START"
703 with m.Else():
704 # update new src/dst step
705 comb += new_svstate.srcstep.eq(skip_srcstep)
706 comb += new_svstate.dststep.eq(skip_dststep)
707 comb += update_svstate.eq(1)
708 # proceed to Decode
709 m.next = "DECODE_SV"
710
711 # after src/dst step have been updated, we are ready
712 # to decode the instruction
713 with m.State("DECODE_SV"):
714 # decode the instruction
715 sync += core.e.eq(pdecode2.e)
716 sync += core.state.eq(cur_state)
717 sync += core.raw_insn_i.eq(dec_opcode_i)
718 sync += core.bigendian_i.eq(self.core_bigendian_i)
719 # set RA_OR_ZERO detection in satellite decoders
720 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
721 m.next = "INSN_EXECUTE" # move to "execute"
722
723 # handshake with execution FSM, move to "wait" once acknowledged
724 with m.State("INSN_EXECUTE"):
725 comb += exec_insn_valid_i.eq(1) # trigger execute
726 with m.If(exec_insn_ready_o): # execute acknowledged us
727 m.next = "EXECUTE_WAIT"
728
729 with m.State("EXECUTE_WAIT"):
730 # wait on "core stop" release, at instruction end
731 # need to do this here, in case we are in a VL>1 loop
732 with m.If(~dbg.core_stop_o & ~core_rst):
733 comb += exec_pc_ready_i.eq(1)
734 with m.If(exec_pc_valid_o):
735
736 # was this the last loop iteration?
737 is_last = Signal()
738 cur_vl = cur_state.svstate.vl
739 comb += is_last.eq(next_srcstep == cur_vl)
740
741 # if either PC or SVSTATE were changed by the previous
742 # instruction, go directly back to Fetch, without
743 # updating either PC or SVSTATE
744 with m.If(pc_changed | sv_changed):
745 m.next = "ISSUE_START"
746
747 # also return to Fetch, when no output was a vector
748 # (regardless of SRCSTEP and VL), or when the last
749 # instruction was really the last one of the VL loop
750 with m.Elif((~pdecode2.loop_continue) | is_last):
751 # before going back to fetch, update the PC state
752 # register with the NIA.
753 # ok here we are not reading the branch unit.
754 # TODO: this just blithely overwrites whatever
755 # pipeline updated the PC
756 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
757 comb += self.state_w_pc.data_i.eq(nia)
758 # reset SRCSTEP before returning to Fetch
759 if self.svp64_en:
760 with m.If(pdecode2.loop_continue):
761 comb += new_svstate.srcstep.eq(0)
762 comb += new_svstate.dststep.eq(0)
763 comb += update_svstate.eq(1)
764 else:
765 comb += new_svstate.srcstep.eq(0)
766 comb += new_svstate.dststep.eq(0)
767 comb += update_svstate.eq(1)
768 m.next = "ISSUE_START"
769
770 # returning to Execute? then, first update SRCSTEP
771 with m.Else():
772 comb += new_svstate.srcstep.eq(next_srcstep)
773 comb += new_svstate.dststep.eq(next_dststep)
774 comb += update_svstate.eq(1)
775 # return to mask skip loop
776 m.next = "PRED_SKIP"
777
778 with m.Else():
779 comb += dbg.core_stopped_i.eq(1)
780 # while stopped, allow updating the PC and SVSTATE
781 with m.If(self.pc_i.ok):
782 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
783 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
784 sync += pc_changed.eq(1)
785 with m.If(self.svstate_i.ok):
786 comb += new_svstate.eq(self.svstate_i.data)
787 comb += update_svstate.eq(1)
788 sync += sv_changed.eq(1)
789
790 # check if svstate needs updating: if so, write it to State Regfile
791 with m.If(update_svstate):
792 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
793 comb += self.state_w_sv.data_i.eq(new_svstate)
794 sync += cur_state.svstate.eq(new_svstate) # for next clock
795
796 def execute_fsm(self, m, core, pc_changed, sv_changed,
797 exec_insn_valid_i, exec_insn_ready_o,
798 exec_pc_valid_o, exec_pc_ready_i):
799 """execute FSM
800
801 execute FSM. this interacts with the "issue" FSM
802 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
803 (outgoing). SVP64 RM prefixes have already been set up by the
804 "issue" phase, so execute is fairly straightforward.
805 """
806
807 comb = m.d.comb
808 sync = m.d.sync
809 pdecode2 = self.pdecode2
810
811 # temporaries
812 core_busy_o = core.busy_o # core is busy
813 core_ivalid_i = core.ivalid_i # instruction is valid
814 core_issue_i = core.issue_i # instruction is issued
815 insn_type = core.e.do.insn_type # instruction MicroOp type
816
817 with m.FSM(name="exec_fsm"):
818
819 # waiting for instruction bus (stays there until not busy)
820 with m.State("INSN_START"):
821 comb += exec_insn_ready_o.eq(1)
822 with m.If(exec_insn_valid_i):
823 comb += core_ivalid_i.eq(1) # instruction is valid
824 comb += core_issue_i.eq(1) # and issued
825 sync += sv_changed.eq(0)
826 sync += pc_changed.eq(0)
827 m.next = "INSN_ACTIVE" # move to "wait completion"
828
829 # instruction started: must wait till it finishes
830 with m.State("INSN_ACTIVE"):
831 with m.If(insn_type != MicrOp.OP_NOP):
832 comb += core_ivalid_i.eq(1) # instruction is valid
833 # note changes to PC and SVSTATE
834 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
835 sync += sv_changed.eq(1)
836 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
837 sync += pc_changed.eq(1)
838 with m.If(~core_busy_o): # instruction done!
839 comb += exec_pc_valid_o.eq(1)
840 with m.If(exec_pc_ready_i):
841 comb += self.insn_done.eq(1)
842 m.next = "INSN_START" # back to fetch
843
844 def setup_peripherals(self, m):
845 comb, sync = m.d.comb, m.d.sync
846
847 m.submodules.core = core = DomainRenamer("coresync")(self.core)
848 m.submodules.imem = imem = self.imem
849 m.submodules.dbg = dbg = self.dbg
850 if self.jtag_en:
851 m.submodules.jtag = jtag = self.jtag
852 # TODO: UART2GDB mux, here, from external pin
853 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
854 sync += dbg.dmi.connect_to(jtag.dmi)
855
856 cur_state = self.cur_state
857
858 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
859 if self.sram4x4k:
860 for i, sram in enumerate(self.sram4k):
861 m.submodules["sram4k_%d" % i] = sram
862 comb += sram.enable.eq(self.wb_sram_en)
863
864 # XICS interrupt handler
865 if self.xics:
866 m.submodules.xics_icp = icp = self.xics_icp
867 m.submodules.xics_ics = ics = self.xics_ics
868 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
869 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
870
871 # GPIO test peripheral
872 if self.gpio:
873 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
874
875 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
876 # XXX causes litex ECP5 test to get wrong idea about input and output
877 # (but works with verilator sim *sigh*)
878 #if self.gpio and self.xics:
879 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
880
881 # instruction decoder
882 pdecode = create_pdecode()
883 m.submodules.dec2 = pdecode2 = self.pdecode2
884 if self.svp64_en:
885 m.submodules.svp64 = svp64 = self.svp64
886
887 # convenience
888 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
889 intrf = self.core.regs.rf['int']
890
891 # clock delay power-on reset
892 cd_por = ClockDomain(reset_less=True)
893 cd_sync = ClockDomain()
894 core_sync = ClockDomain("coresync")
895 m.domains += cd_por, cd_sync, core_sync
896
897 ti_rst = Signal(reset_less=True)
898 delay = Signal(range(4), reset=3)
899 with m.If(delay != 0):
900 m.d.por += delay.eq(delay - 1)
901 comb += cd_por.clk.eq(ClockSignal())
902
903 # power-on reset delay
904 core_rst = ResetSignal("coresync")
905 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
906 comb += core_rst.eq(ti_rst)
907
908 # busy/halted signals from core
909 comb += self.busy_o.eq(core.busy_o)
910 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
911
912 # temporary hack: says "go" immediately for both address gen and ST
913 l0 = core.l0
914 ldst = core.fus.fus['ldst0']
915 st_go_edge = rising_edge(m, ldst.st.rel_o)
916 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
917 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
918
919 return core_rst
920
921 def elaborate(self, platform):
922 m = Module()
923 # convenience
924 comb, sync = m.d.comb, m.d.sync
925 cur_state = self.cur_state
926 pdecode2 = self.pdecode2
927 dbg = self.dbg
928 core = self.core
929
930 # set up peripherals and core
931 core_rst = self.setup_peripherals(m)
932
933 # reset current state if core reset requested
934 with m.If(core_rst):
935 m.d.sync += self.cur_state.eq(0)
936
937 # PC and instruction from I-Memory
938 comb += self.pc_o.eq(cur_state.pc)
939 pc_changed = Signal() # note write to PC
940 sv_changed = Signal() # note write to SVSTATE
941
942 # read state either from incoming override or from regfile
943 # TODO: really should be doing MSR in the same way
944 pc = state_get(m, core_rst, self.pc_i,
945 "pc", # read PC
946 self.state_r_pc, StateRegs.PC)
947 svstate = state_get(m, core_rst, self.svstate_i,
948 "svstate", # read SVSTATE
949 self.state_r_sv, StateRegs.SVSTATE)
950
951 # don't write pc every cycle
952 comb += self.state_w_pc.wen.eq(0)
953 comb += self.state_w_pc.data_i.eq(0)
954
955 # don't read msr every cycle
956 comb += self.state_r_msr.ren.eq(0)
957
958 # address of the next instruction, in the absence of a branch
959 # depends on the instruction size
960 nia = Signal(64)
961
962 # connect up debug signals
963 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
964 comb += dbg.terminate_i.eq(core.core_terminate_o)
965 comb += dbg.state.pc.eq(pc)
966 comb += dbg.state.svstate.eq(svstate)
967 comb += dbg.state.msr.eq(cur_state.msr)
968
969 # pass the prefix mode from Fetch to Issue, so the latter can loop
970 # on VL==0
971 is_svp64_mode = Signal()
972
973 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
974 # these are the handshake signals between fetch and decode/execute
975
976 # fetch FSM can run as soon as the PC is valid
977 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
978 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
979
980 # fetch FSM hands over the instruction to be decoded / issued
981 fetch_insn_valid_o = Signal()
982 fetch_insn_ready_i = Signal()
983
984 # predicate fetch FSM decodes and fetches the predicate
985 pred_insn_valid_i = Signal()
986 pred_insn_ready_o = Signal()
987
988 # predicate fetch FSM delivers the masks
989 pred_mask_valid_o = Signal()
990 pred_mask_ready_i = Signal()
991
992 # issue FSM delivers the instruction to the be executed
993 exec_insn_valid_i = Signal()
994 exec_insn_ready_o = Signal()
995
996 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
997 exec_pc_valid_o = Signal()
998 exec_pc_ready_i = Signal()
999
1000 # the FSMs here are perhaps unusual in that they detect conditions
1001 # then "hold" information, combinatorially, for the core
1002 # (as opposed to using sync - which would be on a clock's delay)
1003 # this includes the actual opcode, valid flags and so on.
1004
1005 # Fetch, then predicate fetch, then Issue, then Execute.
1006 # Issue is where the VL for-loop # lives. the ready/valid
1007 # signalling is used to communicate between the four.
1008
1009 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
1010 fetch_pc_ready_o, fetch_pc_valid_i,
1011 fetch_insn_valid_o, fetch_insn_ready_i)
1012
1013 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
1014 dbg, core_rst, is_svp64_mode,
1015 fetch_pc_ready_o, fetch_pc_valid_i,
1016 fetch_insn_valid_o, fetch_insn_ready_i,
1017 pred_insn_valid_i, pred_insn_ready_o,
1018 pred_mask_valid_o, pred_mask_ready_i,
1019 exec_insn_valid_i, exec_insn_ready_o,
1020 exec_pc_valid_o, exec_pc_ready_i)
1021
1022 if self.svp64_en:
1023 self.fetch_predicate_fsm(m,
1024 pred_insn_valid_i, pred_insn_ready_o,
1025 pred_mask_valid_o, pred_mask_ready_i)
1026
1027 self.execute_fsm(m, core, pc_changed, sv_changed,
1028 exec_insn_valid_i, exec_insn_ready_o,
1029 exec_pc_valid_o, exec_pc_ready_i)
1030
1031 # whatever was done above, over-ride it if core reset is held
1032 with m.If(core_rst):
1033 sync += nia.eq(0)
1034
1035 # this bit doesn't have to be in the FSM: connect up to read
1036 # regfiles on demand from DMI
1037 self.do_dmi(m, dbg)
1038
1039 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
1040 # (which uses that in PowerDecoder2 to raise 0x900 exception)
1041 self.tb_dec_fsm(m, cur_state.dec)
1042
1043 return m
1044
1045 def do_dmi(self, m, dbg):
1046 """deals with DMI debug requests
1047
1048 currently only provides read requests for the INT regfile, CR and XER
1049 it will later also deal with *writing* to these regfiles.
1050 """
1051 comb = m.d.comb
1052 sync = m.d.sync
1053 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
1054 intrf = self.core.regs.rf['int']
1055
1056 with m.If(d_reg.req): # request for regfile access being made
1057 # TODO: error-check this
1058 # XXX should this be combinatorial? sync better?
1059 if intrf.unary:
1060 comb += self.int_r.ren.eq(1<<d_reg.addr)
1061 else:
1062 comb += self.int_r.addr.eq(d_reg.addr)
1063 comb += self.int_r.ren.eq(1)
1064 d_reg_delay = Signal()
1065 sync += d_reg_delay.eq(d_reg.req)
1066 with m.If(d_reg_delay):
1067 # data arrives one clock later
1068 comb += d_reg.data.eq(self.int_r.data_o)
1069 comb += d_reg.ack.eq(1)
1070
1071 # sigh same thing for CR debug
1072 with m.If(d_cr.req): # request for regfile access being made
1073 comb += self.cr_r.ren.eq(0b11111111) # enable all
1074 d_cr_delay = Signal()
1075 sync += d_cr_delay.eq(d_cr.req)
1076 with m.If(d_cr_delay):
1077 # data arrives one clock later
1078 comb += d_cr.data.eq(self.cr_r.data_o)
1079 comb += d_cr.ack.eq(1)
1080
1081 # aaand XER...
1082 with m.If(d_xer.req): # request for regfile access being made
1083 comb += self.xer_r.ren.eq(0b111111) # enable all
1084 d_xer_delay = Signal()
1085 sync += d_xer_delay.eq(d_xer.req)
1086 with m.If(d_xer_delay):
1087 # data arrives one clock later
1088 comb += d_xer.data.eq(self.xer_r.data_o)
1089 comb += d_xer.ack.eq(1)
1090
1091 def tb_dec_fsm(self, m, spr_dec):
1092 """tb_dec_fsm
1093
1094 this is a FSM for updating either dec or tb. it runs alternately
1095 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
1096 value to DEC, however the regfile has "passthrough" on it so this
1097 *should* be ok.
1098
1099 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
1100 """
1101
1102 comb, sync = m.d.comb, m.d.sync
1103 fast_rf = self.core.regs.rf['fast']
1104 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
1105 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
1106
1107 with m.FSM() as fsm:
1108
1109 # initiates read of current DEC
1110 with m.State("DEC_READ"):
1111 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
1112 comb += fast_r_dectb.ren.eq(1)
1113 m.next = "DEC_WRITE"
1114
1115 # waits for DEC read to arrive (1 cycle), updates with new value
1116 with m.State("DEC_WRITE"):
1117 new_dec = Signal(64)
1118 # TODO: MSR.LPCR 32-bit decrement mode
1119 comb += new_dec.eq(fast_r_dectb.data_o - 1)
1120 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
1121 comb += fast_w_dectb.wen.eq(1)
1122 comb += fast_w_dectb.data_i.eq(new_dec)
1123 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
1124 m.next = "TB_READ"
1125
1126 # initiates read of current TB
1127 with m.State("TB_READ"):
1128 comb += fast_r_dectb.addr.eq(FastRegs.TB)
1129 comb += fast_r_dectb.ren.eq(1)
1130 m.next = "TB_WRITE"
1131
1132 # waits for read TB to arrive, initiates write of current TB
1133 with m.State("TB_WRITE"):
1134 new_tb = Signal(64)
1135 comb += new_tb.eq(fast_r_dectb.data_o + 1)
1136 comb += fast_w_dectb.addr.eq(FastRegs.TB)
1137 comb += fast_w_dectb.wen.eq(1)
1138 comb += fast_w_dectb.data_i.eq(new_tb)
1139 m.next = "DEC_READ"
1140
1141 return m
1142
1143 def __iter__(self):
1144 yield from self.pc_i.ports()
1145 yield self.pc_o
1146 yield self.memerr_o
1147 yield from self.core.ports()
1148 yield from self.imem.ports()
1149 yield self.core_bigendian_i
1150 yield self.busy_o
1151
1152 def ports(self):
1153 return list(self)
1154
1155 def external_ports(self):
1156 ports = self.pc_i.ports()
1157 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
1158 ]
1159
1160 if self.jtag_en:
1161 ports += list(self.jtag.external_ports())
1162 else:
1163 # don't add DMI if JTAG is enabled
1164 ports += list(self.dbg.dmi.ports())
1165
1166 ports += list(self.imem.ibus.fields.values())
1167 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1168
1169 if self.sram4x4k:
1170 for sram in self.sram4k:
1171 ports += list(sram.bus.fields.values())
1172
1173 if self.xics:
1174 ports += list(self.xics_icp.bus.fields.values())
1175 ports += list(self.xics_ics.bus.fields.values())
1176 ports.append(self.int_level_i)
1177
1178 if self.gpio:
1179 ports += list(self.simple_gpio.bus.fields.values())
1180 ports.append(self.gpio_o)
1181
1182 return ports
1183
1184 def ports(self):
1185 return list(self)
1186
1187
1188 class TestIssuer(Elaboratable):
1189 def __init__(self, pspec):
1190 self.ti = TestIssuerInternal(pspec)
1191
1192 self.pll = DummyPLL()
1193
1194 # PLL direct clock or not
1195 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1196 if self.pll_en:
1197 self.pll_18_o = Signal(reset_less=True)
1198 self.clk_sel_i = Signal(reset_less=True)
1199
1200 def elaborate(self, platform):
1201 m = Module()
1202 comb = m.d.comb
1203
1204 # TestIssuer runs at direct clock
1205 m.submodules.ti = ti = self.ti
1206 cd_int = ClockDomain("coresync")
1207
1208 if self.pll_en:
1209 # ClockSelect runs at PLL output internal clock rate
1210 m.submodules.pll = pll = self.pll
1211
1212 # add clock domains from PLL
1213 cd_pll = ClockDomain("pllclk")
1214 m.domains += cd_pll
1215
1216 # PLL clock established. has the side-effect of running clklsel
1217 # at the PLL's speed (see DomainRenamer("pllclk") above)
1218 pllclk = ClockSignal("pllclk")
1219 comb += pllclk.eq(pll.clk_pll_o)
1220
1221 # wire up external 24mhz to PLL
1222 comb += pll.clk_24_i.eq(ClockSignal())
1223
1224 # output 18 mhz PLL test signal
1225 comb += self.pll_18_o.eq(pll.pll_18_o)
1226
1227 # input to pll clock selection
1228 comb += Cat(pll.sel_a0_i, pll.sel_a1_i).eq(self.clk_sel_i)
1229
1230 # now wire up ResetSignals. don't mind them being in this domain
1231 pll_rst = ResetSignal("pllclk")
1232 comb += pll_rst.eq(ResetSignal())
1233
1234 # internal clock is set to selector clock-out. has the side-effect of
1235 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1236 intclk = ClockSignal("coresync")
1237 if self.pll_en:
1238 comb += intclk.eq(pll.clk_pll_o)
1239 else:
1240 comb += intclk.eq(ClockSignal())
1241
1242 return m
1243
1244 def ports(self):
1245 return list(self.ti.ports()) + list(self.pll.ports()) + \
1246 [ClockSignal(), ResetSignal()]
1247
1248 def external_ports(self):
1249 ports = self.ti.external_ports()
1250 ports.append(ClockSignal())
1251 ports.append(ResetSignal())
1252 if self.pll_en:
1253 ports.append(self.clk_sel_i)
1254 ports.append(self.pll_18_o)
1255 ports.append(self.pll.pll_ana_o)
1256 return ports
1257
1258
1259 if __name__ == '__main__':
1260 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1261 'spr': 1,
1262 'div': 1,
1263 'mul': 1,
1264 'shiftrot': 1
1265 }
1266 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1267 imem_ifacetype='bare_wb',
1268 addr_wid=48,
1269 mask_wid=8,
1270 reg_wid=64,
1271 units=units)
1272 dut = TestIssuer(pspec)
1273 vl = main(dut, ports=dut.ports(), name="test_issuer")
1274
1275 if len(sys.argv) == 1:
1276 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1277 with open("test_issuer.il", "w") as f:
1278 f.write(vl)