src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # JTAG interface.  add this right at the start because if it's
  64         # added it *modifies* the pspec, by adding enable/disable signals
  65         # for parts of the rest of the core
  66         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  67         if self.jtag_en:
  68             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  69                       'pwm', 'sd0', 'sdr'}
  70             self.jtag = JTAG(get_pinspecs(subset=subset))
  71             # add signals to pspec to enable/disable icache and dcache
  72             # (or data and intstruction wishbone if icache/dcache not included)
  73             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  74             # TODO: do we actually care if these are not domain-synchronised?
  75             # honestly probably not.
  76             pspec.wb_icache_en = self.jtag.wb_icache_en
  77             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  78             self.wb_sram_en = self.jtag.wb_sram_en
  79         else:
  80             self.wb_sram_en = Const(1)
  81
  82         # add 4k sram blocks?
  83         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  84                          pspec.sram4x4kblock == True)
  85         if self.sram4x4k:
  86             self.sram4k = []
  87             for i in range(4):
  88                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  89                                                     features={'err'}))
  90
  91         # add interrupt controller?
  92         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  93         if self.xics:
  94             self.xics_icp = XICS_ICP()
  95             self.xics_ics = XICS_ICS()
  96             self.int_level_i = self.xics_ics.int_level_i
  97
  98         # add GPIO peripheral?
  99         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 100         if self.gpio:
 101             self.simple_gpio = SimpleGPIO()
 102             self.gpio_o = self.simple_gpio.gpio_o
 103
 104         # main instruction core25
 105         self.core = core = NonProductionCore(pspec)
 106
 107         # instruction decoder.  goes into Trap Record
 108         pdecode = create_pdecode()
 109         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 110         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 111                                      opkls=IssuerDecode2ToOperand)
 112         self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 113
 114         # Test Instruction memory
 115         self.imem = ConfigFetchUnit(pspec).fu
 116         # one-row cache of instruction read
 117         self.iline = Signal(64) # one instruction line
 118         self.iprev_adr = Signal(64) # previous address: if different, do read
 119
 120         # DMI interface
 121         self.dbg = CoreDebug()
 122
 123         # instruction go/monitor
 124         self.pc_o = Signal(64, reset_less=True)
 125         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 126         self.svstate_i = Data(32, "svstate_i") # ditto
 127         self.core_bigendian_i = Signal()
 128         self.busy_o = Signal(reset_less=True)
 129         self.memerr_o = Signal(reset_less=True)
 130
 131         # STATE regfile read /write ports for PC, MSR, SVSTATE
 132         staterf = self.core.regs.rf['state']
 133         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 134         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 135         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 136         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 137         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 138
 139         # DMI interface access
 140         intrf = self.core.regs.rf['int']
 141         crrf = self.core.regs.rf['cr']
 142         xerrf = self.core.regs.rf['xer']
 143         self.int_r = intrf.r_ports['dmi'] # INT read
 144         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 145         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 146
 147         # hack method of keeping an eye on whether branch/trap set the PC
 148         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 149         self.state_nia.wen.name = 'state_nia_wen'
 150
 151     def fetch_fsm(self, m, core, pc, svstate, nia,
 152                         fetch_pc_ready_o, fetch_pc_valid_i,
 153                         fetch_insn_valid_o, fetch_insn_ready_i):
 154         """fetch FSM
 155         this FSM performs fetch of raw instruction data, partial-decodes
 156         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 157         read a 2nd 32-bit quantity if that occurs.
 158         """
 159         comb = m.d.comb
 160         sync = m.d.sync
 161         pdecode2 = self.pdecode2
 162         svp64 = self.svp64
 163         cur_state = self.cur_state
 164         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 165
 166         msr_read = Signal(reset=1)
 167
 168         with m.FSM(name='fetch_fsm'):
 169
 170             # waiting (zzz)
 171             with m.State("IDLE"):
 172                 comb += fetch_pc_ready_o.eq(1)
 173                 with m.If(fetch_pc_valid_i):
 174                     # instruction allowed to go: start by reading the PC
 175                     # capture the PC and also drop it into Insn Memory
 176                     # we have joined a pair of combinatorial memory
 177                     # lookups together.  this is Generally Bad.
 178                     comb += self.imem.a_pc_i.eq(pc)
 179                     comb += self.imem.a_valid_i.eq(1)
 180                     comb += self.imem.f_valid_i.eq(1)
 181                     sync += cur_state.pc.eq(pc)
 182                     sync += cur_state.svstate.eq(svstate) # and svstate
 183
 184                     # initiate read of MSR. arrives one clock later
 185                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 186                     sync += msr_read.eq(0)
 187
 188                     m.next = "INSN_READ"  # move to "wait for bus" phase
 189
 190             # dummy pause to find out why simulation is not keeping up
 191             with m.State("INSN_READ"):
 192                 # one cycle later, msr/sv read arrives.  valid only once.
 193                 with m.If(~msr_read):
 194                     sync += msr_read.eq(1) # yeah don't read it again
 195                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 196                 with m.If(self.imem.f_busy_o): # zzz...
 197                     # busy: stay in wait-read
 198                     comb += self.imem.a_valid_i.eq(1)
 199                     comb += self.imem.f_valid_i.eq(1)
 200                 with m.Else():
 201                     # not busy: instruction fetched
 202                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 203                     # decode the SVP64 prefix, if any
 204                     comb += svp64.raw_opcode_in.eq(insn)
 205                     comb += svp64.bigendian.eq(self.core_bigendian_i)
 206                     # pass the decoded prefix (if any) to PowerDecoder2
 207                     sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 208                     # calculate the address of the following instruction
 209                     insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 210                     sync += nia.eq(cur_state.pc + insn_size)
 211                     with m.If(~svp64.is_svp64_mode):
 212                         # with no prefix, store the instruction
 213                         # and hand it directly to the next FSM
 214                         sync += dec_opcode_i.eq(insn)
 215                         m.next = "INSN_READY"
 216                     with m.Else():
 217                         # fetch the rest of the instruction from memory
 218                         comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 219                         comb += self.imem.a_valid_i.eq(1)
 220                         comb += self.imem.f_valid_i.eq(1)
 221                         m.next = "INSN_READ2"
 222
 223             with m.State("INSN_READ2"):
 224                 with m.If(self.imem.f_busy_o):  # zzz...
 225                     # busy: stay in wait-read
 226                     comb += self.imem.a_valid_i.eq(1)
 227                     comb += self.imem.f_valid_i.eq(1)
 228                 with m.Else():
 229                     # not busy: instruction fetched
 230                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 231                     sync += dec_opcode_i.eq(insn)
 232                     m.next = "INSN_READY"
 233
 234             with m.State("INSN_READY"):
 235                 # hand over the instruction, to be decoded
 236                 comb += fetch_insn_valid_o.eq(1)
 237                 with m.If(fetch_insn_ready_i):
 238                     m.next = "IDLE"
 239
 240     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 241                   dbg, core_rst,
 242                   fetch_pc_ready_o, fetch_pc_valid_i,
 243                   fetch_insn_valid_o, fetch_insn_ready_i,
 244                   exec_insn_valid_i, exec_insn_ready_o,
 245                   exec_pc_valid_o, exec_pc_ready_i):
 246         """issue FSM
 247
 248         decode / issue FSM.  this interacts with the "fetch" FSM
 249         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 250         (outgoing). also interacts with the "execute" FSM
 251         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 252         (incoming).
 253         SVP64 RM prefixes have already been set up by the
 254         "fetch" phase, so execute is fairly straightforward.
 255         """
 256
 257         comb = m.d.comb
 258         sync = m.d.sync
 259         pdecode2 = self.pdecode2
 260         cur_state = self.cur_state
 261
 262         # temporaries
 263         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 264
 265         # for updating svstate (things like srcstep etc.)
 266         update_svstate = Signal() # set this (below) if updating
 267         new_svstate = SVSTATERec("new_svstate")
 268         comb += new_svstate.eq(cur_state.svstate)
 269
 270         with m.FSM(name="issue_fsm"):
 271
 272             # go fetch the instruction at the current PC
 273             # at this point, there is no instruction running, that
 274             # could inadvertently update the PC.
 275             with m.State("INSN_FETCH"):
 276                 # wait on "core stop" release, before next fetch
 277                 # need to do this here, in case we are in a VL==0 loop
 278                 with m.If(~dbg.core_stop_o & ~core_rst):
 279                     comb += fetch_pc_valid_i.eq(1)
 280                     with m.If(fetch_pc_ready_o):
 281                         m.next = "INSN_WAIT"
 282                 with m.Else():
 283                     comb += core.core_stopped_i.eq(1)
 284                     comb += dbg.core_stopped_i.eq(1)
 285                     # while stopped, allow updating the PC and SVSTATE
 286                     with m.If(self.pc_i.ok):
 287                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 288                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 289                         sync += pc_changed.eq(1)
 290                     with m.If(self.svstate_i.ok):
 291                         comb += new_svstate.eq(self.svstate_i.data)
 292                         comb += update_svstate.eq(1)
 293                         sync += sv_changed.eq(1)
 294
 295             # decode the instruction when it arrives
 296             with m.State("INSN_WAIT"):
 297                 comb += fetch_insn_ready_i.eq(1)
 298                 with m.If(fetch_insn_valid_o):
 299                     # decode the instruction
 300                     sync += core.e.eq(pdecode2.e)
 301                     sync += core.state.eq(cur_state)
 302                     sync += core.raw_insn_i.eq(dec_opcode_i)
 303                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 304                     # loop into INSN_FETCH if it's a vector instruction
 305                     # and VL == 0.  this because VL==0 is a for-loop
 306                     # from 0 to 0 i.e. always, always a NOP.
 307                     cur_vl = cur_state.svstate.vl
 308                     with m.If(~pdecode2.no_out_vec & (cur_vl == 0)):
 309                         # update the PC before fetching the next instruction
 310                         # since we are in a VL==0 loop, no instruction was
 311                         # executed that we could be overwriting
 312                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 313                         comb += self.state_w_pc.data_i.eq(nia)
 314                         m.next = "INSN_FETCH"
 315                     with m.Else():
 316                         m.next = "INSN_EXECUTE"  # move to "execute"
 317
 318             with m.State("INSN_EXECUTE"):
 319                 comb += exec_insn_valid_i.eq(1)
 320                 with m.If(exec_insn_ready_o):
 321                     m.next = "EXECUTE_WAIT"
 322
 323             with m.State("EXECUTE_WAIT"):
 324                 # wait on "core stop" release, at instruction end
 325                 # need to do this here, in case we are in a VL>1 loop
 326                 with m.If(~dbg.core_stop_o & ~core_rst):
 327                     comb += exec_pc_ready_i.eq(1)
 328                     with m.If(exec_pc_valid_o):
 329                         # precalculate srcstep+1
 330                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 331                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 332                         # was this the last loop iteration?
 333                         is_last = Signal()
 334                         cur_vl = cur_state.svstate.vl
 335                         comb += is_last.eq(next_srcstep == cur_vl)
 336
 337                         # if either PC or SVSTATE were changed by the previous
 338                         # instruction, go directly back to Fetch, without
 339                         # updating either PC or SVSTATE
 340                         with m.If(pc_changed | sv_changed):
 341                             m.next = "INSN_FETCH"
 342
 343                         # also return to Fetch, when no output was a vector
 344                         # (regardless of SRCSTEP and VL), or when the last
 345                         # instruction was really the last one of the VL loop
 346                         with m.Elif(pdecode2.no_out_vec | is_last):
 347                             # before going back to fetch, update the PC state
 348                             # register with the NIA.
 349                             # ok here we are not reading the branch unit.
 350                             # TODO: this just blithely overwrites whatever
 351                             #       pipeline updated the PC
 352                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 353                             comb += self.state_w_pc.data_i.eq(nia)
 354                             # reset SRCSTEP before returning to Fetch
 355                             with m.If(~pdecode2.no_out_vec):
 356                                 comb += new_svstate.srcstep.eq(0)
 357                                 comb += update_svstate.eq(1)
 358                             m.next = "INSN_FETCH"
 359
 360                         # returning to Execute? then, first update SRCSTEP
 361                         with m.Else():
 362                             comb += new_svstate.srcstep.eq(next_srcstep)
 363                             comb += update_svstate.eq(1)
 364                             m.next = "DECODE_SV"
 365
 366                 with m.Else():
 367                     comb += core.core_stopped_i.eq(1)
 368                     comb += dbg.core_stopped_i.eq(1)
 369                     # while stopped, allow updating the PC and SVSTATE
 370                     with m.If(self.pc_i.ok):
 371                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 372                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 373                         sync += pc_changed.eq(1)
 374                     with m.If(self.svstate_i.ok):
 375                         comb += new_svstate.eq(self.svstate_i.data)
 376                         comb += update_svstate.eq(1)
 377                         sync += sv_changed.eq(1)
 378
 379             # need to decode the instruction again, after updating SRCSTEP
 380             # in the previous state.
 381             # mostly a copy of INSN_WAIT, but without the actual wait
 382             with m.State("DECODE_SV"):
 383                 # decode the instruction
 384                 sync += core.e.eq(pdecode2.e)
 385                 sync += core.state.eq(cur_state)
 386                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 387                 m.next = "INSN_EXECUTE"  # move to "execute"
 388
 389         # check if svstate needs updating: if so, write it to State Regfile
 390         with m.If(update_svstate):
 391             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 392             comb += self.state_w_sv.data_i.eq(new_svstate)
 393             sync += cur_state.svstate.eq(new_svstate) # for next clock
 394
 395     def execute_fsm(self, m, core, insn_done, pc_changed, sv_changed,
 396                     exec_insn_valid_i, exec_insn_ready_o,
 397                     exec_pc_valid_o, exec_pc_ready_i):
 398         """execute FSM
 399
 400         execute FSM. this interacts with the "issue" FSM
 401         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 402         (outgoing). SVP64 RM prefixes have already been set up by the
 403         "issue" phase, so execute is fairly straightforward.
 404         """
 405
 406         comb = m.d.comb
 407         sync = m.d.sync
 408         pdecode2 = self.pdecode2
 409         svp64 = self.svp64
 410
 411         # temporaries
 412         core_busy_o = core.busy_o                 # core is busy
 413         core_ivalid_i = core.ivalid_i             # instruction is valid
 414         core_issue_i = core.issue_i               # instruction is issued
 415         insn_type = core.e.do.insn_type           # instruction MicroOp type
 416
 417         with m.FSM(name="exec_fsm"):
 418
 419             # waiting for instruction bus (stays there until not busy)
 420             with m.State("INSN_START"):
 421                 comb += exec_insn_ready_o.eq(1)
 422                 with m.If(exec_insn_valid_i):
 423                     comb += core_ivalid_i.eq(1)  # instruction is valid
 424                     comb += core_issue_i.eq(1)  # and issued
 425                     sync += sv_changed.eq(0)
 426                     sync += pc_changed.eq(0)
 427                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 428
 429             # instruction started: must wait till it finishes
 430             with m.State("INSN_ACTIVE"):
 431                 with m.If(insn_type != MicrOp.OP_NOP):
 432                     comb += core_ivalid_i.eq(1) # instruction is valid
 433                 # note changes to PC and SVSTATE
 434                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 435                     sync += sv_changed.eq(1)
 436                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 437                     sync += pc_changed.eq(1)
 438                 with m.If(~core_busy_o): # instruction done!
 439                     comb += insn_done.eq(1)
 440                     comb += exec_pc_valid_o.eq(1)
 441                     with m.If(exec_pc_ready_i):
 442                         m.next = "INSN_START"  # back to fetch
 443
 444     def elaborate(self, platform):
 445         m = Module()
 446         comb, sync = m.d.comb, m.d.sync
 447
 448         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 449         m.submodules.imem = imem = self.imem
 450         m.submodules.dbg = dbg = self.dbg
 451         if self.jtag_en:
 452             m.submodules.jtag = jtag = self.jtag
 453             # TODO: UART2GDB mux, here, from external pin
 454             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 455             sync += dbg.dmi.connect_to(jtag.dmi)
 456
 457         cur_state = self.cur_state
 458
 459         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 460         if self.sram4x4k:
 461             for i, sram in enumerate(self.sram4k):
 462                 m.submodules["sram4k_%d" % i] = sram
 463                 comb += sram.enable.eq(self.wb_sram_en)
 464
 465         # XICS interrupt handler
 466         if self.xics:
 467             m.submodules.xics_icp = icp = self.xics_icp
 468             m.submodules.xics_ics = ics = self.xics_ics
 469             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 470             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 471
 472         # GPIO test peripheral
 473         if self.gpio:
 474             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 475
 476         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 477         # XXX causes litex ECP5 test to get wrong idea about input and output
 478         # (but works with verilator sim *sigh*)
 479         #if self.gpio and self.xics:
 480         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 481
 482         # instruction decoder
 483         pdecode = create_pdecode()
 484         m.submodules.dec2 = pdecode2 = self.pdecode2
 485         m.submodules.svp64 = svp64 = self.svp64
 486
 487         # convenience
 488         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 489         intrf = self.core.regs.rf['int']
 490
 491         # clock delay power-on reset
 492         cd_por  = ClockDomain(reset_less=True)
 493         cd_sync = ClockDomain()
 494         core_sync = ClockDomain("coresync")
 495         m.domains += cd_por, cd_sync, core_sync
 496
 497         ti_rst = Signal(reset_less=True)
 498         delay = Signal(range(4), reset=3)
 499         with m.If(delay != 0):
 500             m.d.por += delay.eq(delay - 1)
 501         comb += cd_por.clk.eq(ClockSignal())
 502
 503         # power-on reset delay
 504         core_rst = ResetSignal("coresync")
 505         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 506         comb += core_rst.eq(ti_rst)
 507
 508         # busy/halted signals from core
 509         comb += self.busy_o.eq(core.busy_o)
 510         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 511
 512         # temporary hack: says "go" immediately for both address gen and ST
 513         l0 = core.l0
 514         ldst = core.fus.fus['ldst0']
 515         st_go_edge = rising_edge(m, ldst.st.rel_o)
 516         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 517         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 518
 519         # PC and instruction from I-Memory
 520         comb += self.pc_o.eq(cur_state.pc)
 521         pc_changed = Signal() # note write to PC
 522         sv_changed = Signal() # note write to SVSTATE
 523         insn_done = Signal()  # fires just once
 524
 525         # read the PC
 526         pc = Signal(64, reset_less=True)
 527         pc_ok_delay = Signal()
 528         sync += pc_ok_delay.eq(~self.pc_i.ok)
 529         with m.If(self.pc_i.ok):
 530             # incoming override (start from pc_i)
 531             comb += pc.eq(self.pc_i.data)
 532         with m.Else():
 533             # otherwise read StateRegs regfile for PC...
 534             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 535         # ... but on a 1-clock delay
 536         with m.If(pc_ok_delay):
 537             comb += pc.eq(self.state_r_pc.data_o)
 538
 539         # read svstate
 540         svstate = Signal(64, reset_less=True)
 541         svstate_ok_delay = Signal()
 542         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 543         with m.If(self.svstate_i.ok):
 544             # incoming override (start from svstate__i)
 545             comb += svstate.eq(self.svstate_i.data)
 546         with m.Else():
 547             # otherwise read StateRegs regfile for SVSTATE...
 548             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 549         # ... but on a 1-clock delay
 550         with m.If(svstate_ok_delay):
 551             comb += svstate.eq(self.state_r_sv.data_o)
 552
 553         # don't write pc every cycle
 554         comb += self.state_w_pc.wen.eq(0)
 555         comb += self.state_w_pc.data_i.eq(0)
 556
 557         # don't read msr every cycle
 558         comb += self.state_r_msr.ren.eq(0)
 559
 560         # address of the next instruction, in the absence of a branch
 561         # depends on the instruction size
 562         nia = Signal(64, reset_less=True)
 563
 564         # connect up debug signals
 565         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 566         comb += dbg.terminate_i.eq(core.core_terminate_o)
 567         comb += dbg.state.pc.eq(pc)
 568         comb += dbg.state.svstate.eq(svstate)
 569         comb += dbg.state.msr.eq(cur_state.msr)
 570
 571         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 572         # these are the handshake signals between fetch and decode/execute
 573
 574         # fetch FSM can run as soon as the PC is valid
 575         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 576         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 577
 578         # fetch FSM hands over the instruction to be decoded / issued
 579         fetch_insn_valid_o = Signal()
 580         fetch_insn_ready_i = Signal()
 581
 582         # issue FSM delivers the instruction to the be executed
 583         exec_insn_valid_i = Signal()
 584         exec_insn_ready_o = Signal()
 585
 586         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 587         exec_pc_valid_o = Signal()
 588         exec_pc_ready_i = Signal()
 589
 590         # the FSMs here are perhaps unusual in that they detect conditions
 591         # then "hold" information, combinatorially, for the core
 592         # (as opposed to using sync - which would be on a clock's delay)
 593         # this includes the actual opcode, valid flags and so on.
 594
 595         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 596         # lives.  the ready/valid signalling is used to communicate between
 597         # the three.
 598
 599         self.fetch_fsm(m, core, pc, svstate, nia,
 600                        fetch_pc_ready_o, fetch_pc_valid_i,
 601                        fetch_insn_valid_o, fetch_insn_ready_i)
 602
 603         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 604                        dbg, core_rst,
 605                        fetch_pc_ready_o, fetch_pc_valid_i,
 606                        fetch_insn_valid_o, fetch_insn_ready_i,
 607                        exec_insn_valid_i, exec_insn_ready_o,
 608                        exec_pc_valid_o, exec_pc_ready_i)
 609
 610         self.execute_fsm(m, core, insn_done, pc_changed, sv_changed,
 611                          exec_insn_valid_i, exec_insn_ready_o,
 612                          exec_pc_valid_o, exec_pc_ready_i)
 613
 614         # this bit doesn't have to be in the FSM: connect up to read
 615         # regfiles on demand from DMI
 616         self.do_dmi(m, dbg)
 617
 618         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 619         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 620         self.tb_dec_fsm(m, cur_state.dec)
 621
 622         return m
 623
 624     def do_dmi(self, m, dbg):
 625         comb = m.d.comb
 626         sync = m.d.sync
 627         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 628         intrf = self.core.regs.rf['int']
 629
 630         with m.If(d_reg.req): # request for regfile access being made
 631             # TODO: error-check this
 632             # XXX should this be combinatorial?  sync better?
 633             if intrf.unary:
 634                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 635             else:
 636                 comb += self.int_r.addr.eq(d_reg.addr)
 637                 comb += self.int_r.ren.eq(1)
 638         d_reg_delay  = Signal()
 639         sync += d_reg_delay.eq(d_reg.req)
 640         with m.If(d_reg_delay):
 641             # data arrives one clock later
 642             comb += d_reg.data.eq(self.int_r.data_o)
 643             comb += d_reg.ack.eq(1)
 644
 645         # sigh same thing for CR debug
 646         with m.If(d_cr.req): # request for regfile access being made
 647             comb += self.cr_r.ren.eq(0b11111111) # enable all
 648         d_cr_delay  = Signal()
 649         sync += d_cr_delay.eq(d_cr.req)
 650         with m.If(d_cr_delay):
 651             # data arrives one clock later
 652             comb += d_cr.data.eq(self.cr_r.data_o)
 653             comb += d_cr.ack.eq(1)
 654
 655         # aaand XER...
 656         with m.If(d_xer.req): # request for regfile access being made
 657             comb += self.xer_r.ren.eq(0b111111) # enable all
 658         d_xer_delay  = Signal()
 659         sync += d_xer_delay.eq(d_xer.req)
 660         with m.If(d_xer_delay):
 661             # data arrives one clock later
 662             comb += d_xer.data.eq(self.xer_r.data_o)
 663             comb += d_xer.ack.eq(1)
 664
 665     def tb_dec_fsm(self, m, spr_dec):
 666         """tb_dec_fsm
 667
 668         this is a FSM for updating either dec or tb.  it runs alternately
 669         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 670         value to DEC, however the regfile has "passthrough" on it so this
 671         *should* be ok.
 672
 673         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 674         """
 675
 676         comb, sync = m.d.comb, m.d.sync
 677         fast_rf = self.core.regs.rf['fast']
 678         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 679         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 680
 681         with m.FSM() as fsm:
 682
 683             # initiates read of current DEC
 684             with m.State("DEC_READ"):
 685                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 686                 comb += fast_r_dectb.ren.eq(1)
 687                 m.next = "DEC_WRITE"
 688
 689             # waits for DEC read to arrive (1 cycle), updates with new value
 690             with m.State("DEC_WRITE"):
 691                 new_dec = Signal(64)
 692                 # TODO: MSR.LPCR 32-bit decrement mode
 693                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 694                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 695                 comb += fast_w_dectb.wen.eq(1)
 696                 comb += fast_w_dectb.data_i.eq(new_dec)
 697                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 698                 m.next = "TB_READ"
 699
 700             # initiates read of current TB
 701             with m.State("TB_READ"):
 702                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 703                 comb += fast_r_dectb.ren.eq(1)
 704                 m.next = "TB_WRITE"
 705
 706             # waits for read TB to arrive, initiates write of current TB
 707             with m.State("TB_WRITE"):
 708                 new_tb = Signal(64)
 709                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 710                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 711                 comb += fast_w_dectb.wen.eq(1)
 712                 comb += fast_w_dectb.data_i.eq(new_tb)
 713                 m.next = "DEC_READ"
 714
 715         return m
 716
 717     def __iter__(self):
 718         yield from self.pc_i.ports()
 719         yield self.pc_o
 720         yield self.memerr_o
 721         yield from self.core.ports()
 722         yield from self.imem.ports()
 723         yield self.core_bigendian_i
 724         yield self.busy_o
 725
 726     def ports(self):
 727         return list(self)
 728
 729     def external_ports(self):
 730         ports = self.pc_i.ports()
 731         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 732                 ]
 733
 734         if self.jtag_en:
 735             ports += list(self.jtag.external_ports())
 736         else:
 737             # don't add DMI if JTAG is enabled
 738             ports += list(self.dbg.dmi.ports())
 739
 740         ports += list(self.imem.ibus.fields.values())
 741         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 742
 743         if self.sram4x4k:
 744             for sram in self.sram4k:
 745                 ports += list(sram.bus.fields.values())
 746
 747         if self.xics:
 748             ports += list(self.xics_icp.bus.fields.values())
 749             ports += list(self.xics_ics.bus.fields.values())
 750             ports.append(self.int_level_i)
 751
 752         if self.gpio:
 753             ports += list(self.simple_gpio.bus.fields.values())
 754             ports.append(self.gpio_o)
 755
 756         return ports
 757
 758     def ports(self):
 759         return list(self)
 760
 761
 762 class TestIssuer(Elaboratable):
 763     def __init__(self, pspec):
 764         self.ti = TestIssuerInternal(pspec)
 765
 766         self.pll = DummyPLL()
 767
 768         # PLL direct clock or not
 769         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 770         if self.pll_en:
 771             self.pll_18_o = Signal(reset_less=True)
 772
 773     def elaborate(self, platform):
 774         m = Module()
 775         comb = m.d.comb
 776
 777         # TestIssuer runs at direct clock
 778         m.submodules.ti = ti = self.ti
 779         cd_int = ClockDomain("coresync")
 780
 781         if self.pll_en:
 782             # ClockSelect runs at PLL output internal clock rate
 783             m.submodules.pll = pll = self.pll
 784
 785             # add clock domains from PLL
 786             cd_pll = ClockDomain("pllclk")
 787             m.domains += cd_pll
 788
 789             # PLL clock established.  has the side-effect of running clklsel
 790             # at the PLL's speed (see DomainRenamer("pllclk") above)
 791             pllclk = ClockSignal("pllclk")
 792             comb += pllclk.eq(pll.clk_pll_o)
 793
 794             # wire up external 24mhz to PLL
 795             comb += pll.clk_24_i.eq(ClockSignal())
 796
 797             # output 18 mhz PLL test signal
 798             comb += self.pll_18_o.eq(pll.pll_18_o)
 799
 800             # now wire up ResetSignals.  don't mind them being in this domain
 801             pll_rst = ResetSignal("pllclk")
 802             comb += pll_rst.eq(ResetSignal())
 803
 804         # internal clock is set to selector clock-out.  has the side-effect of
 805         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 806         intclk = ClockSignal("coresync")
 807         if self.pll_en:
 808             comb += intclk.eq(pll.clk_pll_o)
 809         else:
 810             comb += intclk.eq(ClockSignal())
 811
 812         return m
 813
 814     def ports(self):
 815         return list(self.ti.ports()) + list(self.pll.ports()) + \
 816                [ClockSignal(), ResetSignal()]
 817
 818     def external_ports(self):
 819         ports = self.ti.external_ports()
 820         ports.append(ClockSignal())
 821         ports.append(ResetSignal())
 822         if self.pll_en:
 823             ports.append(self.pll.clk_sel_i)
 824             ports.append(self.pll_18_o)
 825             ports.append(self.pll.pll_lck_o)
 826         return ports
 827
 828
 829 if __name__ == '__main__':
 830     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 831              'spr': 1,
 832              'div': 1,
 833              'mul': 1,
 834              'shiftrot': 1
 835             }
 836     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 837                          imem_ifacetype='bare_wb',
 838                          addr_wid=48,
 839                          mask_wid=8,
 840                          reg_wid=64,
 841                          units=units)
 842     dut = TestIssuer(pspec)
 843     vl = main(dut, ports=dut.ports(), name="test_issuer")
 844
 845     if len(sys.argv) == 1:
 846         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 847         with open("test_issuer.il", "w") as f:
 848             f.write(vl)