projects / soc.git / blob
? search:


5101ecb20737f5b6965a9c05d3bdd4b321b892d5
[soc.git] / src / soc / simple / issuer.py
1 """simple core issuer
2
3 not in any way intended for production use. this runs a FSM that:
4
5 * reads the Program Counter from StateRegs
6 * reads an instruction from a fixed-size Test Memory
7 * issues it to the Simple Core
8 * waits for it to complete
9 * increments the PC
10 * does it all over again
11
12 the purpose of this module is to verify the functional correctness
13 of the Function Units in the absolute simplest and clearest possible
14 way, and to at provide something that can be further incrementally
15 improved.
16 """
17
18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
19 ClockDomain, DomainRenamer, Mux, Const, Repl, Cat)
20 from nmigen.cli import rtlil
21 from nmigen.cli import main
22 import sys
23
24 from nmigen.lib.coding import PriorityEncoder
25
26 from soc.decoder.power_decoder import create_pdecode
27 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
28 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
29 from soc.decoder.decode2execute1 import Data
30 from soc.experiment.testmem import TestMemory # test only for instructions
31 from soc.regfile.regfiles import StateRegs, FastRegs
32 from soc.simple.core import NonProductionCore
33 from soc.config.test.test_loadstore import TestMemPspec
34 from soc.config.ifetch import ConfigFetchUnit
35 from soc.decoder.power_enums import (MicrOp, SVP64PredInt, SVP64PredCR,
36 SVP64PredMode)
37 from soc.debug.dmi import CoreDebug, DMIInterface
38 from soc.debug.jtag import JTAG
39 from soc.config.pinouts import get_pinspecs
40 from soc.config.state import CoreState
41 from soc.interrupts.xics import XICS_ICP, XICS_ICS
42 from soc.bus.simple_gpio import SimpleGPIO
43 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
44 from soc.clock.select import ClockSelect
45 from soc.clock.dummypll import DummyPLL
46 from soc.sv.svstate import SVSTATERec
47
48
49 from nmutil.util import rising_edge
50
51 def get_insn(f_instr_o, pc):
52 if f_instr_o.width == 32:
53 return f_instr_o
54 else:
55 # 64-bit: bit 2 of pc decides which word to select
56 return f_instr_o.word_select(pc[2], 32)
57
58 # gets state input or reads from state regfile
59 def state_get(m, state_i, name, regfile, regnum):
60 comb = m.d.comb
61 sync = m.d.sync
62 # read the PC
63 res = Signal(64, reset_less=True, name=name)
64 res_ok_delay = Signal(name="%s_ok_delay" % name)
65 sync += res_ok_delay.eq(~state_i.ok)
66 with m.If(state_i.ok):
67 # incoming override (start from pc_i)
68 comb += res.eq(state_i.data)
69 with m.Else():
70 # otherwise read StateRegs regfile for PC...
71 comb += regfile.ren.eq(1<<regnum)
72 # ... but on a 1-clock delay
73 with m.If(res_ok_delay):
74 comb += res.eq(regfile.data_o)
75 return res
76
77 def get_predint(m, mask, name):
78 """decode SVP64 predicate integer mask field to reg number and invert
79 this is identical to the equivalent function in ISACaller except that
80 it doesn't read the INT directly, it just decodes "what needs to be done"
81 i.e. which INT reg, whether it is shifted and whether it is bit-inverted.
82
83 * all1s is set to indicate that no mask is to be applied.
84 * regread indicates the GPR register number to be read
85 * invert is set to indicate that the register value is to be inverted
86 * unary indicates that the contents of the register is to be shifted 1<<r3
87 """
88 comb = m.d.comb
89 regread = Signal(5, name=name+"regread")
90 invert = Signal(name=name+"invert")
91 unary = Signal(name=name+"unary")
92 all1s = Signal(name=name+"all1s")
93 with m.Switch(mask):
94 with m.Case(SVP64PredInt.ALWAYS.value):
95 comb += all1s.eq(1) # use 0b1111 (all ones)
96 with m.Case(SVP64PredInt.R3_UNARY.value):
97 comb += regread.eq(3)
98 comb += unary.eq(1) # 1<<r3 - shift r3 (single bit)
99 with m.Case(SVP64PredInt.R3.value):
100 comb += regread.eq(3)
101 with m.Case(SVP64PredInt.R3_N.value):
102 comb += regread.eq(3)
103 comb += invert.eq(1)
104 with m.Case(SVP64PredInt.R10.value):
105 comb += regread.eq(10)
106 with m.Case(SVP64PredInt.R10_N.value):
107 comb += regread.eq(10)
108 comb += invert.eq(1)
109 with m.Case(SVP64PredInt.R30.value):
110 comb += regread.eq(30)
111 with m.Case(SVP64PredInt.R30_N.value):
112 comb += regread.eq(30)
113 comb += invert.eq(1)
114 return regread, invert, unary, all1s
115
116 def get_predcr(m, mask, name):
117 """decode SVP64 predicate CR to reg number field and invert status
118 this is identical to _get_predcr in ISACaller
119 """
120 comb = m.d.comb
121 idx = Signal(2, name=name+"idx")
122 invert = Signal(name=name+"crinvert")
123 with m.Switch(mask):
124 with m.Case(SVP64PredCR.LT.value):
125 comb += idx.eq(0)
126 comb += invert.eq(1)
127 with m.Case(SVP64PredCR.GE.value):
128 comb += idx.eq(0)
129 comb += invert.eq(0)
130 with m.Case(SVP64PredCR.GT.value):
131 comb += idx.eq(1)
132 comb += invert.eq(1)
133 with m.Case(SVP64PredCR.LE.value):
134 comb += idx.eq(1)
135 comb += invert.eq(0)
136 with m.Case(SVP64PredCR.EQ.value):
137 comb += idx.eq(2)
138 comb += invert.eq(1)
139 with m.Case(SVP64PredCR.NE.value):
140 comb += idx.eq(1)
141 comb += invert.eq(0)
142 with m.Case(SVP64PredCR.SO.value):
143 comb += idx.eq(3)
144 comb += invert.eq(1)
145 with m.Case(SVP64PredCR.NS.value):
146 comb += idx.eq(3)
147 comb += invert.eq(0)
148 return idx, invert
149
150
151 class TestIssuerInternal(Elaboratable):
152 """TestIssuer - reads instructions from TestMemory and issues them
153
154 efficiency and speed is not the main goal here: functional correctness
155 and code clarity is. optimisations (which almost 100% interfere with
156 easy understanding) come later.
157 """
158 def __init__(self, pspec):
159
160 # test is SVP64 is to be enabled
161 self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
162
163 # and if regfiles are reduced
164 self.regreduce_en = (hasattr(pspec, "regreduce") and
165 (pspec.regreduce == True))
166
167 # JTAG interface. add this right at the start because if it's
168 # added it *modifies* the pspec, by adding enable/disable signals
169 # for parts of the rest of the core
170 self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
171 if self.jtag_en:
172 # XXX MUST keep this up-to-date with litex, and
173 # soc-cocotb-sim, and err.. all needs sorting out, argh
174 subset = ['uart',
175 'mtwi',
176 'eint', 'gpio', 'mspi0',
177 # 'mspi1', - disabled for now
178 # 'pwm', 'sd0', - disabled for now
179 'sdr']
180 self.jtag = JTAG(get_pinspecs(subset=subset))
181 # add signals to pspec to enable/disable icache and dcache
182 # (or data and intstruction wishbone if icache/dcache not included)
183 # https://bugs.libre-soc.org/show_bug.cgi?id=520
184 # TODO: do we actually care if these are not domain-synchronised?
185 # honestly probably not.
186 pspec.wb_icache_en = self.jtag.wb_icache_en
187 pspec.wb_dcache_en = self.jtag.wb_dcache_en
188 self.wb_sram_en = self.jtag.wb_sram_en
189 else:
190 self.wb_sram_en = Const(1)
191
192 # add 4k sram blocks?
193 self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
194 pspec.sram4x4kblock == True)
195 if self.sram4x4k:
196 self.sram4k = []
197 for i in range(4):
198 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
199 features={'err'}))
200
201 # add interrupt controller?
202 self.xics = hasattr(pspec, "xics") and pspec.xics == True
203 if self.xics:
204 self.xics_icp = XICS_ICP()
205 self.xics_ics = XICS_ICS()
206 self.int_level_i = self.xics_ics.int_level_i
207
208 # add GPIO peripheral?
209 self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
210 if self.gpio:
211 self.simple_gpio = SimpleGPIO()
212 self.gpio_o = self.simple_gpio.gpio_o
213
214 # main instruction core. suitable for prototyping / demo only
215 self.core = core = NonProductionCore(pspec)
216
217 # instruction decoder. goes into Trap Record
218 pdecode = create_pdecode()
219 self.cur_state = CoreState("cur") # current state (MSR/PC/SVSTATE)
220 self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
221 opkls=IssuerDecode2ToOperand,
222 svp64_en=self.svp64_en,
223 regreduce_en=self.regreduce_en)
224 if self.svp64_en:
225 self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
226
227 # Test Instruction memory
228 self.imem = ConfigFetchUnit(pspec).fu
229
230 # DMI interface
231 self.dbg = CoreDebug()
232
233 # instruction go/monitor
234 self.pc_o = Signal(64, reset_less=True)
235 self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
236 self.svstate_i = Data(32, "svstate_i") # ditto
237 self.core_bigendian_i = Signal() # TODO: set based on MSR.LE
238 self.busy_o = Signal(reset_less=True)
239 self.memerr_o = Signal(reset_less=True)
240
241 # STATE regfile read /write ports for PC, MSR, SVSTATE
242 staterf = self.core.regs.rf['state']
243 self.state_r_pc = staterf.r_ports['cia'] # PC rd
244 self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
245 self.state_r_msr = staterf.r_ports['msr'] # MSR rd
246 self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
247 self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
248
249 # DMI interface access
250 intrf = self.core.regs.rf['int']
251 crrf = self.core.regs.rf['cr']
252 xerrf = self.core.regs.rf['xer']
253 self.int_r = intrf.r_ports['dmi'] # INT read
254 self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
255 self.xer_r = xerrf.r_ports['full_xer'] # XER read
256
257 if self.svp64_en:
258 # for predication
259 self.int_pred = intrf.r_ports['pred'] # INT predicate read
260 self.cr_pred = crrf.r_ports['cr_pred'] # CR predicate read
261
262 # hack method of keeping an eye on whether branch/trap set the PC
263 self.state_nia = self.core.regs.rf['state'].w_ports['nia']
264 self.state_nia.wen.name = 'state_nia_wen'
265
266 # pulse to synchronize the simulator at instruction end
267 self.insn_done = Signal()
268
269 if self.svp64_en:
270 # store copies of predicate masks
271 self.srcmask = Signal(64)
272 self.dstmask = Signal(64)
273
274 def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
275 fetch_pc_ready_o, fetch_pc_valid_i,
276 fetch_insn_valid_o, fetch_insn_ready_i):
277 """fetch FSM
278
279 this FSM performs fetch of raw instruction data, partial-decodes
280 it 32-bit at a time to detect SVP64 prefixes, and will optionally
281 read a 2nd 32-bit quantity if that occurs.
282 """
283 comb = m.d.comb
284 sync = m.d.sync
285 pdecode2 = self.pdecode2
286 cur_state = self.cur_state
287 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
288
289 msr_read = Signal(reset=1)
290
291 with m.FSM(name='fetch_fsm'):
292
293 # waiting (zzz)
294 with m.State("IDLE"):
295 comb += fetch_pc_ready_o.eq(1)
296 with m.If(fetch_pc_valid_i):
297 # instruction allowed to go: start by reading the PC
298 # capture the PC and also drop it into Insn Memory
299 # we have joined a pair of combinatorial memory
300 # lookups together. this is Generally Bad.
301 comb += self.imem.a_pc_i.eq(pc)
302 comb += self.imem.a_valid_i.eq(1)
303 comb += self.imem.f_valid_i.eq(1)
304 sync += cur_state.pc.eq(pc)
305 sync += cur_state.svstate.eq(svstate) # and svstate
306
307 # initiate read of MSR. arrives one clock later
308 comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
309 sync += msr_read.eq(0)
310
311 m.next = "INSN_READ" # move to "wait for bus" phase
312
313 # dummy pause to find out why simulation is not keeping up
314 with m.State("INSN_READ"):
315 # one cycle later, msr/sv read arrives. valid only once.
316 with m.If(~msr_read):
317 sync += msr_read.eq(1) # yeah don't read it again
318 sync += cur_state.msr.eq(self.state_r_msr.data_o)
319 with m.If(self.imem.f_busy_o): # zzz...
320 # busy: stay in wait-read
321 comb += self.imem.a_valid_i.eq(1)
322 comb += self.imem.f_valid_i.eq(1)
323 with m.Else():
324 # not busy: instruction fetched
325 insn = get_insn(self.imem.f_instr_o, cur_state.pc)
326 if self.svp64_en:
327 svp64 = self.svp64
328 # decode the SVP64 prefix, if any
329 comb += svp64.raw_opcode_in.eq(insn)
330 comb += svp64.bigendian.eq(self.core_bigendian_i)
331 # pass the decoded prefix (if any) to PowerDecoder2
332 sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
333 # remember whether this is a prefixed instruction, so
334 # the FSM can readily loop when VL==0
335 sync += is_svp64_mode.eq(svp64.is_svp64_mode)
336 # calculate the address of the following instruction
337 insn_size = Mux(svp64.is_svp64_mode, 8, 4)
338 sync += nia.eq(cur_state.pc + insn_size)
339 with m.If(~svp64.is_svp64_mode):
340 # with no prefix, store the instruction
341 # and hand it directly to the next FSM
342 sync += dec_opcode_i.eq(insn)
343 m.next = "INSN_READY"
344 with m.Else():
345 # fetch the rest of the instruction from memory
346 comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
347 comb += self.imem.a_valid_i.eq(1)
348 comb += self.imem.f_valid_i.eq(1)
349 m.next = "INSN_READ2"
350 else:
351 # not SVP64 - 32-bit only
352 sync += nia.eq(cur_state.pc + 4)
353 sync += dec_opcode_i.eq(insn)
354 m.next = "INSN_READY"
355
356 with m.State("INSN_READ2"):
357 with m.If(self.imem.f_busy_o): # zzz...
358 # busy: stay in wait-read
359 comb += self.imem.a_valid_i.eq(1)
360 comb += self.imem.f_valid_i.eq(1)
361 with m.Else():
362 # not busy: instruction fetched
363 insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
364 sync += dec_opcode_i.eq(insn)
365 m.next = "INSN_READY"
366 # TODO: probably can start looking at pdecode2.rm_dec
367 # here or maybe even in INSN_READ state, if svp64_mode
368 # detected, in order to trigger - and wait for - the
369 # predicate reading.
370 if self.svp64_en:
371 pmode = pdecode2.rm_dec.predmode
372 """
373 if pmode != SVP64PredMode.ALWAYS.value:
374 fire predicate loading FSM and wait before
375 moving to INSN_READY
376 else:
377 sync += self.srcmask.eq(-1) # set to all 1s
378 sync += self.dstmask.eq(-1) # set to all 1s
379 m.next = "INSN_READY"
380 """
381
382 with m.State("INSN_READY"):
383 # hand over the instruction, to be decoded
384 comb += fetch_insn_valid_o.eq(1)
385 with m.If(fetch_insn_ready_i):
386 m.next = "IDLE"
387
388 def fetch_predicate_fsm(self, m,
389 pred_insn_valid_i, pred_insn_ready_o,
390 pred_mask_valid_o, pred_mask_ready_i):
391 """fetch_predicate_fsm - obtains (constructs in the case of CR)
392 src/dest predicate masks
393
394 https://bugs.libre-soc.org/show_bug.cgi?id=617
395 the predicates can be read here, by using IntRegs r_ports['pred']
396 or CRRegs r_ports['pred']. in the case of CRs it will have to
397 be done through multiple reads, extracting one relevant at a time.
398 later, a faster way would be to use the 32-bit-wide CR port but
399 this is more complex decoding, here. equivalent code used in
400 ISACaller is "from soc.decoder.isa.caller import get_predcr"
401
402 note: this ENTIRE FSM is not to be called when svp64 is disabled
403 """
404 comb = m.d.comb
405 sync = m.d.sync
406 pdecode2 = self.pdecode2
407 rm_dec = pdecode2.rm_dec # SVP64RMModeDecode
408 predmode = rm_dec.predmode
409 srcpred, dstpred = rm_dec.srcpred, rm_dec.dstpred
410 cr_pred, int_pred = self.cr_pred, self.int_pred # read regfiles
411
412 # elif predmode == CR:
413 # CR-src sidx, sinvert = get_predcr(m, srcpred)
414 # CR-dst didx, dinvert = get_predcr(m, dstpred)
415 # TODO read CR-src and CR-dst into self.srcmask+dstmask with loop
416 # has to cope with first one then the other
417 # for cr_idx = FSM-state-loop(0..VL-1):
418 # FSM-state-trigger-CR-read:
419 # cr_ren = (1<<7-(cr_idx+SVP64CROffs.CRPred))
420 # comb += cr_pred.ren.eq(cr_ren)
421 # FSM-state-1-clock-later-actual-Read:
422 # cr_field = Signal(4)
423 # cr_bit = Signal(1)
424 # # read the CR field, select the appropriate bit
425 # comb += cr_field.eq(cr_pred.data_o)
426 # comb += cr_bit.eq(cr_field.bit_select(idx)))
427 # # just like in branch BO tests
428 # comd += self.srcmask[cr_idx].eq(inv ^ cr_bit)
429
430 # decode predicates
431 sregread, sinvert, sunary, sall1s = get_predint(m, srcpred, 's')
432 dregread, dinvert, dunary, dall1s = get_predint(m, dstpred, 'd')
433 sidx, scrinvert = get_predcr(m, srcpred, 's')
434 didx, dcrinvert = get_predcr(m, dstpred, 'd')
435
436 with m.FSM(name="fetch_predicate"):
437
438 with m.State("FETCH_PRED_IDLE"):
439 comb += pred_insn_ready_o.eq(1)
440 with m.If(pred_insn_valid_i):
441 with m.If(predmode == SVP64PredMode.INT):
442 # skip fetching destination mask register, when zero
443 with m.If(dall1s):
444 sync += self.dstmask.eq(-1)
445 # directly go to fetch source mask register
446 # guaranteed not to be zero (otherwise predmode
447 # would be SVP64PredMode.ALWAYS, not INT)
448 comb += int_pred.addr.eq(sregread)
449 comb += int_pred.ren.eq(1)
450 m.next = "INT_SRC_READ"
451 # fetch destination predicate register
452 with m.Else():
453 comb += int_pred.addr.eq(dregread)
454 comb += int_pred.ren.eq(1)
455 m.next = "INT_DST_READ"
456 with m.Else():
457 sync += self.srcmask.eq(-1)
458 sync += self.dstmask.eq(-1)
459 m.next = "FETCH_PRED_DONE"
460
461 with m.State("INT_DST_READ"):
462 # store destination mask
463 inv = Repl(dinvert, 64)
464 sync += self.dstmask.eq(self.int_pred.data_o ^ inv)
465 # skip fetching source mask register, when zero
466 with m.If(sall1s):
467 sync += self.srcmask.eq(-1)
468 m.next = "FETCH_PRED_DONE"
469 # fetch source predicate register
470 with m.Else():
471 comb += int_pred.addr.eq(sregread)
472 comb += int_pred.ren.eq(1)
473 m.next = "INT_SRC_READ"
474
475 with m.State("INT_SRC_READ"):
476 # store source mask
477 inv = Repl(sinvert, 64)
478 sync += self.srcmask.eq(self.int_pred.data_o ^ inv)
479 m.next = "FETCH_PRED_DONE"
480
481 with m.State("FETCH_PRED_DONE"):
482 comb += pred_mask_valid_o.eq(1)
483 with m.If(pred_mask_ready_i):
484 m.next = "FETCH_PRED_IDLE"
485
486 def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
487 dbg, core_rst, is_svp64_mode,
488 fetch_pc_ready_o, fetch_pc_valid_i,
489 fetch_insn_valid_o, fetch_insn_ready_i,
490 pred_insn_valid_i, pred_insn_ready_o,
491 pred_mask_valid_o, pred_mask_ready_i,
492 exec_insn_valid_i, exec_insn_ready_o,
493 exec_pc_valid_o, exec_pc_ready_i):
494 """issue FSM
495
496 decode / issue FSM. this interacts with the "fetch" FSM
497 through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
498 (outgoing). also interacts with the "execute" FSM
499 through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
500 (incoming).
501 SVP64 RM prefixes have already been set up by the
502 "fetch" phase, so execute is fairly straightforward.
503 """
504
505 comb = m.d.comb
506 sync = m.d.sync
507 pdecode2 = self.pdecode2
508 cur_state = self.cur_state
509
510 # temporaries
511 dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
512
513 # for updating svstate (things like srcstep etc.)
514 update_svstate = Signal() # set this (below) if updating
515 new_svstate = SVSTATERec("new_svstate")
516 comb += new_svstate.eq(cur_state.svstate)
517
518 # precalculate srcstep+1 and dststep+1
519 cur_srcstep = cur_state.svstate.srcstep
520 cur_dststep = cur_state.svstate.dststep
521 next_srcstep = Signal.like(cur_srcstep)
522 next_dststep = Signal.like(cur_dststep)
523 comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
524 comb += next_dststep.eq(cur_state.svstate.dststep+1)
525
526 with m.FSM(name="issue_fsm"):
527
528 # sync with the "fetch" phase which is reading the instruction
529 # at this point, there is no instruction running, that
530 # could inadvertently update the PC.
531 with m.State("ISSUE_START"):
532 # wait on "core stop" release, before next fetch
533 # need to do this here, in case we are in a VL==0 loop
534 with m.If(~dbg.core_stop_o & ~core_rst):
535 comb += fetch_pc_valid_i.eq(1) # tell fetch to start
536 with m.If(fetch_pc_ready_o): # fetch acknowledged us
537 m.next = "INSN_WAIT"
538 with m.Else():
539 # tell core it's stopped, and acknowledge debug handshake
540 comb += core.core_stopped_i.eq(1)
541 comb += dbg.core_stopped_i.eq(1)
542 # while stopped, allow updating the PC and SVSTATE
543 with m.If(self.pc_i.ok):
544 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
545 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
546 sync += pc_changed.eq(1)
547 with m.If(self.svstate_i.ok):
548 comb += new_svstate.eq(self.svstate_i.data)
549 comb += update_svstate.eq(1)
550 sync += sv_changed.eq(1)
551
552 # wait for an instruction to arrive from Fetch
553 with m.State("INSN_WAIT"):
554 comb += fetch_insn_ready_i.eq(1)
555 with m.If(fetch_insn_valid_o):
556 # loop into ISSUE_START if it's a SVP64 instruction
557 # and VL == 0. this because VL==0 is a for-loop
558 # from 0 to 0 i.e. always, always a NOP.
559 cur_vl = cur_state.svstate.vl
560 with m.If(is_svp64_mode & (cur_vl == 0)):
561 # update the PC before fetching the next instruction
562 # since we are in a VL==0 loop, no instruction was
563 # executed that we could be overwriting
564 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
565 comb += self.state_w_pc.data_i.eq(nia)
566 comb += self.insn_done.eq(1)
567 m.next = "ISSUE_START"
568 with m.Else():
569 if self.svp64_en:
570 m.next = "PRED_START" # start fetching predicate
571 else:
572 m.next = "DECODE_SV" # skip predication
573
574 with m.State("PRED_START"):
575 comb += pred_insn_valid_i.eq(1) # tell fetch_pred to start
576 with m.If(pred_insn_ready_o): # fetch_pred acknowledged us
577 m.next = "MASK_WAIT"
578
579 with m.State("MASK_WAIT"):
580 comb += pred_mask_ready_i.eq(1) # ready to receive the masks
581 with m.If(pred_mask_valid_o): # predication masks are ready
582 m.next = "PRED_SKIP"
583
584 # skip zeros in predicate
585 with m.State("PRED_SKIP"):
586 with m.If(~is_svp64_mode):
587 m.next = "DECODE_SV" # nothing to do
588 with m.Else():
589 if self.svp64_en:
590 pred_src_zero = pdecode2.rm_dec.pred_sz
591 pred_dst_zero = pdecode2.rm_dec.pred_dz
592
593 # new srcstep, after skipping zeros
594 skip_srcstep = Signal.like(cur_srcstep)
595 # value to be added to the current srcstep
596 src_delta = Signal.like(cur_srcstep)
597 # add leading zeros to srcstep, if not in zero mode
598 with m.If(~pred_src_zero):
599 # priority encoder (count leading zeros)
600 # append guard bit, in case the mask is all zeros
601 pri_enc_src = PriorityEncoder(65)
602 m.submodules.pri_enc_src = pri_enc_src
603 comb += pri_enc_src.i.eq(Cat(self.srcmask,
604 Const(1, 1)))
605 comb += src_delta.eq(pri_enc_src.o)
606 # apply delta to srcstep
607 comb += skip_srcstep.eq(cur_srcstep + src_delta)
608 # shift-out all leading zeros from the mask
609 # plus the leading "one" bit
610 sync += self.srcmask.eq(self.srcmask >> (src_delta+1))
611
612 # same as above, but for dststep
613 skip_dststep = Signal.like(cur_dststep)
614 dst_delta = Signal.like(cur_dststep)
615 with m.If(~pred_dst_zero):
616 pri_enc_dst = PriorityEncoder(65)
617 m.submodules.pri_enc_dst = pri_enc_dst
618 comb += pri_enc_dst.i.eq(Cat(self.dstmask,
619 Const(1, 1)))
620 comb += dst_delta.eq(pri_enc_dst.o)
621 comb += skip_dststep.eq(cur_dststep + dst_delta)
622 sync += self.dstmask.eq(self.dstmask >> (dst_delta+1))
623
624 # TODO: initialize mask[VL]=1 to avoid passing past VL
625 with m.If((skip_srcstep >= cur_vl) |
626 (skip_dststep >= cur_vl)):
627 # end of VL loop. Update PC and reset src/dst step
628 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
629 comb += self.state_w_pc.data_i.eq(nia)
630 comb += new_svstate.srcstep.eq(0)
631 comb += new_svstate.dststep.eq(0)
632 comb += update_svstate.eq(1)
633 # synchronize with the simulator
634 comb += self.insn_done.eq(1)
635 # go back to Issue
636 m.next = "ISSUE_START"
637 with m.Else():
638 # update new src/dst step
639 comb += new_svstate.srcstep.eq(skip_srcstep)
640 comb += new_svstate.dststep.eq(skip_dststep)
641 comb += update_svstate.eq(1)
642 # proceed to Decode
643 m.next = "DECODE_SV"
644
645 # after src/dst step have been updated, we are ready
646 # to decode the instruction
647 with m.State("DECODE_SV"):
648 # decode the instruction
649 sync += core.e.eq(pdecode2.e)
650 sync += core.state.eq(cur_state)
651 sync += core.raw_insn_i.eq(dec_opcode_i)
652 sync += core.bigendian_i.eq(self.core_bigendian_i)
653 # set RA_OR_ZERO detection in satellite decoders
654 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
655 m.next = "INSN_EXECUTE" # move to "execute"
656
657 # handshake with execution FSM, move to "wait" once acknowledged
658 with m.State("INSN_EXECUTE"):
659 comb += exec_insn_valid_i.eq(1) # trigger execute
660 with m.If(exec_insn_ready_o): # execute acknowledged us
661 m.next = "EXECUTE_WAIT"
662
663 with m.State("EXECUTE_WAIT"):
664 # wait on "core stop" release, at instruction end
665 # need to do this here, in case we are in a VL>1 loop
666 with m.If(~dbg.core_stop_o & ~core_rst):
667 comb += exec_pc_ready_i.eq(1)
668 with m.If(exec_pc_valid_o):
669
670 # was this the last loop iteration?
671 is_last = Signal()
672 cur_vl = cur_state.svstate.vl
673 comb += is_last.eq(next_srcstep == cur_vl)
674
675 # if either PC or SVSTATE were changed by the previous
676 # instruction, go directly back to Fetch, without
677 # updating either PC or SVSTATE
678 with m.If(pc_changed | sv_changed):
679 m.next = "ISSUE_START"
680
681 # also return to Fetch, when no output was a vector
682 # (regardless of SRCSTEP and VL), or when the last
683 # instruction was really the last one of the VL loop
684 with m.Elif((~pdecode2.loop_continue) | is_last):
685 # before going back to fetch, update the PC state
686 # register with the NIA.
687 # ok here we are not reading the branch unit.
688 # TODO: this just blithely overwrites whatever
689 # pipeline updated the PC
690 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
691 comb += self.state_w_pc.data_i.eq(nia)
692 # reset SRCSTEP before returning to Fetch
693 if self.svp64_en:
694 with m.If(pdecode2.loop_continue):
695 comb += new_svstate.srcstep.eq(0)
696 comb += new_svstate.dststep.eq(0)
697 comb += update_svstate.eq(1)
698 else:
699 comb += new_svstate.srcstep.eq(0)
700 comb += new_svstate.dststep.eq(0)
701 comb += update_svstate.eq(1)
702 m.next = "ISSUE_START"
703
704 # returning to Execute? then, first update SRCSTEP
705 with m.Else():
706 comb += new_svstate.srcstep.eq(next_srcstep)
707 comb += new_svstate.dststep.eq(next_dststep)
708 comb += update_svstate.eq(1)
709 # return to mask skip loop
710 m.next = "PRED_SKIP"
711
712 with m.Else():
713 comb += core.core_stopped_i.eq(1)
714 comb += dbg.core_stopped_i.eq(1)
715 # while stopped, allow updating the PC and SVSTATE
716 with m.If(self.pc_i.ok):
717 comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
718 comb += self.state_w_pc.data_i.eq(self.pc_i.data)
719 sync += pc_changed.eq(1)
720 with m.If(self.svstate_i.ok):
721 comb += new_svstate.eq(self.svstate_i.data)
722 comb += update_svstate.eq(1)
723 sync += sv_changed.eq(1)
724
725 # check if svstate needs updating: if so, write it to State Regfile
726 with m.If(update_svstate):
727 comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
728 comb += self.state_w_sv.data_i.eq(new_svstate)
729 sync += cur_state.svstate.eq(new_svstate) # for next clock
730
731 def execute_fsm(self, m, core, pc_changed, sv_changed,
732 exec_insn_valid_i, exec_insn_ready_o,
733 exec_pc_valid_o, exec_pc_ready_i):
734 """execute FSM
735
736 execute FSM. this interacts with the "issue" FSM
737 through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
738 (outgoing). SVP64 RM prefixes have already been set up by the
739 "issue" phase, so execute is fairly straightforward.
740 """
741
742 comb = m.d.comb
743 sync = m.d.sync
744 pdecode2 = self.pdecode2
745
746 # temporaries
747 core_busy_o = core.busy_o # core is busy
748 core_ivalid_i = core.ivalid_i # instruction is valid
749 core_issue_i = core.issue_i # instruction is issued
750 insn_type = core.e.do.insn_type # instruction MicroOp type
751
752 with m.FSM(name="exec_fsm"):
753
754 # waiting for instruction bus (stays there until not busy)
755 with m.State("INSN_START"):
756 comb += exec_insn_ready_o.eq(1)
757 with m.If(exec_insn_valid_i):
758 comb += core_ivalid_i.eq(1) # instruction is valid
759 comb += core_issue_i.eq(1) # and issued
760 sync += sv_changed.eq(0)
761 sync += pc_changed.eq(0)
762 m.next = "INSN_ACTIVE" # move to "wait completion"
763
764 # instruction started: must wait till it finishes
765 with m.State("INSN_ACTIVE"):
766 with m.If(insn_type != MicrOp.OP_NOP):
767 comb += core_ivalid_i.eq(1) # instruction is valid
768 # note changes to PC and SVSTATE
769 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
770 sync += sv_changed.eq(1)
771 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
772 sync += pc_changed.eq(1)
773 with m.If(~core_busy_o): # instruction done!
774 comb += exec_pc_valid_o.eq(1)
775 with m.If(exec_pc_ready_i):
776 comb += self.insn_done.eq(1)
777 m.next = "INSN_START" # back to fetch
778
779 def setup_peripherals(self, m):
780 comb, sync = m.d.comb, m.d.sync
781
782 m.submodules.core = core = DomainRenamer("coresync")(self.core)
783 m.submodules.imem = imem = self.imem
784 m.submodules.dbg = dbg = self.dbg
785 if self.jtag_en:
786 m.submodules.jtag = jtag = self.jtag
787 # TODO: UART2GDB mux, here, from external pin
788 # see https://bugs.libre-soc.org/show_bug.cgi?id=499
789 sync += dbg.dmi.connect_to(jtag.dmi)
790
791 cur_state = self.cur_state
792
793 # 4x 4k SRAM blocks. these simply "exist", they get routed in litex
794 if self.sram4x4k:
795 for i, sram in enumerate(self.sram4k):
796 m.submodules["sram4k_%d" % i] = sram
797 comb += sram.enable.eq(self.wb_sram_en)
798
799 # XICS interrupt handler
800 if self.xics:
801 m.submodules.xics_icp = icp = self.xics_icp
802 m.submodules.xics_ics = ics = self.xics_ics
803 comb += icp.ics_i.eq(ics.icp_o) # connect ICS to ICP
804 sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
805
806 # GPIO test peripheral
807 if self.gpio:
808 m.submodules.simple_gpio = simple_gpio = self.simple_gpio
809
810 # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
811 # XXX causes litex ECP5 test to get wrong idea about input and output
812 # (but works with verilator sim *sigh*)
813 #if self.gpio and self.xics:
814 # comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
815
816 # instruction decoder
817 pdecode = create_pdecode()
818 m.submodules.dec2 = pdecode2 = self.pdecode2
819 if self.svp64_en:
820 m.submodules.svp64 = svp64 = self.svp64
821
822 # convenience
823 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
824 intrf = self.core.regs.rf['int']
825
826 # clock delay power-on reset
827 cd_por = ClockDomain(reset_less=True)
828 cd_sync = ClockDomain()
829 core_sync = ClockDomain("coresync")
830 m.domains += cd_por, cd_sync, core_sync
831
832 ti_rst = Signal(reset_less=True)
833 delay = Signal(range(4), reset=3)
834 with m.If(delay != 0):
835 m.d.por += delay.eq(delay - 1)
836 comb += cd_por.clk.eq(ClockSignal())
837
838 # power-on reset delay
839 core_rst = ResetSignal("coresync")
840 comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
841 comb += core_rst.eq(ti_rst)
842
843 # busy/halted signals from core
844 comb += self.busy_o.eq(core.busy_o)
845 comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
846
847 # temporary hack: says "go" immediately for both address gen and ST
848 l0 = core.l0
849 ldst = core.fus.fus['ldst0']
850 st_go_edge = rising_edge(m, ldst.st.rel_o)
851 m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
852 m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
853
854 return core_rst
855
856 def elaborate(self, platform):
857 m = Module()
858 # convenience
859 comb, sync = m.d.comb, m.d.sync
860 cur_state = self.cur_state
861 pdecode2 = self.pdecode2
862 dbg = self.dbg
863 core = self.core
864
865 # set up peripherals and core
866 core_rst = self.setup_peripherals(m)
867
868 # PC and instruction from I-Memory
869 comb += self.pc_o.eq(cur_state.pc)
870 pc_changed = Signal() # note write to PC
871 sv_changed = Signal() # note write to SVSTATE
872
873 # read state either from incoming override or from regfile
874 # TODO: really should be doing MSR in the same way
875 pc = state_get(m, self.pc_i, "pc", # read PC
876 self.state_r_pc, StateRegs.PC)
877 svstate = state_get(m, self.svstate_i, "svstate", # read SVSTATE
878 self.state_r_sv, StateRegs.SVSTATE)
879
880 # don't write pc every cycle
881 comb += self.state_w_pc.wen.eq(0)
882 comb += self.state_w_pc.data_i.eq(0)
883
884 # don't read msr every cycle
885 comb += self.state_r_msr.ren.eq(0)
886
887 # address of the next instruction, in the absence of a branch
888 # depends on the instruction size
889 nia = Signal(64, reset_less=True)
890
891 # connect up debug signals
892 # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
893 comb += dbg.terminate_i.eq(core.core_terminate_o)
894 comb += dbg.state.pc.eq(pc)
895 comb += dbg.state.svstate.eq(svstate)
896 comb += dbg.state.msr.eq(cur_state.msr)
897
898 # pass the prefix mode from Fetch to Issue, so the latter can loop
899 # on VL==0
900 is_svp64_mode = Signal()
901
902 # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
903 # these are the handshake signals between fetch and decode/execute
904
905 # fetch FSM can run as soon as the PC is valid
906 fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
907 fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
908
909 # fetch FSM hands over the instruction to be decoded / issued
910 fetch_insn_valid_o = Signal()
911 fetch_insn_ready_i = Signal()
912
913 # predicate fetch FSM decodes and fetches the predicate
914 pred_insn_valid_i = Signal()
915 pred_insn_ready_o = Signal()
916
917 # predicate fetch FSM delivers the masks
918 pred_mask_valid_o = Signal()
919 pred_mask_ready_i = Signal()
920
921 # issue FSM delivers the instruction to the be executed
922 exec_insn_valid_i = Signal()
923 exec_insn_ready_o = Signal()
924
925 # execute FSM, hands over the PC/SVSTATE back to the issue FSM
926 exec_pc_valid_o = Signal()
927 exec_pc_ready_i = Signal()
928
929 # the FSMs here are perhaps unusual in that they detect conditions
930 # then "hold" information, combinatorially, for the core
931 # (as opposed to using sync - which would be on a clock's delay)
932 # this includes the actual opcode, valid flags and so on.
933
934 # Fetch, then predicate fetch, then Issue, then Execute.
935 # Issue is where the VL for-loop # lives. the ready/valid
936 # signalling is used to communicate between the four.
937
938 self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
939 fetch_pc_ready_o, fetch_pc_valid_i,
940 fetch_insn_valid_o, fetch_insn_ready_i)
941
942 self.issue_fsm(m, core, pc_changed, sv_changed, nia,
943 dbg, core_rst, is_svp64_mode,
944 fetch_pc_ready_o, fetch_pc_valid_i,
945 fetch_insn_valid_o, fetch_insn_ready_i,
946 pred_insn_valid_i, pred_insn_ready_o,
947 pred_mask_valid_o, pred_mask_ready_i,
948 exec_insn_valid_i, exec_insn_ready_o,
949 exec_pc_valid_o, exec_pc_ready_i)
950
951 if self.svp64_en:
952 self.fetch_predicate_fsm(m,
953 pred_insn_valid_i, pred_insn_ready_o,
954 pred_mask_valid_o, pred_mask_ready_i)
955
956 self.execute_fsm(m, core, pc_changed, sv_changed,
957 exec_insn_valid_i, exec_insn_ready_o,
958 exec_pc_valid_o, exec_pc_ready_i)
959
960 # this bit doesn't have to be in the FSM: connect up to read
961 # regfiles on demand from DMI
962 self.do_dmi(m, dbg)
963
964 # DEC and TB inc/dec FSM. copy of DEC is put into CoreState,
965 # (which uses that in PowerDecoder2 to raise 0x900 exception)
966 self.tb_dec_fsm(m, cur_state.dec)
967
968 return m
969
970 def do_dmi(self, m, dbg):
971 """deals with DMI debug requests
972
973 currently only provides read requests for the INT regfile, CR and XER
974 it will later also deal with *writing* to these regfiles.
975 """
976 comb = m.d.comb
977 sync = m.d.sync
978 dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
979 intrf = self.core.regs.rf['int']
980
981 with m.If(d_reg.req): # request for regfile access being made
982 # TODO: error-check this
983 # XXX should this be combinatorial? sync better?
984 if intrf.unary:
985 comb += self.int_r.ren.eq(1<<d_reg.addr)
986 else:
987 comb += self.int_r.addr.eq(d_reg.addr)
988 comb += self.int_r.ren.eq(1)
989 d_reg_delay = Signal()
990 sync += d_reg_delay.eq(d_reg.req)
991 with m.If(d_reg_delay):
992 # data arrives one clock later
993 comb += d_reg.data.eq(self.int_r.data_o)
994 comb += d_reg.ack.eq(1)
995
996 # sigh same thing for CR debug
997 with m.If(d_cr.req): # request for regfile access being made
998 comb += self.cr_r.ren.eq(0b11111111) # enable all
999 d_cr_delay = Signal()
1000 sync += d_cr_delay.eq(d_cr.req)
1001 with m.If(d_cr_delay):
1002 # data arrives one clock later
1003 comb += d_cr.data.eq(self.cr_r.data_o)
1004 comb += d_cr.ack.eq(1)
1005
1006 # aaand XER...
1007 with m.If(d_xer.req): # request for regfile access being made
1008 comb += self.xer_r.ren.eq(0b111111) # enable all
1009 d_xer_delay = Signal()
1010 sync += d_xer_delay.eq(d_xer.req)
1011 with m.If(d_xer_delay):
1012 # data arrives one clock later
1013 comb += d_xer.data.eq(self.xer_r.data_o)
1014 comb += d_xer.ack.eq(1)
1015
1016 def tb_dec_fsm(self, m, spr_dec):
1017 """tb_dec_fsm
1018
1019 this is a FSM for updating either dec or tb. it runs alternately
1020 DEC, TB, DEC, TB. note that SPR pipeline could have written a new
1021 value to DEC, however the regfile has "passthrough" on it so this
1022 *should* be ok.
1023
1024 see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
1025 """
1026
1027 comb, sync = m.d.comb, m.d.sync
1028 fast_rf = self.core.regs.rf['fast']
1029 fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
1030 fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
1031
1032 with m.FSM() as fsm:
1033
1034 # initiates read of current DEC
1035 with m.State("DEC_READ"):
1036 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
1037 comb += fast_r_dectb.ren.eq(1)
1038 m.next = "DEC_WRITE"
1039
1040 # waits for DEC read to arrive (1 cycle), updates with new value
1041 with m.State("DEC_WRITE"):
1042 new_dec = Signal(64)
1043 # TODO: MSR.LPCR 32-bit decrement mode
1044 comb += new_dec.eq(fast_r_dectb.data_o - 1)
1045 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
1046 comb += fast_w_dectb.wen.eq(1)
1047 comb += fast_w_dectb.data_i.eq(new_dec)
1048 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
1049 m.next = "TB_READ"
1050
1051 # initiates read of current TB
1052 with m.State("TB_READ"):
1053 comb += fast_r_dectb.addr.eq(FastRegs.TB)
1054 comb += fast_r_dectb.ren.eq(1)
1055 m.next = "TB_WRITE"
1056
1057 # waits for read TB to arrive, initiates write of current TB
1058 with m.State("TB_WRITE"):
1059 new_tb = Signal(64)
1060 comb += new_tb.eq(fast_r_dectb.data_o + 1)
1061 comb += fast_w_dectb.addr.eq(FastRegs.TB)
1062 comb += fast_w_dectb.wen.eq(1)
1063 comb += fast_w_dectb.data_i.eq(new_tb)
1064 m.next = "DEC_READ"
1065
1066 return m
1067
1068 def __iter__(self):
1069 yield from self.pc_i.ports()
1070 yield self.pc_o
1071 yield self.memerr_o
1072 yield from self.core.ports()
1073 yield from self.imem.ports()
1074 yield self.core_bigendian_i
1075 yield self.busy_o
1076
1077 def ports(self):
1078 return list(self)
1079
1080 def external_ports(self):
1081 ports = self.pc_i.ports()
1082 ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
1083 ]
1084
1085 if self.jtag_en:
1086 ports += list(self.jtag.external_ports())
1087 else:
1088 # don't add DMI if JTAG is enabled
1089 ports += list(self.dbg.dmi.ports())
1090
1091 ports += list(self.imem.ibus.fields.values())
1092 ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
1093
1094 if self.sram4x4k:
1095 for sram in self.sram4k:
1096 ports += list(sram.bus.fields.values())
1097
1098 if self.xics:
1099 ports += list(self.xics_icp.bus.fields.values())
1100 ports += list(self.xics_ics.bus.fields.values())
1101 ports.append(self.int_level_i)
1102
1103 if self.gpio:
1104 ports += list(self.simple_gpio.bus.fields.values())
1105 ports.append(self.gpio_o)
1106
1107 return ports
1108
1109 def ports(self):
1110 return list(self)
1111
1112
1113 class TestIssuer(Elaboratable):
1114 def __init__(self, pspec):
1115 self.ti = TestIssuerInternal(pspec)
1116
1117 self.pll = DummyPLL()
1118
1119 # PLL direct clock or not
1120 self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
1121 if self.pll_en:
1122 self.pll_18_o = Signal(reset_less=True)
1123
1124 def elaborate(self, platform):
1125 m = Module()
1126 comb = m.d.comb
1127
1128 # TestIssuer runs at direct clock
1129 m.submodules.ti = ti = self.ti
1130 cd_int = ClockDomain("coresync")
1131
1132 if self.pll_en:
1133 # ClockSelect runs at PLL output internal clock rate
1134 m.submodules.pll = pll = self.pll
1135
1136 # add clock domains from PLL
1137 cd_pll = ClockDomain("pllclk")
1138 m.domains += cd_pll
1139
1140 # PLL clock established. has the side-effect of running clklsel
1141 # at the PLL's speed (see DomainRenamer("pllclk") above)
1142 pllclk = ClockSignal("pllclk")
1143 comb += pllclk.eq(pll.clk_pll_o)
1144
1145 # wire up external 24mhz to PLL
1146 comb += pll.clk_24_i.eq(ClockSignal())
1147
1148 # output 18 mhz PLL test signal
1149 comb += self.pll_18_o.eq(pll.pll_18_o)
1150
1151 # now wire up ResetSignals. don't mind them being in this domain
1152 pll_rst = ResetSignal("pllclk")
1153 comb += pll_rst.eq(ResetSignal())
1154
1155 # internal clock is set to selector clock-out. has the side-effect of
1156 # running TestIssuer at this speed (see DomainRenamer("intclk") above)
1157 intclk = ClockSignal("coresync")
1158 if self.pll_en:
1159 comb += intclk.eq(pll.clk_pll_o)
1160 else:
1161 comb += intclk.eq(ClockSignal())
1162
1163 return m
1164
1165 def ports(self):
1166 return list(self.ti.ports()) + list(self.pll.ports()) + \
1167 [ClockSignal(), ResetSignal()]
1168
1169 def external_ports(self):
1170 ports = self.ti.external_ports()
1171 ports.append(ClockSignal())
1172 ports.append(ResetSignal())
1173 if self.pll_en:
1174 ports.append(self.pll.clk_sel_i)
1175 ports.append(self.pll_18_o)
1176 ports.append(self.pll.pll_lck_o)
1177 return ports
1178
1179
1180 if __name__ == '__main__':
1181 units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
1182 'spr': 1,
1183 'div': 1,
1184 'mul': 1,
1185 'shiftrot': 1
1186 }
1187 pspec = TestMemPspec(ldst_ifacetype='bare_wb',
1188 imem_ifacetype='bare_wb',
1189 addr_wid=48,
1190 mask_wid=8,
1191 reg_wid=64,
1192 units=units)
1193 dut = TestIssuer(pspec)
1194 vl = main(dut, ports=dut.ports(), name="test_issuer")
1195
1196 if len(sys.argv) == 1:
1197 vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
1198 with open("test_issuer.il", "w") as f:
1199 f.write(vl)