src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # test is SVP64 is to be enabled
  64         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
  65
  66         # JTAG interface.  add this right at the start because if it's
  67         # added it *modifies* the pspec, by adding enable/disable signals
  68         # for parts of the rest of the core
  69         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  70         if self.jtag_en:
  71             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  72                       'pwm', 'sd0', 'sdr'}
  73             self.jtag = JTAG(get_pinspecs(subset=subset))
  74             # add signals to pspec to enable/disable icache and dcache
  75             # (or data and intstruction wishbone if icache/dcache not included)
  76             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  77             # TODO: do we actually care if these are not domain-synchronised?
  78             # honestly probably not.
  79             pspec.wb_icache_en = self.jtag.wb_icache_en
  80             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  81             self.wb_sram_en = self.jtag.wb_sram_en
  82         else:
  83             self.wb_sram_en = Const(1)
  84
  85         # add 4k sram blocks?
  86         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  87                          pspec.sram4x4kblock == True)
  88         if self.sram4x4k:
  89             self.sram4k = []
  90             for i in range(4):
  91                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  92                                                     features={'err'}))
  93
  94         # add interrupt controller?
  95         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  96         if self.xics:
  97             self.xics_icp = XICS_ICP()
  98             self.xics_ics = XICS_ICS()
  99             self.int_level_i = self.xics_ics.int_level_i
 100
 101         # add GPIO peripheral?
 102         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 103         if self.gpio:
 104             self.simple_gpio = SimpleGPIO()
 105             self.gpio_o = self.simple_gpio.gpio_o
 106
 107         # main instruction core25
 108         self.core = core = NonProductionCore(pspec)
 109
 110         # instruction decoder.  goes into Trap Record
 111         pdecode = create_pdecode()
 112         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 113         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 114                                      opkls=IssuerDecode2ToOperand,
 115                                      svp64_en=self.svp64_en)
 116         if self.svp64_en:
 117             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 118
 119         # Test Instruction memory
 120         self.imem = ConfigFetchUnit(pspec).fu
 121         # one-row cache of instruction read
 122         self.iline = Signal(64) # one instruction line
 123         self.iprev_adr = Signal(64) # previous address: if different, do read
 124
 125         # DMI interface
 126         self.dbg = CoreDebug()
 127
 128         # instruction go/monitor
 129         self.pc_o = Signal(64, reset_less=True)
 130         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 131         self.svstate_i = Data(32, "svstate_i") # ditto
 132         self.core_bigendian_i = Signal()
 133         self.busy_o = Signal(reset_less=True)
 134         self.memerr_o = Signal(reset_less=True)
 135
 136         # STATE regfile read /write ports for PC, MSR, SVSTATE
 137         staterf = self.core.regs.rf['state']
 138         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 139         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 140         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 141         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 142         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 143
 144         # DMI interface access
 145         intrf = self.core.regs.rf['int']
 146         crrf = self.core.regs.rf['cr']
 147         xerrf = self.core.regs.rf['xer']
 148         self.int_r = intrf.r_ports['dmi'] # INT read
 149         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 150         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 151
 152         # hack method of keeping an eye on whether branch/trap set the PC
 153         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 154         self.state_nia.wen.name = 'state_nia_wen'
 155
 156     def fetch_fsm(self, m, core, pc, svstate, nia,
 157                         fetch_pc_ready_o, fetch_pc_valid_i,
 158                         fetch_insn_valid_o, fetch_insn_ready_i):
 159         """fetch FSM
 160         this FSM performs fetch of raw instruction data, partial-decodes
 161         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 162         read a 2nd 32-bit quantity if that occurs.
 163         """
 164         comb = m.d.comb
 165         sync = m.d.sync
 166         pdecode2 = self.pdecode2
 167         cur_state = self.cur_state
 168         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 169
 170         msr_read = Signal(reset=1)
 171
 172         with m.FSM(name='fetch_fsm'):
 173
 174             # waiting (zzz)
 175             with m.State("IDLE"):
 176                 comb += fetch_pc_ready_o.eq(1)
 177                 with m.If(fetch_pc_valid_i):
 178                     # instruction allowed to go: start by reading the PC
 179                     # capture the PC and also drop it into Insn Memory
 180                     # we have joined a pair of combinatorial memory
 181                     # lookups together.  this is Generally Bad.
 182                     comb += self.imem.a_pc_i.eq(pc)
 183                     comb += self.imem.a_valid_i.eq(1)
 184                     comb += self.imem.f_valid_i.eq(1)
 185                     sync += cur_state.pc.eq(pc)
 186                     sync += cur_state.svstate.eq(svstate) # and svstate
 187
 188                     # initiate read of MSR. arrives one clock later
 189                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 190                     sync += msr_read.eq(0)
 191
 192                     m.next = "INSN_READ"  # move to "wait for bus" phase
 193
 194             # dummy pause to find out why simulation is not keeping up
 195             with m.State("INSN_READ"):
 196                 # one cycle later, msr/sv read arrives.  valid only once.
 197                 with m.If(~msr_read):
 198                     sync += msr_read.eq(1) # yeah don't read it again
 199                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 200                 with m.If(self.imem.f_busy_o): # zzz...
 201                     # busy: stay in wait-read
 202                     comb += self.imem.a_valid_i.eq(1)
 203                     comb += self.imem.f_valid_i.eq(1)
 204                 with m.Else():
 205                     # not busy: instruction fetched
 206                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 207                     if self.svp64_en:
 208                         svp64 = self.svp64
 209                         # decode the SVP64 prefix, if any
 210                         comb += svp64.raw_opcode_in.eq(insn)
 211                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 212                         # pass the decoded prefix (if any) to PowerDecoder2
 213                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 214                         # calculate the address of the following instruction
 215                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 216                         sync += nia.eq(cur_state.pc + insn_size)
 217                         with m.If(~svp64.is_svp64_mode):
 218                             # with no prefix, store the instruction
 219                             # and hand it directly to the next FSM
 220                             sync += dec_opcode_i.eq(insn)
 221                             m.next = "INSN_READY"
 222                         with m.Else():
 223                             # fetch the rest of the instruction from memory
 224                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 225                             comb += self.imem.a_valid_i.eq(1)
 226                             comb += self.imem.f_valid_i.eq(1)
 227                             m.next = "INSN_READ2"
 228                     else:
 229                         # not SVP64 - 32-bit only
 230                         sync += nia.eq(cur_state.pc + 4)
 231                         sync += dec_opcode_i.eq(insn)
 232                         m.next = "INSN_READY"
 233
 234             with m.State("INSN_READ2"):
 235                 with m.If(self.imem.f_busy_o):  # zzz...
 236                     # busy: stay in wait-read
 237                     comb += self.imem.a_valid_i.eq(1)
 238                     comb += self.imem.f_valid_i.eq(1)
 239                 with m.Else():
 240                     # not busy: instruction fetched
 241                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 242                     sync += dec_opcode_i.eq(insn)
 243                     m.next = "INSN_READY"
 244
 245             with m.State("INSN_READY"):
 246                 # hand over the instruction, to be decoded
 247                 comb += fetch_insn_valid_o.eq(1)
 248                 with m.If(fetch_insn_ready_i):
 249                     m.next = "IDLE"
 250
 251     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 252                   dbg, core_rst,
 253                   fetch_pc_ready_o, fetch_pc_valid_i,
 254                   fetch_insn_valid_o, fetch_insn_ready_i,
 255                   exec_insn_valid_i, exec_insn_ready_o,
 256                   exec_pc_valid_o, exec_pc_ready_i):
 257         """issue FSM
 258
 259         decode / issue FSM.  this interacts with the "fetch" FSM
 260         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 261         (outgoing). also interacts with the "execute" FSM
 262         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 263         (incoming).
 264         SVP64 RM prefixes have already been set up by the
 265         "fetch" phase, so execute is fairly straightforward.
 266         """
 267
 268         comb = m.d.comb
 269         sync = m.d.sync
 270         pdecode2 = self.pdecode2
 271         cur_state = self.cur_state
 272
 273         # temporaries
 274         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 275
 276         # for updating svstate (things like srcstep etc.)
 277         update_svstate = Signal() # set this (below) if updating
 278         new_svstate = SVSTATERec("new_svstate")
 279         comb += new_svstate.eq(cur_state.svstate)
 280
 281         with m.FSM(name="issue_fsm"):
 282
 283             # go fetch the instruction at the current PC
 284             # at this point, there is no instruction running, that
 285             # could inadvertently update the PC.
 286             with m.State("INSN_FETCH"):
 287                 # wait on "core stop" release, before next fetch
 288                 # need to do this here, in case we are in a VL==0 loop
 289                 with m.If(~dbg.core_stop_o & ~core_rst):
 290                     comb += fetch_pc_valid_i.eq(1)
 291                     with m.If(fetch_pc_ready_o):
 292                         m.next = "INSN_WAIT"
 293                 with m.Else():
 294                     comb += core.core_stopped_i.eq(1)
 295                     comb += dbg.core_stopped_i.eq(1)
 296                     # while stopped, allow updating the PC and SVSTATE
 297                     with m.If(self.pc_i.ok):
 298                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 299                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 300                         sync += pc_changed.eq(1)
 301                     with m.If(self.svstate_i.ok):
 302                         comb += new_svstate.eq(self.svstate_i.data)
 303                         comb += update_svstate.eq(1)
 304                         sync += sv_changed.eq(1)
 305
 306             # decode the instruction when it arrives
 307             with m.State("INSN_WAIT"):
 308                 comb += fetch_insn_ready_i.eq(1)
 309                 with m.If(fetch_insn_valid_o):
 310                     # decode the instruction
 311                     sync += core.e.eq(pdecode2.e)
 312                     sync += core.state.eq(cur_state)
 313                     sync += core.raw_insn_i.eq(dec_opcode_i)
 314                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 315                     # loop into INSN_FETCH if it's a vector instruction
 316                     # and VL == 0.  this because VL==0 is a for-loop
 317                     # from 0 to 0 i.e. always, always a NOP.
 318                     cur_vl = cur_state.svstate.vl
 319                     with m.If(~pdecode2.no_out_vec & (cur_vl == 0)):
 320                         # update the PC before fetching the next instruction
 321                         # since we are in a VL==0 loop, no instruction was
 322                         # executed that we could be overwriting
 323                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 324                         comb += self.state_w_pc.data_i.eq(nia)
 325                         m.next = "INSN_FETCH"
 326                     with m.Else():
 327                         m.next = "INSN_EXECUTE"  # move to "execute"
 328
 329             with m.State("INSN_EXECUTE"):
 330                 comb += exec_insn_valid_i.eq(1)
 331                 with m.If(exec_insn_ready_o):
 332                     m.next = "EXECUTE_WAIT"
 333
 334             with m.State("EXECUTE_WAIT"):
 335                 # wait on "core stop" release, at instruction end
 336                 # need to do this here, in case we are in a VL>1 loop
 337                 with m.If(~dbg.core_stop_o & ~core_rst):
 338                     comb += exec_pc_ready_i.eq(1)
 339                     with m.If(exec_pc_valid_o):
 340                         # precalculate srcstep+1
 341                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 342                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 343                         # was this the last loop iteration?
 344                         is_last = Signal()
 345                         cur_vl = cur_state.svstate.vl
 346                         comb += is_last.eq(next_srcstep == cur_vl)
 347
 348                         # if either PC or SVSTATE were changed by the previous
 349                         # instruction, go directly back to Fetch, without
 350                         # updating either PC or SVSTATE
 351                         with m.If(pc_changed | sv_changed):
 352                             m.next = "INSN_FETCH"
 353
 354                         # also return to Fetch, when no output was a vector
 355                         # (regardless of SRCSTEP and VL), or when the last
 356                         # instruction was really the last one of the VL loop
 357                         with m.Elif(pdecode2.no_out_vec | is_last):
 358                             # before going back to fetch, update the PC state
 359                             # register with the NIA.
 360                             # ok here we are not reading the branch unit.
 361                             # TODO: this just blithely overwrites whatever
 362                             #       pipeline updated the PC
 363                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 364                             comb += self.state_w_pc.data_i.eq(nia)
 365                             # reset SRCSTEP before returning to Fetch
 366                             with m.If(~pdecode2.no_out_vec):
 367                                 comb += new_svstate.srcstep.eq(0)
 368                                 comb += update_svstate.eq(1)
 369                             m.next = "INSN_FETCH"
 370
 371                         # returning to Execute? then, first update SRCSTEP
 372                         with m.Else():
 373                             comb += new_svstate.srcstep.eq(next_srcstep)
 374                             comb += update_svstate.eq(1)
 375                             m.next = "DECODE_SV"
 376
 377                 with m.Else():
 378                     comb += core.core_stopped_i.eq(1)
 379                     comb += dbg.core_stopped_i.eq(1)
 380                     # while stopped, allow updating the PC and SVSTATE
 381                     with m.If(self.pc_i.ok):
 382                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 383                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 384                         sync += pc_changed.eq(1)
 385                     with m.If(self.svstate_i.ok):
 386                         comb += new_svstate.eq(self.svstate_i.data)
 387                         comb += update_svstate.eq(1)
 388                         sync += sv_changed.eq(1)
 389
 390             # need to decode the instruction again, after updating SRCSTEP
 391             # in the previous state.
 392             # mostly a copy of INSN_WAIT, but without the actual wait
 393             with m.State("DECODE_SV"):
 394                 # decode the instruction
 395                 sync += core.e.eq(pdecode2.e)
 396                 sync += core.state.eq(cur_state)
 397                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 398                 m.next = "INSN_EXECUTE"  # move to "execute"
 399
 400         # check if svstate needs updating: if so, write it to State Regfile
 401         with m.If(update_svstate):
 402             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 403             comb += self.state_w_sv.data_i.eq(new_svstate)
 404             sync += cur_state.svstate.eq(new_svstate) # for next clock
 405
 406     def execute_fsm(self, m, core, pc_changed, sv_changed,
 407                     exec_insn_valid_i, exec_insn_ready_o,
 408                     exec_pc_valid_o, exec_pc_ready_i):
 409         """execute FSM
 410
 411         execute FSM. this interacts with the "issue" FSM
 412         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 413         (outgoing). SVP64 RM prefixes have already been set up by the
 414         "issue" phase, so execute is fairly straightforward.
 415         """
 416
 417         comb = m.d.comb
 418         sync = m.d.sync
 419         pdecode2 = self.pdecode2
 420
 421         # temporaries
 422         core_busy_o = core.busy_o                 # core is busy
 423         core_ivalid_i = core.ivalid_i             # instruction is valid
 424         core_issue_i = core.issue_i               # instruction is issued
 425         insn_type = core.e.do.insn_type           # instruction MicroOp type
 426
 427         with m.FSM(name="exec_fsm"):
 428
 429             # waiting for instruction bus (stays there until not busy)
 430             with m.State("INSN_START"):
 431                 comb += exec_insn_ready_o.eq(1)
 432                 with m.If(exec_insn_valid_i):
 433                     comb += core_ivalid_i.eq(1)  # instruction is valid
 434                     comb += core_issue_i.eq(1)  # and issued
 435                     sync += sv_changed.eq(0)
 436                     sync += pc_changed.eq(0)
 437                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 438
 439             # instruction started: must wait till it finishes
 440             with m.State("INSN_ACTIVE"):
 441                 with m.If(insn_type != MicrOp.OP_NOP):
 442                     comb += core_ivalid_i.eq(1) # instruction is valid
 443                 # note changes to PC and SVSTATE
 444                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 445                     sync += sv_changed.eq(1)
 446                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 447                     sync += pc_changed.eq(1)
 448                 with m.If(~core_busy_o): # instruction done!
 449                     comb += exec_pc_valid_o.eq(1)
 450                     with m.If(exec_pc_ready_i):
 451                         m.next = "INSN_START"  # back to fetch
 452
 453     def elaborate(self, platform):
 454         m = Module()
 455         comb, sync = m.d.comb, m.d.sync
 456
 457         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 458         m.submodules.imem = imem = self.imem
 459         m.submodules.dbg = dbg = self.dbg
 460         if self.jtag_en:
 461             m.submodules.jtag = jtag = self.jtag
 462             # TODO: UART2GDB mux, here, from external pin
 463             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 464             sync += dbg.dmi.connect_to(jtag.dmi)
 465
 466         cur_state = self.cur_state
 467
 468         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 469         if self.sram4x4k:
 470             for i, sram in enumerate(self.sram4k):
 471                 m.submodules["sram4k_%d" % i] = sram
 472                 comb += sram.enable.eq(self.wb_sram_en)
 473
 474         # XICS interrupt handler
 475         if self.xics:
 476             m.submodules.xics_icp = icp = self.xics_icp
 477             m.submodules.xics_ics = ics = self.xics_ics
 478             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 479             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 480
 481         # GPIO test peripheral
 482         if self.gpio:
 483             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 484
 485         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 486         # XXX causes litex ECP5 test to get wrong idea about input and output
 487         # (but works with verilator sim *sigh*)
 488         #if self.gpio and self.xics:
 489         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 490
 491         # instruction decoder
 492         pdecode = create_pdecode()
 493         m.submodules.dec2 = pdecode2 = self.pdecode2
 494         if self.svp64_en:
 495             m.submodules.svp64 = svp64 = self.svp64
 496
 497         # convenience
 498         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 499         intrf = self.core.regs.rf['int']
 500
 501         # clock delay power-on reset
 502         cd_por  = ClockDomain(reset_less=True)
 503         cd_sync = ClockDomain()
 504         core_sync = ClockDomain("coresync")
 505         m.domains += cd_por, cd_sync, core_sync
 506
 507         ti_rst = Signal(reset_less=True)
 508         delay = Signal(range(4), reset=3)
 509         with m.If(delay != 0):
 510             m.d.por += delay.eq(delay - 1)
 511         comb += cd_por.clk.eq(ClockSignal())
 512
 513         # power-on reset delay
 514         core_rst = ResetSignal("coresync")
 515         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 516         comb += core_rst.eq(ti_rst)
 517
 518         # busy/halted signals from core
 519         comb += self.busy_o.eq(core.busy_o)
 520         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 521
 522         # temporary hack: says "go" immediately for both address gen and ST
 523         l0 = core.l0
 524         ldst = core.fus.fus['ldst0']
 525         st_go_edge = rising_edge(m, ldst.st.rel_o)
 526         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 527         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 528
 529         # PC and instruction from I-Memory
 530         comb += self.pc_o.eq(cur_state.pc)
 531         pc_changed = Signal() # note write to PC
 532         sv_changed = Signal() # note write to SVSTATE
 533
 534         # read the PC
 535         pc = Signal(64, reset_less=True)
 536         pc_ok_delay = Signal()
 537         sync += pc_ok_delay.eq(~self.pc_i.ok)
 538         with m.If(self.pc_i.ok):
 539             # incoming override (start from pc_i)
 540             comb += pc.eq(self.pc_i.data)
 541         with m.Else():
 542             # otherwise read StateRegs regfile for PC...
 543             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 544         # ... but on a 1-clock delay
 545         with m.If(pc_ok_delay):
 546             comb += pc.eq(self.state_r_pc.data_o)
 547
 548         # read svstate
 549         svstate = Signal(64, reset_less=True)
 550         svstate_ok_delay = Signal()
 551         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 552         with m.If(self.svstate_i.ok):
 553             # incoming override (start from svstate__i)
 554             comb += svstate.eq(self.svstate_i.data)
 555         with m.Else():
 556             # otherwise read StateRegs regfile for SVSTATE...
 557             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 558         # ... but on a 1-clock delay
 559         with m.If(svstate_ok_delay):
 560             comb += svstate.eq(self.state_r_sv.data_o)
 561
 562         # don't write pc every cycle
 563         comb += self.state_w_pc.wen.eq(0)
 564         comb += self.state_w_pc.data_i.eq(0)
 565
 566         # don't read msr every cycle
 567         comb += self.state_r_msr.ren.eq(0)
 568
 569         # address of the next instruction, in the absence of a branch
 570         # depends on the instruction size
 571         nia = Signal(64, reset_less=True)
 572
 573         # connect up debug signals
 574         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 575         comb += dbg.terminate_i.eq(core.core_terminate_o)
 576         comb += dbg.state.pc.eq(pc)
 577         comb += dbg.state.svstate.eq(svstate)
 578         comb += dbg.state.msr.eq(cur_state.msr)
 579
 580         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 581         # these are the handshake signals between fetch and decode/execute
 582
 583         # fetch FSM can run as soon as the PC is valid
 584         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 585         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 586
 587         # fetch FSM hands over the instruction to be decoded / issued
 588         fetch_insn_valid_o = Signal()
 589         fetch_insn_ready_i = Signal()
 590
 591         # issue FSM delivers the instruction to the be executed
 592         exec_insn_valid_i = Signal()
 593         exec_insn_ready_o = Signal()
 594
 595         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 596         exec_pc_valid_o = Signal()
 597         exec_pc_ready_i = Signal()
 598
 599         # the FSMs here are perhaps unusual in that they detect conditions
 600         # then "hold" information, combinatorially, for the core
 601         # (as opposed to using sync - which would be on a clock's delay)
 602         # this includes the actual opcode, valid flags and so on.
 603
 604         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 605         # lives.  the ready/valid signalling is used to communicate between
 606         # the three.
 607
 608         self.fetch_fsm(m, core, pc, svstate, nia,
 609                        fetch_pc_ready_o, fetch_pc_valid_i,
 610                        fetch_insn_valid_o, fetch_insn_ready_i)
 611
 612         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 613                        dbg, core_rst,
 614                        fetch_pc_ready_o, fetch_pc_valid_i,
 615                        fetch_insn_valid_o, fetch_insn_ready_i,
 616                        exec_insn_valid_i, exec_insn_ready_o,
 617                        exec_pc_valid_o, exec_pc_ready_i)
 618
 619         self.execute_fsm(m, core, pc_changed, sv_changed,
 620                          exec_insn_valid_i, exec_insn_ready_o,
 621                          exec_pc_valid_o, exec_pc_ready_i)
 622
 623         # this bit doesn't have to be in the FSM: connect up to read
 624         # regfiles on demand from DMI
 625         self.do_dmi(m, dbg)
 626
 627         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 628         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 629         self.tb_dec_fsm(m, cur_state.dec)
 630
 631         return m
 632
 633     def do_dmi(self, m, dbg):
 634         comb = m.d.comb
 635         sync = m.d.sync
 636         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 637         intrf = self.core.regs.rf['int']
 638
 639         with m.If(d_reg.req): # request for regfile access being made
 640             # TODO: error-check this
 641             # XXX should this be combinatorial?  sync better?
 642             if intrf.unary:
 643                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 644             else:
 645                 comb += self.int_r.addr.eq(d_reg.addr)
 646                 comb += self.int_r.ren.eq(1)
 647         d_reg_delay  = Signal()
 648         sync += d_reg_delay.eq(d_reg.req)
 649         with m.If(d_reg_delay):
 650             # data arrives one clock later
 651             comb += d_reg.data.eq(self.int_r.data_o)
 652             comb += d_reg.ack.eq(1)
 653
 654         # sigh same thing for CR debug
 655         with m.If(d_cr.req): # request for regfile access being made
 656             comb += self.cr_r.ren.eq(0b11111111) # enable all
 657         d_cr_delay  = Signal()
 658         sync += d_cr_delay.eq(d_cr.req)
 659         with m.If(d_cr_delay):
 660             # data arrives one clock later
 661             comb += d_cr.data.eq(self.cr_r.data_o)
 662             comb += d_cr.ack.eq(1)
 663
 664         # aaand XER...
 665         with m.If(d_xer.req): # request for regfile access being made
 666             comb += self.xer_r.ren.eq(0b111111) # enable all
 667         d_xer_delay  = Signal()
 668         sync += d_xer_delay.eq(d_xer.req)
 669         with m.If(d_xer_delay):
 670             # data arrives one clock later
 671             comb += d_xer.data.eq(self.xer_r.data_o)
 672             comb += d_xer.ack.eq(1)
 673
 674     def tb_dec_fsm(self, m, spr_dec):
 675         """tb_dec_fsm
 676
 677         this is a FSM for updating either dec or tb.  it runs alternately
 678         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 679         value to DEC, however the regfile has "passthrough" on it so this
 680         *should* be ok.
 681
 682         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 683         """
 684
 685         comb, sync = m.d.comb, m.d.sync
 686         fast_rf = self.core.regs.rf['fast']
 687         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 688         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 689
 690         with m.FSM() as fsm:
 691
 692             # initiates read of current DEC
 693             with m.State("DEC_READ"):
 694                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 695                 comb += fast_r_dectb.ren.eq(1)
 696                 m.next = "DEC_WRITE"
 697
 698             # waits for DEC read to arrive (1 cycle), updates with new value
 699             with m.State("DEC_WRITE"):
 700                 new_dec = Signal(64)
 701                 # TODO: MSR.LPCR 32-bit decrement mode
 702                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 703                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 704                 comb += fast_w_dectb.wen.eq(1)
 705                 comb += fast_w_dectb.data_i.eq(new_dec)
 706                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 707                 m.next = "TB_READ"
 708
 709             # initiates read of current TB
 710             with m.State("TB_READ"):
 711                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 712                 comb += fast_r_dectb.ren.eq(1)
 713                 m.next = "TB_WRITE"
 714
 715             # waits for read TB to arrive, initiates write of current TB
 716             with m.State("TB_WRITE"):
 717                 new_tb = Signal(64)
 718                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 719                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 720                 comb += fast_w_dectb.wen.eq(1)
 721                 comb += fast_w_dectb.data_i.eq(new_tb)
 722                 m.next = "DEC_READ"
 723
 724         return m
 725
 726     def __iter__(self):
 727         yield from self.pc_i.ports()
 728         yield self.pc_o
 729         yield self.memerr_o
 730         yield from self.core.ports()
 731         yield from self.imem.ports()
 732         yield self.core_bigendian_i
 733         yield self.busy_o
 734
 735     def ports(self):
 736         return list(self)
 737
 738     def external_ports(self):
 739         ports = self.pc_i.ports()
 740         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 741                 ]
 742
 743         if self.jtag_en:
 744             ports += list(self.jtag.external_ports())
 745         else:
 746             # don't add DMI if JTAG is enabled
 747             ports += list(self.dbg.dmi.ports())
 748
 749         ports += list(self.imem.ibus.fields.values())
 750         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 751
 752         if self.sram4x4k:
 753             for sram in self.sram4k:
 754                 ports += list(sram.bus.fields.values())
 755
 756         if self.xics:
 757             ports += list(self.xics_icp.bus.fields.values())
 758             ports += list(self.xics_ics.bus.fields.values())
 759             ports.append(self.int_level_i)
 760
 761         if self.gpio:
 762             ports += list(self.simple_gpio.bus.fields.values())
 763             ports.append(self.gpio_o)
 764
 765         return ports
 766
 767     def ports(self):
 768         return list(self)
 769
 770
 771 class TestIssuer(Elaboratable):
 772     def __init__(self, pspec):
 773         self.ti = TestIssuerInternal(pspec)
 774
 775         self.pll = DummyPLL()
 776
 777         # PLL direct clock or not
 778         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 779         if self.pll_en:
 780             self.pll_18_o = Signal(reset_less=True)
 781
 782     def elaborate(self, platform):
 783         m = Module()
 784         comb = m.d.comb
 785
 786         # TestIssuer runs at direct clock
 787         m.submodules.ti = ti = self.ti
 788         cd_int = ClockDomain("coresync")
 789
 790         if self.pll_en:
 791             # ClockSelect runs at PLL output internal clock rate
 792             m.submodules.pll = pll = self.pll
 793
 794             # add clock domains from PLL
 795             cd_pll = ClockDomain("pllclk")
 796             m.domains += cd_pll
 797
 798             # PLL clock established.  has the side-effect of running clklsel
 799             # at the PLL's speed (see DomainRenamer("pllclk") above)
 800             pllclk = ClockSignal("pllclk")
 801             comb += pllclk.eq(pll.clk_pll_o)
 802
 803             # wire up external 24mhz to PLL
 804             comb += pll.clk_24_i.eq(ClockSignal())
 805
 806             # output 18 mhz PLL test signal
 807             comb += self.pll_18_o.eq(pll.pll_18_o)
 808
 809             # now wire up ResetSignals.  don't mind them being in this domain
 810             pll_rst = ResetSignal("pllclk")
 811             comb += pll_rst.eq(ResetSignal())
 812
 813         # internal clock is set to selector clock-out.  has the side-effect of
 814         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 815         intclk = ClockSignal("coresync")
 816         if self.pll_en:
 817             comb += intclk.eq(pll.clk_pll_o)
 818         else:
 819             comb += intclk.eq(ClockSignal())
 820
 821         return m
 822
 823     def ports(self):
 824         return list(self.ti.ports()) + list(self.pll.ports()) + \
 825                [ClockSignal(), ResetSignal()]
 826
 827     def external_ports(self):
 828         ports = self.ti.external_ports()
 829         ports.append(ClockSignal())
 830         ports.append(ResetSignal())
 831         if self.pll_en:
 832             ports.append(self.pll.clk_sel_i)
 833             ports.append(self.pll_18_o)
 834             ports.append(self.pll.pll_lck_o)
 835         return ports
 836
 837
 838 if __name__ == '__main__':
 839     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 840              'spr': 1,
 841              'div': 1,
 842              'mul': 1,
 843              'shiftrot': 1
 844             }
 845     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 846                          imem_ifacetype='bare_wb',
 847                          addr_wid=48,
 848                          mask_wid=8,
 849                          reg_wid=64,
 850                          units=units)
 851     dut = TestIssuer(pspec)
 852     vl = main(dut, ports=dut.ports(), name="test_issuer")
 853
 854     if len(sys.argv) == 1:
 855         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 856         with open("test_issuer.il", "w") as f:
 857             f.write(vl)