src/soc/simple/issuer.py

   1 """simple core issuer
   2
   3 not in any way intended for production use.  this runs a FSM that:
   4
   5 * reads the Program Counter from StateRegs
   6 * reads an instruction from a fixed-size Test Memory
   7 * issues it to the Simple Core
   8 * waits for it to complete
   9 * increments the PC
  10 * does it all over again
  11
  12 the purpose of this module is to verify the functional correctness
  13 of the Function Units in the absolute simplest and clearest possible
  14 way, and to at provide something that can be further incrementally
  15 improved.
  16 """
  17
  18 from nmigen import (Elaboratable, Module, Signal, ClockSignal, ResetSignal,
  19                     ClockDomain, DomainRenamer, Mux, Const)
  20 from nmigen.cli import rtlil
  21 from nmigen.cli import main
  22 import sys
  23
  24 from soc.decoder.power_decoder import create_pdecode
  25 from soc.decoder.power_decoder2 import PowerDecode2, SVP64PrefixDecoder
  26 from soc.decoder.decode2execute1 import IssuerDecode2ToOperand
  27 from soc.decoder.decode2execute1 import Data
  28 from soc.experiment.testmem import TestMemory # test only for instructions
  29 from soc.regfile.regfiles import StateRegs, FastRegs
  30 from soc.simple.core import NonProductionCore
  31 from soc.config.test.test_loadstore import TestMemPspec
  32 from soc.config.ifetch import ConfigFetchUnit
  33 from soc.decoder.power_enums import MicrOp
  34 from soc.debug.dmi import CoreDebug, DMIInterface
  35 from soc.debug.jtag import JTAG
  36 from soc.config.pinouts import get_pinspecs
  37 from soc.config.state import CoreState
  38 from soc.interrupts.xics import XICS_ICP, XICS_ICS
  39 from soc.bus.simple_gpio import SimpleGPIO
  40 from soc.bus.SPBlock512W64B8W import SPBlock512W64B8W
  41 from soc.clock.select import ClockSelect
  42 from soc.clock.dummypll import DummyPLL
  43 from soc.sv.svstate import SVSTATERec
  44
  45
  46 from nmutil.util import rising_edge
  47
  48 def get_insn(f_instr_o, pc):
  49     if f_instr_o.width == 32:
  50         return f_instr_o
  51     else:
  52         # 64-bit: bit 2 of pc decides which word to select
  53         return f_instr_o.word_select(pc[2], 32)
  54
  55
  56 class TestIssuerInternal(Elaboratable):
  57     """TestIssuer - reads instructions from TestMemory and issues them
  58
  59     efficiency and speed is not the main goal here: functional correctness is.
  60     """
  61     def __init__(self, pspec):
  62
  63         # test is SVP64 is to be enabled
  64         self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
  65
  66         # JTAG interface.  add this right at the start because if it's
  67         # added it *modifies* the pspec, by adding enable/disable signals
  68         # for parts of the rest of the core
  69         self.jtag_en = hasattr(pspec, "debug") and pspec.debug == 'jtag'
  70         if self.jtag_en:
  71             subset = {'uart', 'mtwi', 'eint', 'gpio', 'mspi0', 'mspi1',
  72                       'pwm', 'sd0', 'sdr'}
  73             self.jtag = JTAG(get_pinspecs(subset=subset))
  74             # add signals to pspec to enable/disable icache and dcache
  75             # (or data and intstruction wishbone if icache/dcache not included)
  76             # https://bugs.libre-soc.org/show_bug.cgi?id=520
  77             # TODO: do we actually care if these are not domain-synchronised?
  78             # honestly probably not.
  79             pspec.wb_icache_en = self.jtag.wb_icache_en
  80             pspec.wb_dcache_en = self.jtag.wb_dcache_en
  81             self.wb_sram_en = self.jtag.wb_sram_en
  82         else:
  83             self.wb_sram_en = Const(1)
  84
  85         # add 4k sram blocks?
  86         self.sram4x4k = (hasattr(pspec, "sram4x4kblock") and
  87                          pspec.sram4x4kblock == True)
  88         if self.sram4x4k:
  89             self.sram4k = []
  90             for i in range(4):
  91                 self.sram4k.append(SPBlock512W64B8W(name="sram4k_%d" % i,
  92                                                     features={'err'}))
  93
  94         # add interrupt controller?
  95         self.xics = hasattr(pspec, "xics") and pspec.xics == True
  96         if self.xics:
  97             self.xics_icp = XICS_ICP()
  98             self.xics_ics = XICS_ICS()
  99             self.int_level_i = self.xics_ics.int_level_i
 100
 101         # add GPIO peripheral?
 102         self.gpio = hasattr(pspec, "gpio") and pspec.gpio == True
 103         if self.gpio:
 104             self.simple_gpio = SimpleGPIO()
 105             self.gpio_o = self.simple_gpio.gpio_o
 106
 107         # main instruction core25
 108         self.core = core = NonProductionCore(pspec)
 109
 110         # instruction decoder.  goes into Trap Record
 111         pdecode = create_pdecode()
 112         self.cur_state = CoreState("cur") # current state (MSR/PC/EINT/SVSTATE)
 113         self.pdecode2 = PowerDecode2(pdecode, state=self.cur_state,
 114                                      opkls=IssuerDecode2ToOperand,
 115                                      svp64_en=self.svp64_en)
 116         if self.svp64_en:
 117             self.svp64 = SVP64PrefixDecoder() # for decoding SVP64 prefix
 118
 119         # Test Instruction memory
 120         self.imem = ConfigFetchUnit(pspec).fu
 121         # one-row cache of instruction read
 122         self.iline = Signal(64) # one instruction line
 123         self.iprev_adr = Signal(64) # previous address: if different, do read
 124
 125         # DMI interface
 126         self.dbg = CoreDebug()
 127
 128         # instruction go/monitor
 129         self.pc_o = Signal(64, reset_less=True)
 130         self.pc_i = Data(64, "pc_i") # set "ok" to indicate "please change me"
 131         self.svstate_i = Data(32, "svstate_i") # ditto
 132         self.core_bigendian_i = Signal()
 133         self.busy_o = Signal(reset_less=True)
 134         self.memerr_o = Signal(reset_less=True)
 135
 136         # STATE regfile read /write ports for PC, MSR, SVSTATE
 137         staterf = self.core.regs.rf['state']
 138         self.state_r_pc = staterf.r_ports['cia'] # PC rd
 139         self.state_w_pc = staterf.w_ports['d_wr1'] # PC wr
 140         self.state_r_msr = staterf.r_ports['msr'] # MSR rd
 141         self.state_r_sv = staterf.r_ports['sv'] # SVSTATE rd
 142         self.state_w_sv = staterf.w_ports['sv'] # SVSTATE wr
 143
 144         # DMI interface access
 145         intrf = self.core.regs.rf['int']
 146         crrf = self.core.regs.rf['cr']
 147         xerrf = self.core.regs.rf['xer']
 148         self.int_r = intrf.r_ports['dmi'] # INT read
 149         self.cr_r = crrf.r_ports['full_cr_dbg'] # CR read
 150         self.xer_r = xerrf.r_ports['full_xer'] # XER read
 151
 152         # hack method of keeping an eye on whether branch/trap set the PC
 153         self.state_nia = self.core.regs.rf['state'].w_ports['nia']
 154         self.state_nia.wen.name = 'state_nia_wen'
 155
 156         # pulse to synchronize the simulator at instruction end
 157         self.insn_done = Signal()
 158
 159     def fetch_fsm(self, m, core, pc, svstate, nia, is_svp64_mode,
 160                         fetch_pc_ready_o, fetch_pc_valid_i,
 161                         fetch_insn_valid_o, fetch_insn_ready_i):
 162         """fetch FSM
 163         this FSM performs fetch of raw instruction data, partial-decodes
 164         it 32-bit at a time to detect SVP64 prefixes, and will optionally
 165         read a 2nd 32-bit quantity if that occurs.
 166         """
 167         comb = m.d.comb
 168         sync = m.d.sync
 169         pdecode2 = self.pdecode2
 170         cur_state = self.cur_state
 171         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 172
 173         msr_read = Signal(reset=1)
 174
 175         with m.FSM(name='fetch_fsm'):
 176
 177             # waiting (zzz)
 178             with m.State("IDLE"):
 179                 comb += fetch_pc_ready_o.eq(1)
 180                 with m.If(fetch_pc_valid_i):
 181                     # instruction allowed to go: start by reading the PC
 182                     # capture the PC and also drop it into Insn Memory
 183                     # we have joined a pair of combinatorial memory
 184                     # lookups together.  this is Generally Bad.
 185                     comb += self.imem.a_pc_i.eq(pc)
 186                     comb += self.imem.a_valid_i.eq(1)
 187                     comb += self.imem.f_valid_i.eq(1)
 188                     sync += cur_state.pc.eq(pc)
 189                     sync += cur_state.svstate.eq(svstate) # and svstate
 190
 191                     # initiate read of MSR. arrives one clock later
 192                     comb += self.state_r_msr.ren.eq(1 << StateRegs.MSR)
 193                     sync += msr_read.eq(0)
 194
 195                     m.next = "INSN_READ"  # move to "wait for bus" phase
 196
 197             # dummy pause to find out why simulation is not keeping up
 198             with m.State("INSN_READ"):
 199                 # one cycle later, msr/sv read arrives.  valid only once.
 200                 with m.If(~msr_read):
 201                     sync += msr_read.eq(1) # yeah don't read it again
 202                     sync += cur_state.msr.eq(self.state_r_msr.data_o)
 203                 with m.If(self.imem.f_busy_o): # zzz...
 204                     # busy: stay in wait-read
 205                     comb += self.imem.a_valid_i.eq(1)
 206                     comb += self.imem.f_valid_i.eq(1)
 207                 with m.Else():
 208                     # not busy: instruction fetched
 209                     insn = get_insn(self.imem.f_instr_o, cur_state.pc)
 210                     if self.svp64_en:
 211                         svp64 = self.svp64
 212                         # decode the SVP64 prefix, if any
 213                         comb += svp64.raw_opcode_in.eq(insn)
 214                         comb += svp64.bigendian.eq(self.core_bigendian_i)
 215                         # pass the decoded prefix (if any) to PowerDecoder2
 216                         sync += pdecode2.sv_rm.eq(svp64.svp64_rm)
 217                         # remember whether this is a prefixed instruction, so
 218                         # the FSM can readily loop when VL==0
 219                         sync += is_svp64_mode.eq(svp64.is_svp64_mode)
 220                         # calculate the address of the following instruction
 221                         insn_size = Mux(svp64.is_svp64_mode, 8, 4)
 222                         sync += nia.eq(cur_state.pc + insn_size)
 223                         with m.If(~svp64.is_svp64_mode):
 224                             # with no prefix, store the instruction
 225                             # and hand it directly to the next FSM
 226                             sync += dec_opcode_i.eq(insn)
 227                             m.next = "INSN_READY"
 228                         with m.Else():
 229                             # fetch the rest of the instruction from memory
 230                             comb += self.imem.a_pc_i.eq(cur_state.pc + 4)
 231                             comb += self.imem.a_valid_i.eq(1)
 232                             comb += self.imem.f_valid_i.eq(1)
 233                             m.next = "INSN_READ2"
 234                     else:
 235                         # not SVP64 - 32-bit only
 236                         sync += nia.eq(cur_state.pc + 4)
 237                         sync += dec_opcode_i.eq(insn)
 238                         m.next = "INSN_READY"
 239
 240             with m.State("INSN_READ2"):
 241                 with m.If(self.imem.f_busy_o):  # zzz...
 242                     # busy: stay in wait-read
 243                     comb += self.imem.a_valid_i.eq(1)
 244                     comb += self.imem.f_valid_i.eq(1)
 245                 with m.Else():
 246                     # not busy: instruction fetched
 247                     insn = get_insn(self.imem.f_instr_o, cur_state.pc+4)
 248                     sync += dec_opcode_i.eq(insn)
 249                     m.next = "INSN_READY"
 250
 251             with m.State("INSN_READY"):
 252                 # hand over the instruction, to be decoded
 253                 comb += fetch_insn_valid_o.eq(1)
 254                 with m.If(fetch_insn_ready_i):
 255                     m.next = "IDLE"
 256
 257     def issue_fsm(self, m, core, pc_changed, sv_changed, nia,
 258                   dbg, core_rst, is_svp64_mode,
 259                   fetch_pc_ready_o, fetch_pc_valid_i,
 260                   fetch_insn_valid_o, fetch_insn_ready_i,
 261                   exec_insn_valid_i, exec_insn_ready_o,
 262                   exec_pc_valid_o, exec_pc_ready_i):
 263         """issue FSM
 264
 265         decode / issue FSM.  this interacts with the "fetch" FSM
 266         through fetch_insn_ready/valid (incoming) and fetch_pc_ready/valid
 267         (outgoing). also interacts with the "execute" FSM
 268         through exec_insn_ready/valid (outgoing) and exec_pc_ready/valid
 269         (incoming).
 270         SVP64 RM prefixes have already been set up by the
 271         "fetch" phase, so execute is fairly straightforward.
 272         """
 273
 274         comb = m.d.comb
 275         sync = m.d.sync
 276         pdecode2 = self.pdecode2
 277         cur_state = self.cur_state
 278
 279         # temporaries
 280         dec_opcode_i = pdecode2.dec.raw_opcode_in # raw opcode
 281
 282         # for updating svstate (things like srcstep etc.)
 283         update_svstate = Signal() # set this (below) if updating
 284         new_svstate = SVSTATERec("new_svstate")
 285         comb += new_svstate.eq(cur_state.svstate)
 286
 287         with m.FSM(name="issue_fsm"):
 288
 289             # go fetch the instruction at the current PC
 290             # at this point, there is no instruction running, that
 291             # could inadvertently update the PC.
 292             with m.State("INSN_FETCH"):
 293                 # wait on "core stop" release, before next fetch
 294                 # need to do this here, in case we are in a VL==0 loop
 295                 with m.If(~dbg.core_stop_o & ~core_rst):
 296                     comb += fetch_pc_valid_i.eq(1)
 297                     with m.If(fetch_pc_ready_o):
 298                         m.next = "INSN_WAIT"
 299                 with m.Else():
 300                     comb += core.core_stopped_i.eq(1)
 301                     comb += dbg.core_stopped_i.eq(1)
 302                     # while stopped, allow updating the PC and SVSTATE
 303                     with m.If(self.pc_i.ok):
 304                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 305                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 306                         sync += pc_changed.eq(1)
 307                     with m.If(self.svstate_i.ok):
 308                         comb += new_svstate.eq(self.svstate_i.data)
 309                         comb += update_svstate.eq(1)
 310                         sync += sv_changed.eq(1)
 311
 312             # decode the instruction when it arrives
 313             with m.State("INSN_WAIT"):
 314                 comb += fetch_insn_ready_i.eq(1)
 315                 with m.If(fetch_insn_valid_o):
 316                     # decode the instruction
 317                     sync += core.e.eq(pdecode2.e)
 318                     sync += core.state.eq(cur_state)
 319                     sync += core.raw_insn_i.eq(dec_opcode_i)
 320                     sync += core.bigendian_i.eq(self.core_bigendian_i)
 321                     # set RA_OR_ZERO detection in satellite decoders
 322                     sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 323                     # loop into INSN_FETCH if it's a SVP64 instruction
 324                     # and VL == 0.  this because VL==0 is a for-loop
 325                     # from 0 to 0 i.e. always, always a NOP.
 326                     cur_vl = cur_state.svstate.vl
 327                     with m.If(is_svp64_mode & (cur_vl == 0)):
 328                         # update the PC before fetching the next instruction
 329                         # since we are in a VL==0 loop, no instruction was
 330                         # executed that we could be overwriting
 331                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 332                         comb += self.state_w_pc.data_i.eq(nia)
 333                         comb += self.insn_done.eq(1)
 334                         m.next = "INSN_FETCH"
 335                     with m.Else():
 336                         m.next = "INSN_EXECUTE"  # move to "execute"
 337
 338             with m.State("INSN_EXECUTE"):
 339                 comb += exec_insn_valid_i.eq(1)
 340                 with m.If(exec_insn_ready_o):
 341                     m.next = "EXECUTE_WAIT"
 342
 343             with m.State("EXECUTE_WAIT"):
 344                 # wait on "core stop" release, at instruction end
 345                 # need to do this here, in case we are in a VL>1 loop
 346                 with m.If(~dbg.core_stop_o & ~core_rst):
 347                     comb += exec_pc_ready_i.eq(1)
 348                     with m.If(exec_pc_valid_o):
 349                         # precalculate srcstep+1
 350                         next_srcstep = Signal.like(cur_state.svstate.srcstep)
 351                         comb += next_srcstep.eq(cur_state.svstate.srcstep+1)
 352                         # was this the last loop iteration?
 353                         is_last = Signal()
 354                         cur_vl = cur_state.svstate.vl
 355                         comb += is_last.eq(next_srcstep == cur_vl)
 356
 357                         # if either PC or SVSTATE were changed by the previous
 358                         # instruction, go directly back to Fetch, without
 359                         # updating either PC or SVSTATE
 360                         with m.If(pc_changed | sv_changed):
 361                             m.next = "INSN_FETCH"
 362
 363                         # also return to Fetch, when no output was a vector
 364                         # (regardless of SRCSTEP and VL), or when the last
 365                         # instruction was really the last one of the VL loop
 366                         with m.Elif((~pdecode2.loop_continue) | is_last):
 367                             # before going back to fetch, update the PC state
 368                             # register with the NIA.
 369                             # ok here we are not reading the branch unit.
 370                             # TODO: this just blithely overwrites whatever
 371                             #       pipeline updated the PC
 372                             comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 373                             comb += self.state_w_pc.data_i.eq(nia)
 374                             # reset SRCSTEP before returning to Fetch
 375                             with m.If(pdecode2.loop_continue):
 376                                 comb += new_svstate.srcstep.eq(0)
 377                                 comb += update_svstate.eq(1)
 378                             m.next = "INSN_FETCH"
 379
 380                         # returning to Execute? then, first update SRCSTEP
 381                         with m.Else():
 382                             comb += new_svstate.srcstep.eq(next_srcstep)
 383                             comb += update_svstate.eq(1)
 384                             m.next = "DECODE_SV"
 385
 386                 with m.Else():
 387                     comb += core.core_stopped_i.eq(1)
 388                     comb += dbg.core_stopped_i.eq(1)
 389                     # while stopped, allow updating the PC and SVSTATE
 390                     with m.If(self.pc_i.ok):
 391                         comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
 392                         comb += self.state_w_pc.data_i.eq(self.pc_i.data)
 393                         sync += pc_changed.eq(1)
 394                     with m.If(self.svstate_i.ok):
 395                         comb += new_svstate.eq(self.svstate_i.data)
 396                         comb += update_svstate.eq(1)
 397                         sync += sv_changed.eq(1)
 398
 399             # need to decode the instruction again, after updating SRCSTEP
 400             # in the previous state.
 401             # mostly a copy of INSN_WAIT, but without the actual wait
 402             with m.State("DECODE_SV"):
 403                 # decode the instruction
 404                 sync += core.e.eq(pdecode2.e)
 405                 sync += core.state.eq(cur_state)
 406                 sync += core.bigendian_i.eq(self.core_bigendian_i)
 407                 sync += core.sv_a_nz.eq(pdecode2.sv_a_nz)
 408                 m.next = "INSN_EXECUTE"  # move to "execute"
 409
 410         # check if svstate needs updating: if so, write it to State Regfile
 411         with m.If(update_svstate):
 412             comb += self.state_w_sv.wen.eq(1<<StateRegs.SVSTATE)
 413             comb += self.state_w_sv.data_i.eq(new_svstate)
 414             sync += cur_state.svstate.eq(new_svstate) # for next clock
 415
 416     def execute_fsm(self, m, core, pc_changed, sv_changed,
 417                     exec_insn_valid_i, exec_insn_ready_o,
 418                     exec_pc_valid_o, exec_pc_ready_i):
 419         """execute FSM
 420
 421         execute FSM. this interacts with the "issue" FSM
 422         through exec_insn_ready/valid (incoming) and exec_pc_ready/valid
 423         (outgoing). SVP64 RM prefixes have already been set up by the
 424         "issue" phase, so execute is fairly straightforward.
 425         """
 426
 427         comb = m.d.comb
 428         sync = m.d.sync
 429         pdecode2 = self.pdecode2
 430
 431         # temporaries
 432         core_busy_o = core.busy_o                 # core is busy
 433         core_ivalid_i = core.ivalid_i             # instruction is valid
 434         core_issue_i = core.issue_i               # instruction is issued
 435         insn_type = core.e.do.insn_type           # instruction MicroOp type
 436
 437         with m.FSM(name="exec_fsm"):
 438
 439             # waiting for instruction bus (stays there until not busy)
 440             with m.State("INSN_START"):
 441                 comb += exec_insn_ready_o.eq(1)
 442                 with m.If(exec_insn_valid_i):
 443                     comb += core_ivalid_i.eq(1)  # instruction is valid
 444                     comb += core_issue_i.eq(1)  # and issued
 445                     sync += sv_changed.eq(0)
 446                     sync += pc_changed.eq(0)
 447                     m.next = "INSN_ACTIVE"  # move to "wait completion"
 448
 449             # instruction started: must wait till it finishes
 450             with m.State("INSN_ACTIVE"):
 451                 with m.If(insn_type != MicrOp.OP_NOP):
 452                     comb += core_ivalid_i.eq(1) # instruction is valid
 453                 # note changes to PC and SVSTATE
 454                 with m.If(self.state_nia.wen & (1<<StateRegs.SVSTATE)):
 455                     sync += sv_changed.eq(1)
 456                 with m.If(self.state_nia.wen & (1<<StateRegs.PC)):
 457                     sync += pc_changed.eq(1)
 458                 with m.If(~core_busy_o): # instruction done!
 459                     comb += exec_pc_valid_o.eq(1)
 460                     with m.If(exec_pc_ready_i):
 461                         comb += self.insn_done.eq(1)
 462                         m.next = "INSN_START"  # back to fetch
 463
 464     def elaborate(self, platform):
 465         m = Module()
 466         comb, sync = m.d.comb, m.d.sync
 467
 468         m.submodules.core = core = DomainRenamer("coresync")(self.core)
 469         m.submodules.imem = imem = self.imem
 470         m.submodules.dbg = dbg = self.dbg
 471         if self.jtag_en:
 472             m.submodules.jtag = jtag = self.jtag
 473             # TODO: UART2GDB mux, here, from external pin
 474             # see https://bugs.libre-soc.org/show_bug.cgi?id=499
 475             sync += dbg.dmi.connect_to(jtag.dmi)
 476
 477         cur_state = self.cur_state
 478
 479         # 4x 4k SRAM blocks.  these simply "exist", they get routed in litex
 480         if self.sram4x4k:
 481             for i, sram in enumerate(self.sram4k):
 482                 m.submodules["sram4k_%d" % i] = sram
 483                 comb += sram.enable.eq(self.wb_sram_en)
 484
 485         # XICS interrupt handler
 486         if self.xics:
 487             m.submodules.xics_icp = icp = self.xics_icp
 488             m.submodules.xics_ics = ics = self.xics_ics
 489             comb += icp.ics_i.eq(ics.icp_o)           # connect ICS to ICP
 490             sync += cur_state.eint.eq(icp.core_irq_o) # connect ICP to core
 491
 492         # GPIO test peripheral
 493         if self.gpio:
 494             m.submodules.simple_gpio = simple_gpio = self.simple_gpio
 495
 496         # connect one GPIO output to ICS bit 15 (like in microwatt soc.vhdl)
 497         # XXX causes litex ECP5 test to get wrong idea about input and output
 498         # (but works with verilator sim *sigh*)
 499         #if self.gpio and self.xics:
 500         #   comb += self.int_level_i[15].eq(simple_gpio.gpio_o[0])
 501
 502         # instruction decoder
 503         pdecode = create_pdecode()
 504         m.submodules.dec2 = pdecode2 = self.pdecode2
 505         if self.svp64_en:
 506             m.submodules.svp64 = svp64 = self.svp64
 507
 508         # convenience
 509         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 510         intrf = self.core.regs.rf['int']
 511
 512         # clock delay power-on reset
 513         cd_por  = ClockDomain(reset_less=True)
 514         cd_sync = ClockDomain()
 515         core_sync = ClockDomain("coresync")
 516         m.domains += cd_por, cd_sync, core_sync
 517
 518         ti_rst = Signal(reset_less=True)
 519         delay = Signal(range(4), reset=3)
 520         with m.If(delay != 0):
 521             m.d.por += delay.eq(delay - 1)
 522         comb += cd_por.clk.eq(ClockSignal())
 523
 524         # power-on reset delay
 525         core_rst = ResetSignal("coresync")
 526         comb += ti_rst.eq(delay != 0 | dbg.core_rst_o | ResetSignal())
 527         comb += core_rst.eq(ti_rst)
 528
 529         # busy/halted signals from core
 530         comb += self.busy_o.eq(core.busy_o)
 531         comb += pdecode2.dec.bigendian.eq(self.core_bigendian_i)
 532
 533         # temporary hack: says "go" immediately for both address gen and ST
 534         l0 = core.l0
 535         ldst = core.fus.fus['ldst0']
 536         st_go_edge = rising_edge(m, ldst.st.rel_o)
 537         m.d.comb += ldst.ad.go_i.eq(ldst.ad.rel_o) # link addr-go direct to rel
 538         m.d.comb += ldst.st.go_i.eq(st_go_edge) # link store-go to rising rel
 539
 540         # PC and instruction from I-Memory
 541         comb += self.pc_o.eq(cur_state.pc)
 542         pc_changed = Signal() # note write to PC
 543         sv_changed = Signal() # note write to SVSTATE
 544
 545         # read the PC
 546         pc = Signal(64, reset_less=True)
 547         pc_ok_delay = Signal()
 548         sync += pc_ok_delay.eq(~self.pc_i.ok)
 549         with m.If(self.pc_i.ok):
 550             # incoming override (start from pc_i)
 551             comb += pc.eq(self.pc_i.data)
 552         with m.Else():
 553             # otherwise read StateRegs regfile for PC...
 554             comb += self.state_r_pc.ren.eq(1<<StateRegs.PC)
 555         # ... but on a 1-clock delay
 556         with m.If(pc_ok_delay):
 557             comb += pc.eq(self.state_r_pc.data_o)
 558
 559         # read svstate
 560         svstate = Signal(64, reset_less=True)
 561         svstate_ok_delay = Signal()
 562         sync += svstate_ok_delay.eq(~self.svstate_i.ok)
 563         with m.If(self.svstate_i.ok):
 564             # incoming override (start from svstate__i)
 565             comb += svstate.eq(self.svstate_i.data)
 566         with m.Else():
 567             # otherwise read StateRegs regfile for SVSTATE...
 568             comb += self.state_r_sv.ren.eq(1 << StateRegs.SVSTATE)
 569         # ... but on a 1-clock delay
 570         with m.If(svstate_ok_delay):
 571             comb += svstate.eq(self.state_r_sv.data_o)
 572
 573         # don't write pc every cycle
 574         comb += self.state_w_pc.wen.eq(0)
 575         comb += self.state_w_pc.data_i.eq(0)
 576
 577         # don't read msr every cycle
 578         comb += self.state_r_msr.ren.eq(0)
 579
 580         # address of the next instruction, in the absence of a branch
 581         # depends on the instruction size
 582         nia = Signal(64, reset_less=True)
 583
 584         # connect up debug signals
 585         # TODO comb += core.icache_rst_i.eq(dbg.icache_rst_o)
 586         comb += dbg.terminate_i.eq(core.core_terminate_o)
 587         comb += dbg.state.pc.eq(pc)
 588         comb += dbg.state.svstate.eq(svstate)
 589         comb += dbg.state.msr.eq(cur_state.msr)
 590
 591         # pass the prefix mode from Fetch to Issue, so the latter can loop
 592         # on VL==0
 593         is_svp64_mode = Signal()
 594
 595         # there are *THREE* FSMs, fetch (32/64-bit) issue, decode/execute.
 596         # these are the handshake signals between fetch and decode/execute
 597
 598         # fetch FSM can run as soon as the PC is valid
 599         fetch_pc_valid_i = Signal() # Execute tells Fetch "start next read"
 600         fetch_pc_ready_o = Signal() # Fetch Tells SVSTATE "proceed"
 601
 602         # fetch FSM hands over the instruction to be decoded / issued
 603         fetch_insn_valid_o = Signal()
 604         fetch_insn_ready_i = Signal()
 605
 606         # issue FSM delivers the instruction to the be executed
 607         exec_insn_valid_i = Signal()
 608         exec_insn_ready_o = Signal()
 609
 610         # execute FSM, hands over the PC/SVSTATE back to the issue FSM
 611         exec_pc_valid_o = Signal()
 612         exec_pc_ready_i = Signal()
 613
 614         # the FSMs here are perhaps unusual in that they detect conditions
 615         # then "hold" information, combinatorially, for the core
 616         # (as opposed to using sync - which would be on a clock's delay)
 617         # this includes the actual opcode, valid flags and so on.
 618
 619         # Fetch, then Issue, then Execute. Issue is where the VL for-loop
 620         # lives.  the ready/valid signalling is used to communicate between
 621         # the three.
 622
 623         self.fetch_fsm(m, core, pc, svstate, nia, is_svp64_mode,
 624                        fetch_pc_ready_o, fetch_pc_valid_i,
 625                        fetch_insn_valid_o, fetch_insn_ready_i)
 626
 627         self.issue_fsm(m, core, pc_changed, sv_changed, nia,
 628                        dbg, core_rst, is_svp64_mode,
 629                        fetch_pc_ready_o, fetch_pc_valid_i,
 630                        fetch_insn_valid_o, fetch_insn_ready_i,
 631                        exec_insn_valid_i, exec_insn_ready_o,
 632                        exec_pc_valid_o, exec_pc_ready_i)
 633
 634         self.execute_fsm(m, core, pc_changed, sv_changed,
 635                          exec_insn_valid_i, exec_insn_ready_o,
 636                          exec_pc_valid_o, exec_pc_ready_i)
 637
 638         # this bit doesn't have to be in the FSM: connect up to read
 639         # regfiles on demand from DMI
 640         self.do_dmi(m, dbg)
 641
 642         # DEC and TB inc/dec FSM.  copy of DEC is put into CoreState,
 643         # (which uses that in PowerDecoder2 to raise 0x900 exception)
 644         self.tb_dec_fsm(m, cur_state.dec)
 645
 646         return m
 647
 648     def do_dmi(self, m, dbg):
 649         comb = m.d.comb
 650         sync = m.d.sync
 651         dmi, d_reg, d_cr, d_xer, = dbg.dmi, dbg.d_gpr, dbg.d_cr, dbg.d_xer
 652         intrf = self.core.regs.rf['int']
 653
 654         with m.If(d_reg.req): # request for regfile access being made
 655             # TODO: error-check this
 656             # XXX should this be combinatorial?  sync better?
 657             if intrf.unary:
 658                 comb += self.int_r.ren.eq(1<<d_reg.addr)
 659             else:
 660                 comb += self.int_r.addr.eq(d_reg.addr)
 661                 comb += self.int_r.ren.eq(1)
 662         d_reg_delay  = Signal()
 663         sync += d_reg_delay.eq(d_reg.req)
 664         with m.If(d_reg_delay):
 665             # data arrives one clock later
 666             comb += d_reg.data.eq(self.int_r.data_o)
 667             comb += d_reg.ack.eq(1)
 668
 669         # sigh same thing for CR debug
 670         with m.If(d_cr.req): # request for regfile access being made
 671             comb += self.cr_r.ren.eq(0b11111111) # enable all
 672         d_cr_delay  = Signal()
 673         sync += d_cr_delay.eq(d_cr.req)
 674         with m.If(d_cr_delay):
 675             # data arrives one clock later
 676             comb += d_cr.data.eq(self.cr_r.data_o)
 677             comb += d_cr.ack.eq(1)
 678
 679         # aaand XER...
 680         with m.If(d_xer.req): # request for regfile access being made
 681             comb += self.xer_r.ren.eq(0b111111) # enable all
 682         d_xer_delay  = Signal()
 683         sync += d_xer_delay.eq(d_xer.req)
 684         with m.If(d_xer_delay):
 685             # data arrives one clock later
 686             comb += d_xer.data.eq(self.xer_r.data_o)
 687             comb += d_xer.ack.eq(1)
 688
 689     def tb_dec_fsm(self, m, spr_dec):
 690         """tb_dec_fsm
 691
 692         this is a FSM for updating either dec or tb.  it runs alternately
 693         DEC, TB, DEC, TB.  note that SPR pipeline could have written a new
 694         value to DEC, however the regfile has "passthrough" on it so this
 695         *should* be ok.
 696
 697         see v3.0B p1097-1099 for Timeer Resource and p1065 and p1076
 698         """
 699
 700         comb, sync = m.d.comb, m.d.sync
 701         fast_rf = self.core.regs.rf['fast']
 702         fast_r_dectb = fast_rf.r_ports['issue'] # DEC/TB
 703         fast_w_dectb = fast_rf.w_ports['issue'] # DEC/TB
 704
 705         with m.FSM() as fsm:
 706
 707             # initiates read of current DEC
 708             with m.State("DEC_READ"):
 709                 comb += fast_r_dectb.addr.eq(FastRegs.DEC)
 710                 comb += fast_r_dectb.ren.eq(1)
 711                 m.next = "DEC_WRITE"
 712
 713             # waits for DEC read to arrive (1 cycle), updates with new value
 714             with m.State("DEC_WRITE"):
 715                 new_dec = Signal(64)
 716                 # TODO: MSR.LPCR 32-bit decrement mode
 717                 comb += new_dec.eq(fast_r_dectb.data_o - 1)
 718                 comb += fast_w_dectb.addr.eq(FastRegs.DEC)
 719                 comb += fast_w_dectb.wen.eq(1)
 720                 comb += fast_w_dectb.data_i.eq(new_dec)
 721                 sync += spr_dec.eq(new_dec) # copy into cur_state for decoder
 722                 m.next = "TB_READ"
 723
 724             # initiates read of current TB
 725             with m.State("TB_READ"):
 726                 comb += fast_r_dectb.addr.eq(FastRegs.TB)
 727                 comb += fast_r_dectb.ren.eq(1)
 728                 m.next = "TB_WRITE"
 729
 730             # waits for read TB to arrive, initiates write of current TB
 731             with m.State("TB_WRITE"):
 732                 new_tb = Signal(64)
 733                 comb += new_tb.eq(fast_r_dectb.data_o + 1)
 734                 comb += fast_w_dectb.addr.eq(FastRegs.TB)
 735                 comb += fast_w_dectb.wen.eq(1)
 736                 comb += fast_w_dectb.data_i.eq(new_tb)
 737                 m.next = "DEC_READ"
 738
 739         return m
 740
 741     def __iter__(self):
 742         yield from self.pc_i.ports()
 743         yield self.pc_o
 744         yield self.memerr_o
 745         yield from self.core.ports()
 746         yield from self.imem.ports()
 747         yield self.core_bigendian_i
 748         yield self.busy_o
 749
 750     def ports(self):
 751         return list(self)
 752
 753     def external_ports(self):
 754         ports = self.pc_i.ports()
 755         ports += [self.pc_o, self.memerr_o, self.core_bigendian_i, self.busy_o,
 756                 ]
 757
 758         if self.jtag_en:
 759             ports += list(self.jtag.external_ports())
 760         else:
 761             # don't add DMI if JTAG is enabled
 762             ports += list(self.dbg.dmi.ports())
 763
 764         ports += list(self.imem.ibus.fields.values())
 765         ports += list(self.core.l0.cmpi.lsmem.lsi.slavebus.fields.values())
 766
 767         if self.sram4x4k:
 768             for sram in self.sram4k:
 769                 ports += list(sram.bus.fields.values())
 770
 771         if self.xics:
 772             ports += list(self.xics_icp.bus.fields.values())
 773             ports += list(self.xics_ics.bus.fields.values())
 774             ports.append(self.int_level_i)
 775
 776         if self.gpio:
 777             ports += list(self.simple_gpio.bus.fields.values())
 778             ports.append(self.gpio_o)
 779
 780         return ports
 781
 782     def ports(self):
 783         return list(self)
 784
 785
 786 class TestIssuer(Elaboratable):
 787     def __init__(self, pspec):
 788         self.ti = TestIssuerInternal(pspec)
 789
 790         self.pll = DummyPLL()
 791
 792         # PLL direct clock or not
 793         self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 794         if self.pll_en:
 795             self.pll_18_o = Signal(reset_less=True)
 796
 797     def elaborate(self, platform):
 798         m = Module()
 799         comb = m.d.comb
 800
 801         # TestIssuer runs at direct clock
 802         m.submodules.ti = ti = self.ti
 803         cd_int = ClockDomain("coresync")
 804
 805         if self.pll_en:
 806             # ClockSelect runs at PLL output internal clock rate
 807             m.submodules.pll = pll = self.pll
 808
 809             # add clock domains from PLL
 810             cd_pll = ClockDomain("pllclk")
 811             m.domains += cd_pll
 812
 813             # PLL clock established.  has the side-effect of running clklsel
 814             # at the PLL's speed (see DomainRenamer("pllclk") above)
 815             pllclk = ClockSignal("pllclk")
 816             comb += pllclk.eq(pll.clk_pll_o)
 817
 818             # wire up external 24mhz to PLL
 819             comb += pll.clk_24_i.eq(ClockSignal())
 820
 821             # output 18 mhz PLL test signal
 822             comb += self.pll_18_o.eq(pll.pll_18_o)
 823
 824             # now wire up ResetSignals.  don't mind them being in this domain
 825             pll_rst = ResetSignal("pllclk")
 826             comb += pll_rst.eq(ResetSignal())
 827
 828         # internal clock is set to selector clock-out.  has the side-effect of
 829         # running TestIssuer at this speed (see DomainRenamer("intclk") above)
 830         intclk = ClockSignal("coresync")
 831         if self.pll_en:
 832             comb += intclk.eq(pll.clk_pll_o)
 833         else:
 834             comb += intclk.eq(ClockSignal())
 835
 836         return m
 837
 838     def ports(self):
 839         return list(self.ti.ports()) + list(self.pll.ports()) + \
 840                [ClockSignal(), ResetSignal()]
 841
 842     def external_ports(self):
 843         ports = self.ti.external_ports()
 844         ports.append(ClockSignal())
 845         ports.append(ResetSignal())
 846         if self.pll_en:
 847             ports.append(self.pll.clk_sel_i)
 848             ports.append(self.pll_18_o)
 849             ports.append(self.pll.pll_lck_o)
 850         return ports
 851
 852
 853 if __name__ == '__main__':
 854     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
 855              'spr': 1,
 856              'div': 1,
 857              'mul': 1,
 858              'shiftrot': 1
 859             }
 860     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
 861                          imem_ifacetype='bare_wb',
 862                          addr_wid=48,
 863                          mask_wid=8,
 864                          reg_wid=64,
 865                          units=units)
 866     dut = TestIssuer(pspec)
 867     vl = main(dut, ports=dut.ports(), name="test_issuer")
 868
 869     if len(sys.argv) == 1:
 870         vl = rtlil.convert(dut, ports=dut.external_ports(), name="test_issuer")
 871         with open("test_issuer.il", "w") as f:
 872             f.write(vl)