src/soc/simple/issuer_verilog.py

   1 """simple core issuer verilog generator
   2 """
   3
   4 import argparse
   5 from nmigen.cli import verilog
   6
   7 from soc.config.test.test_loadstore import TestMemPspec
   8 from soc.simple.issuer import TestIssuer
   9
  10
  11 if __name__ == '__main__':
  12     parser = argparse.ArgumentParser(description="Simple core issuer " \
  13                                      "verilog generator")
  14     parser.add_argument("output_filename")
  15     parser.add_argument("--enable-xics", dest='xics', action="store_true",
  16                         help="Enable interrupts",
  17                         default=True)
  18     parser.add_argument("--disable-xics", dest='xics', action="store_false",
  19                         help="Disable interrupts",
  20                         default=False)
  21     parser.add_argument("--enable-core", dest='core', action="store_true",
  22                         help="Enable main core",
  23                         default=True)
  24     parser.add_argument("--disable-core", dest='core', action="store_false",
  25                         help="disable main core",
  26                         default=False)
  27     parser.add_argument("--enable-pll", dest='pll', action="store_true",
  28                         help="Enable pll",
  29                         default=False)
  30     parser.add_argument("--disable-pll", dest='pll', action="store_false",
  31                         help="Disable pll",
  32                         default=False)
  33     parser.add_argument("--enable-testgpio", action="store_true",
  34                         help="Disable gpio pins",
  35                         default=False)
  36     parser.add_argument("--enable-sram4x4kblock", action="store_true",
  37                         help="Disable sram 4x4k block",
  38                         default=False)
  39     parser.add_argument("--debug", default="jtag", help="Select debug " \
  40                         "interface [jtag | dmi] [default jtag]")
  41
  42     args = parser.parse_args()
  43
  44     print(args)
  45
  46     units = {'alu': 1,
  47              'cr': 1, 'branch': 1, 'trap': 1,
  48              'logical': 1,
  49              'spr': 1,
  50              'div': 1,
  51              'mul': 1,
  52              'shiftrot': 1
  53             }
  54
  55     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
  56                          imem_ifacetype='bare_wb',
  57                          addr_wid=48,
  58                          mask_wid=8,
  59                          # must leave at 64
  60                          reg_wid=64,
  61                          # set to 32 for instruction-memory width=32
  62                          imem_reg_wid=64,
  63                          # set to 32 to make data wishbone bus 32-bit
  64                          #wb_data_wid=32,
  65                          xics=args.xics, # XICS interrupt controller
  66                          nocore=not args.core, # test coriolis2 ioring
  67                          use_pll=args.pll,  # bypass PLL
  68                          gpio=args.enable_testgpio, # for test purposes
  69                          sram4x4kblock=args.enable_sram4x4kblock, # add SRAMs
  70                          debug=args.debug,      # set to jtag or dmi
  71                          units=units)
  72
  73     print("nocore", pspec.__dict__["nocore"])
  74     print("gpio", pspec.__dict__["gpio"])
  75     print("sram4x4kblock", pspec.__dict__["sram4x4kblock"])
  76     print("xics", pspec.__dict__["xics"])
  77     print("use_pll", pspec.__dict__["use_pll"])
  78     print("debug", pspec.__dict__["debug"])
  79
  80     dut = TestIssuer(pspec)
  81
  82     vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
  83     with open(args.output_filename, "w") as f:
  84         f.write(vl)