src/soc/simple/test/test_issuer_mmu_microwatt.py

   1 """simple core test, runs instructions from a TestMemory
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6 """
   7
   8 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   9 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  10
  11 import unittest
  12 import sys
  13
  14 # here is the logic which takes test cases and "executes" them.
  15 # in this instance (TestRunner) its job is to instantiate both
  16 # a Libre-SOC nmigen-based HDL instance and an ISACaller python
  17 # simulator.  it's also responsible for performing the single
  18 # step and comparison.
  19 from soc.simple.test.test_runner import TestRunner
  20
  21 #@platen:bookmarks
  22 #src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
  23
  24 # test with MMU
  25 from openpower.test.mmu.mmu_cases import MMUTestCase
  26 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
  27 from openpower.test.ldst.ldst_cases import LDSTTestCase
  28 from openpower.test.ldst.ldst_exc_cases import LDSTExceptionTestCase
  29 #from openpower.simulator.test_sim import (GeneralTestCases, AttnTestCase)
  30
  31 from openpower.simulator.program import Program
  32 from openpower.endian import bigendian
  33 from openpower.test.common import TestAccumulatorBase
  34
  35 from openpower.consts import MSR
  36
  37 from soc.experiment.test import pagetables
  38
  39
  40 class MMUTestCase(TestAccumulatorBase):
  41
  42     def case_microwatt_test_3_mmu_ld(self):
  43         lst = [
  44                "ld 6,0(2)",
  45               ]
  46
  47         # set up regs
  48         initial_regs = [0] * 32
  49         initial_regs[2] = 0x124108
  50
  51         # no pre-loaded memory here
  52         initial_mem = {
  53              0x12010: 0x0a00010000000000,
  54              0x10000: 0x0930010000000080,
  55              0x8108: 0x0000000badc0ffee,
  56         }
  57
  58         # set virtual and non-privileged
  59         # msr: 8000000000000011
  60         initial_msr = 0 << MSR.PR # must set "problem" state
  61         initial_msr |= 1 << MSR.LE # little-endian
  62         initial_msr |= 1 << MSR.SF # 64-bit
  63         initial_msr |= 1 << MSR.DR # set "virtual" state for data
  64
  65         # set PRTBL to 0x12000
  66         initial_sprs = {720: 0x12000, # PRTBL
  67                         48: 1       # PIDR
  68                         }
  69
  70         print("MMUTEST: initial_msr=",initial_msr)
  71         self.add_case(Program(lst, bigendian), initial_regs,
  72                              initial_mem=initial_mem,
  73                              initial_sprs=initial_sprs,
  74                              initial_msr=initial_msr)
  75
  76
  77
  78 mmu_test3 = {
  79              0x12010: 0x0a00010000000000,
  80              0x10000: 0x0930010000000080,
  81              0x8108: 0x0000000badc0ffee,
  82             }
  83
  84 if __name__ == "__main__":
  85     svp64 = True
  86     if len(sys.argv) == 2:
  87         if sys.argv[1] == 'nosvp64':
  88             svp64 = False
  89         sys.argv.pop()
  90
  91     print ("SVP64 test mode enabled", svp64)
  92
  93     unittest.main(exit=False)
  94     suite = unittest.TestSuite()
  95
  96     # MMU/DCache integration tests
  97     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
  98                               microwatt_mmu=True,
  99                               rom=mmu_test3))
 100
 101     runner = unittest.TextTestRunner()
 102     runner.run(suite)