src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
   7 """
   8 from nmigen import Module, Signal, Cat, ClockSignal
   9 from nmigen.hdl.xfrm import ResetInserter
  10 from copy import copy
  11
  12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  14 from nmutil.sim_tmp_alternative import Simulator, Settle
  15
  16 from nmutil.formaltest import FHDLTestCase
  17 from nmutil.gtkw import write_gtkw
  18 from nmigen.cli import rtlil
  19 from openpower.decoder.isa.caller import special_sprs, SVP64State
  20 from openpower.decoder.isa.all import ISA
  21 from openpower.endian import bigendian
  22
  23 from openpower.decoder.power_decoder import create_pdecode
  24 from openpower.decoder.power_decoder2 import PowerDecode2
  25 from soc.regfile.regfiles import StateRegs
  26
  27 from soc.simple.issuer import TestIssuerInternal
  28
  29 from soc.config.test.test_loadstore import TestMemPspec
  30 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
  31                                        wait_for_busy_clear,
  32                                        wait_for_busy_hi)
  33 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  34                                                  check_sim_memory)
  35 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  36 from nmutil.util import wrap
  37 from soc.experiment.test.test_mmu_dcache import wb_get
  38 from openpower.test.state import TestState
  39
  40
  41 def setup_i_memory(imem, startaddr, instructions):
  42     mem = imem
  43     print("insn before, init mem", mem.depth, mem.width, mem,
  44           len(instructions))
  45     for i in range(mem.depth):
  46         yield mem._array[i].eq(0)
  47     yield Settle()
  48     startaddr //= 4  # instructions are 32-bit
  49     if mem.width == 32:
  50         mask = ((1 << 32)-1)
  51         for ins in instructions:
  52             if isinstance(ins, tuple):
  53                 insn, code = ins
  54             else:
  55                 insn, code = ins, ''
  56             insn = insn & 0xffffffff
  57             yield mem._array[startaddr].eq(insn)
  58             yield Settle()
  59             if insn != 0:
  60                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  61             startaddr += 1
  62             startaddr = startaddr & mask
  63         return
  64
  65     # 64 bit
  66     mask = ((1 << 64)-1)
  67     for ins in instructions:
  68         if isinstance(ins, tuple):
  69             insn, code = ins
  70         else:
  71             insn, code = ins, ''
  72         insn = insn & 0xffffffff
  73         msbs = (startaddr >> 1) & mask
  74         val = yield mem._array[msbs]
  75         if insn != 0:
  76             print("before set", hex(4*startaddr),
  77                   hex(msbs), hex(val), hex(insn))
  78         lsb = 1 if (startaddr & 1) else 0
  79         val = (val | (insn << (lsb*32)))
  80         val = val & mask
  81         yield mem._array[msbs].eq(val)
  82         yield Settle()
  83         if insn != 0:
  84             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  85             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  86         startaddr += 1
  87         startaddr = startaddr & mask
  88
  89
  90 def set_dmi(dmi, addr, data):
  91     yield dmi.req_i.eq(1)
  92     yield dmi.addr_i.eq(addr)
  93     yield dmi.din.eq(data)
  94     yield dmi.we_i.eq(1)
  95     while True:
  96         ack = yield dmi.ack_o
  97         if ack:
  98             break
  99         yield
 100     yield
 101     yield dmi.req_i.eq(0)
 102     yield dmi.addr_i.eq(0)
 103     yield dmi.din.eq(0)
 104     yield dmi.we_i.eq(0)
 105     yield
 106
 107
 108 def get_dmi(dmi, addr):
 109     yield dmi.req_i.eq(1)
 110     yield dmi.addr_i.eq(addr)
 111     yield dmi.din.eq(0)
 112     yield dmi.we_i.eq(0)
 113     while True:
 114         ack = yield dmi.ack_o
 115         if ack:
 116             break
 117         yield
 118     yield  # wait one
 119     data = yield dmi.dout  # get data after ack valid for 1 cycle
 120     yield dmi.req_i.eq(0)
 121     yield dmi.addr_i.eq(0)
 122     yield dmi.we_i.eq(0)
 123     yield
 124     return data
 125
 126
 127 def run_hdl_state(dut, test, issuer, pc_i, svstate_i, instructions):
 128     """run_hdl_state - runs a TestIssuer nmigen HDL simulation
 129     """
 130
 131     imem = issuer.imem._get_memory()
 132     core = issuer.core
 133     dmi = issuer.dbg.dmi
 134     pdecode2 = issuer.pdecode2
 135     l0 = core.l0
 136     hdl_states = []
 137
 138     # establish the TestIssuer context (mem, regs etc)
 139
 140     pc = 0  # start address
 141     counter = 0  # test to pause/start
 142
 143     yield from setup_i_memory(imem, pc, instructions)
 144     yield from setup_tst_memory(l0, test.mem)
 145     yield from setup_regs(pdecode2, core, test)
 146
 147     # set PC and SVSTATE
 148     yield pc_i.eq(pc)
 149     yield issuer.pc_i.ok.eq(1)
 150
 151     # copy initial SVSTATE
 152     initial_svstate = copy(test.svstate)
 153     if isinstance(initial_svstate, int):
 154         initial_svstate = SVP64State(initial_svstate)
 155     yield svstate_i.eq(initial_svstate.value)
 156     yield issuer.svstate_i.ok.eq(1)
 157     yield
 158
 159     print("instructions", instructions)
 160
 161     # run the loop of the instructions on the current test
 162     index = (yield issuer.cur_state.pc) // 4
 163     while index < len(instructions):
 164         ins, code = instructions[index]
 165
 166         print("hdl instr: 0x{:X}".format(ins & 0xffffffff))
 167         print(index, code)
 168
 169         if counter == 0:
 170             # start the core
 171             yield
 172             yield from set_dmi(dmi, DBGCore.CTRL,
 173                                1<<DBGCtrl.START)
 174             yield issuer.pc_i.ok.eq(0) # no change PC after this
 175             yield issuer.svstate_i.ok.eq(0) # ditto
 176             yield
 177             yield
 178
 179         counter = counter + 1
 180
 181         # wait until executed
 182         while not (yield issuer.insn_done):
 183             yield
 184
 185         yield Settle()
 186
 187         index = (yield issuer.cur_state.pc) // 4
 188
 189         terminated = yield issuer.dbg.terminated_o
 190         print("terminated", terminated)
 191
 192         if index < len(instructions):
 193             # Get HDL mem and state
 194             state = yield from TestState("hdl", core, dut,
 195                                          code)
 196             hdl_states.append(state)
 197
 198         if index >= len(instructions):
 199             print ("index over, send dmi stop")
 200             # stop at end
 201             yield from set_dmi(dmi, DBGCore.CTRL,
 202                                1<<DBGCtrl.STOP)
 203             yield
 204             yield
 205
 206         terminated = yield issuer.dbg.terminated_o
 207         print("terminated(2)", terminated)
 208         if terminated:
 209             break
 210
 211     return hdl_states
 212
 213
 214 def run_sim_state(dut, test, simdec2, instructions, gen, insncode):
 215     """run_sim_state - runs an ISACaller simulation
 216     """
 217
 218     sim_states = []
 219
 220     # set up the Simulator (which must track TestIssuer exactly)
 221     sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 222               test.msr,
 223               initial_insns=gen, respect_pc=True,
 224               disassembly=insncode,
 225               bigendian=bigendian,
 226               initial_svstate=test.svstate)
 227
 228     # run the loop of the instructions on the current test
 229     index = sim.pc.CIA.value//4
 230     while index < len(instructions):
 231         ins, code = instructions[index]
 232
 233         print("sim instr: 0x{:X}".format(ins & 0xffffffff))
 234         print(index, code)
 235
 236         # set up simulated instruction (in simdec2)
 237         try:
 238             yield from sim.setup_one()
 239         except KeyError:  # instruction not in imem: stop
 240             break
 241         yield Settle()
 242
 243         # call simulated operation
 244         print("sim", code)
 245         yield from sim.execute_one()
 246         yield Settle()
 247         index = sim.pc.CIA.value//4
 248
 249         # get sim register and memory TestState, add to list
 250         state = yield from TestState("sim", sim, dut, code)
 251         sim_states.append(state)
 252
 253     return sim_states
 254
 255
 256 class TestRunner(FHDLTestCase):
 257     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 258                         svp64=True):
 259         super().__init__("run_all")
 260         self.test_data = tst_data
 261         self.microwatt_mmu = microwatt_mmu
 262         self.rom = rom
 263         self.svp64 = svp64
 264
 265     def run_all(self):
 266         m = Module()
 267         comb = m.d.comb
 268         pc_i = Signal(32)
 269         svstate_i = Signal(64)
 270
 271         if self.microwatt_mmu:
 272             ldst_ifacetype = 'test_mmu_cache_wb'
 273         else:
 274             ldst_ifacetype = 'test_bare_wb'
 275         imem_ifacetype = 'test_bare_wb'
 276
 277         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 278                              imem_ifacetype=imem_ifacetype,
 279                              addr_wid=48,
 280                              mask_wid=8,
 281                              imem_reg_wid=64,
 282                              # wb_data_width=32,
 283                              use_pll=False,
 284                              nocore=False,
 285                              xics=False,
 286                              gpio=False,
 287                              regreduce=True,
 288                              svp64=self.svp64,
 289                              mmu=self.microwatt_mmu,
 290                              reg_wid=64)
 291         #hard_reset = Signal(reset_less=True)
 292         issuer = TestIssuerInternal(pspec)
 293         # use DMI RESET command instead, this does actually work though
 294         #issuer = ResetInserter({'coresync': hard_reset,
 295         #                        'sync': hard_reset})(issuer)
 296         m.submodules.issuer = issuer
 297         dmi = issuer.dbg.dmi
 298
 299         regreduce_en = pspec.regreduce_en == True
 300         simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
 301         m.submodules.simdec2 = simdec2  # pain in the neck
 302
 303         # run core clock at same rate as test clock
 304         intclk = ClockSignal("coresync")
 305         comb += intclk.eq(ClockSignal())
 306
 307         comb += issuer.pc_i.data.eq(pc_i)
 308         comb += issuer.svstate_i.data.eq(svstate_i)
 309
 310         # nmigen Simulation
 311         sim = Simulator(m)
 312         sim.add_clock(1e-6)
 313
 314         def process():
 315
 316             # start in stopped
 317             yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 318             yield
 319
 320             # get each test, completely reset the core, and run it
 321
 322             for test in self.test_data:
 323
 324                 # set up bigendian (TODO: don't do this, use MSR)
 325                 yield issuer.core_bigendian_i.eq(bigendian)
 326                 yield Settle()
 327
 328                 yield
 329                 yield
 330                 yield
 331                 yield
 332
 333                 print(test.name)
 334                 program = test.program
 335                 with self.subTest(test.name):
 336                     print("regs", test.regs)
 337                     print("sprs", test.sprs)
 338                     print("cr", test.cr)
 339                     print("mem", test.mem)
 340                     print("msr", test.msr)
 341                     print("assem", program.assembly)
 342                     gen = list(program.generate_instructions())
 343                     insncode = program.assembly.splitlines()
 344                     instructions = list(zip(gen, insncode))
 345
 346                     # Run two tests (TODO, move these to functions)
 347                     # * first the Simulator, collate a batch of results
 348                     # * then the HDL, likewise
 349                     #   (actually, the other way round because running
 350                     #    Simulator somehow modifies the test state!)
 351                     # * finally, compare all the results
 352
 353                     ##########
 354                     # 1. HDL
 355                     ##########
 356                     hdl_states = yield from run_hdl_state(self, test, issuer,
 357                                                           pc_i, svstate_i,
 358                                                           instructions)
 359
 360                     ##########
 361                     # 2. Simulator
 362                     ##########
 363
 364                     sim_states = yield from run_sim_state(self, test, simdec2,
 365                                                           instructions, gen,
 366                                                           insncode)
 367
 368                     ###############
 369                     # 3. Compare
 370                     ###############
 371
 372                     for simstate, hdlstate in zip(sim_states, hdl_states):
 373                         simstate.compare(hdlstate)     # register check
 374                         simstate.compare_mem(hdlstate) # memory check
 375
 376                     print ("hdl_states")
 377                     for state in hdl_states:
 378                         print (state)
 379
 380                     print ("sim_states")
 381                     for state in sim_states:
 382                         print (state)
 383
 384                     # compare against expected results
 385                     if test.expected is not None:
 386                         # have to put these in manually
 387                         test.expected.to_test = test.expected
 388                         test.expected.dut = self
 389                         test.expected.state_type = "expected"
 390                         test.expected.code = 0
 391                         # do actual comparison, against last item
 392                         sim_states[-1].compare(test.expected)
 393
 394                     self.assertTrue(len(hdl_states) == len(sim_states),
 395                                     "number of instructions run not the same")
 396
 397                 # stop at end
 398                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 399                 yield
 400                 yield
 401
 402                 # TODO, here is where the static (expected) results
 403                 # can be checked: register check (TODO, memory check)
 404                 # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 405                 # yield from check_regs(self, sim, core, test, code,
 406                 #                       >>>expected_data<<<)
 407
 408                 # get CR
 409                 cr = yield from get_dmi(dmi, DBGCore.CR)
 410                 print("after test %s cr value %x" % (test.name, cr))
 411
 412                 # get XER
 413                 xer = yield from get_dmi(dmi, DBGCore.XER)
 414                 print("after test %s XER value %x" % (test.name, xer))
 415
 416                 # test of dmi reg get
 417                 for int_reg in range(32):
 418                     yield from set_dmi(dmi, DBGCore.GSPR_IDX, int_reg)
 419                     value = yield from get_dmi(dmi, DBGCore.GSPR_DATA)
 420
 421                     print("after test %s reg %2d value %x" %
 422                           (test.name, int_reg, value))
 423
 424                 # pull a reset
 425                 yield from set_dmi(dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 426                 yield
 427
 428         styles = {
 429             'dec': {'base': 'dec'},
 430             'bin': {'base': 'bin'},
 431             'closed': {'closed': True}
 432         }
 433
 434         traces = [
 435             'clk',
 436             ('state machines', 'closed', [
 437                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 438                 'fetch_fsm_state',
 439                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 440                 'pred_insn_i_valid', 'pred_insn_o_ready',
 441                 'fetch_predicate_state',
 442                 'pred_mask_o_valid', 'pred_mask_i_ready',
 443                 'issue_fsm_state',
 444                 'exec_insn_i_valid', 'exec_insn_o_ready',
 445                 'exec_fsm_state',
 446                 'exec_pc_o_valid', 'exec_pc_i_ready',
 447                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 448                 'is_last', 'dec2.no_out_vec']),
 449             {'comment': 'fetch and decode'},
 450             (None, 'dec', [
 451                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
 452                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 453             'raw_insn_i[31:0]',
 454             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 455             ('svp64 decoding', 'closed', [
 456                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 457                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 458                 'dec2.sv_rm_dec.ptype_in',
 459                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 460                 'dstmask[63:0]', 'srcmask[63:0]',
 461                 'dregread[4:0]', 'dinvert',
 462                 'sregread[4:0]', 'sinvert',
 463                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 464                 'core.int.pred__ren']),
 465             ('register augmentation', 'dec', 'closed', [
 466                 {'comment': 'v3.0b registers'},
 467                 'dec2.dec_o.RT[4:0]',
 468                 'dec2.dec_a.RA[4:0]',
 469                 'dec2.dec_b.RB[4:0]',
 470                 ('Rdest', [
 471                     'dec2.o_svdec.reg_in[4:0]',
 472                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 473                     'dec2.o_svdec.reg_out[6:0]']),
 474                 ('Rsrc1', [
 475                     'dec2.in1_svdec.reg_in[4:0]',
 476                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 477                     'dec2.in1_svdec.reg_out[6:0]']),
 478                 ('Rsrc1', [
 479                     'dec2.in2_svdec.reg_in[4:0]',
 480                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 481                     'dec2.in2_svdec.reg_out[6:0]']),
 482                 {'comment': 'SVP64 registers'},
 483                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 484             ]),
 485             {'comment': 'svp64 context'},
 486             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 487             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 488             'core_core_dststep[6:0]',
 489             {'comment': 'issue and execute'},
 490             'core.core_core_insn_type',
 491             (None, 'dec', [
 492                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 493             'issue_i', 'busy_o',
 494             {'comment': 'dmi'},
 495             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 496             {'comment': 'instruction memory'},
 497             'imem.sram.rdport.memory(0)[63:0]',
 498             {'comment': 'registers'},
 499             # match with soc.regfile.regfiles.IntRegs port names
 500             'core.int.rp_src1.memory(0)[63:0]',
 501             'core.int.rp_src1.memory(1)[63:0]',
 502             'core.int.rp_src1.memory(2)[63:0]',
 503             'core.int.rp_src1.memory(3)[63:0]',
 504             'core.int.rp_src1.memory(4)[63:0]',
 505             'core.int.rp_src1.memory(5)[63:0]',
 506             'core.int.rp_src1.memory(6)[63:0]',
 507             'core.int.rp_src1.memory(7)[63:0]',
 508             'core.int.rp_src1.memory(9)[63:0]',
 509             'core.int.rp_src1.memory(10)[63:0]',
 510             'core.int.rp_src1.memory(13)[63:0]'
 511         ]
 512
 513         # PortInterface module path varies depending on MMU option
 514         if self.microwatt_mmu:
 515             pi_module = 'core.ldst0'
 516         else:
 517             pi_module = 'core.fus.ldst0'
 518
 519         traces += [('ld/st port interface', {'submodule': pi_module}, [
 520             'oper_r__insn_type',
 521             'ldst_port0_is_ld_i',
 522             'ldst_port0_is_st_i',
 523             'ldst_port0_busy_o',
 524             'ldst_port0_addr_i[47:0]',
 525             'ldst_port0_addr_i_ok',
 526             'ldst_port0_addr_ok_o',
 527             'ldst_port0_exc_happened',
 528             'ldst_port0_st_data_i[63:0]',
 529             'ldst_port0_st_data_i_ok',
 530             'ldst_port0_ld_data_o[63:0]',
 531             'ldst_port0_ld_data_o_ok',
 532             'exc_o_happened',
 533             'cancel'
 534         ])]
 535
 536         if self.microwatt_mmu:
 537             traces += [
 538                 {'comment': 'microwatt_mmu'},
 539                 'core.fus.mmu0.alu_mmu0.illegal',
 540                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 541                 'core.fus.mmu0.alu_mmu0.mmu.state',
 542                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 543                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 544                 {'comment': 'wishbone_memory'},
 545                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 546                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 547                 'core.fus.mmu0.alu_mmu0.dcache.we',
 548                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 549                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 550             ]
 551
 552         write_gtkw("issuer_simulator.gtkw",
 553                    "issuer_simulator.vcd",
 554                    traces, styles, module='top.issuer')
 555
 556         # add run of instructions
 557         sim.add_sync_process(process)
 558
 559         # optionally, if a wishbone-based ROM is passed in, run that as an
 560         # extra emulated process
 561         if self.rom is not None:
 562             dcache = core.fus.fus["mmu0"].alu.dcache
 563             default_mem = self.rom
 564             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 565
 566         with sim.write_vcd("issuer_simulator.vcd"):
 567             sim.run()