src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
   7 """
   8 from nmigen import Module, Signal, Cat, ClockSignal
   9 from nmigen.hdl.xfrm import ResetInserter
  10 from copy import copy
  11
  12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  14 from nmutil.sim_tmp_alternative import Simulator, Settle
  15
  16 from nmutil.formaltest import FHDLTestCase
  17 from nmutil.gtkw import write_gtkw
  18 from nmigen.cli import rtlil
  19 from openpower.decoder.isa.caller import special_sprs, SVP64State
  20 from openpower.decoder.isa.all import ISA
  21 from openpower.endian import bigendian
  22
  23 from openpower.decoder.power_decoder import create_pdecode
  24 from openpower.decoder.power_decoder2 import PowerDecode2
  25 from soc.regfile.regfiles import StateRegs
  26
  27 from soc.simple.issuer import TestIssuerInternal
  28
  29 from soc.config.test.test_loadstore import TestMemPspec
  30 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
  31                                        wait_for_busy_clear,
  32                                        wait_for_busy_hi)
  33 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  34                                                  check_sim_memory)
  35 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  36 from nmutil.util import wrap
  37 from soc.experiment.test.test_mmu_dcache import wb_get
  38 from openpower.test.state import TestState, StateRunner
  39
  40
  41 def setup_i_memory(imem, startaddr, instructions):
  42     mem = imem
  43     print("insn before, init mem", mem.depth, mem.width, mem,
  44           len(instructions))
  45     for i in range(mem.depth):
  46         yield mem._array[i].eq(0)
  47     yield Settle()
  48     startaddr //= 4  # instructions are 32-bit
  49     if mem.width == 32:
  50         mask = ((1 << 32)-1)
  51         for ins in instructions:
  52             if isinstance(ins, tuple):
  53                 insn, code = ins
  54             else:
  55                 insn, code = ins, ''
  56             insn = insn & 0xffffffff
  57             yield mem._array[startaddr].eq(insn)
  58             yield Settle()
  59             if insn != 0:
  60                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  61             startaddr += 1
  62             startaddr = startaddr & mask
  63         return
  64
  65     # 64 bit
  66     mask = ((1 << 64)-1)
  67     for ins in instructions:
  68         if isinstance(ins, tuple):
  69             insn, code = ins
  70         else:
  71             insn, code = ins, ''
  72         insn = insn & 0xffffffff
  73         msbs = (startaddr >> 1) & mask
  74         val = yield mem._array[msbs]
  75         if insn != 0:
  76             print("before set", hex(4*startaddr),
  77                   hex(msbs), hex(val), hex(insn))
  78         lsb = 1 if (startaddr & 1) else 0
  79         val = (val | (insn << (lsb*32)))
  80         val = val & mask
  81         yield mem._array[msbs].eq(val)
  82         yield Settle()
  83         if insn != 0:
  84             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  85             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  86         startaddr += 1
  87         startaddr = startaddr & mask
  88
  89
  90 def set_dmi(dmi, addr, data):
  91     yield dmi.req_i.eq(1)
  92     yield dmi.addr_i.eq(addr)
  93     yield dmi.din.eq(data)
  94     yield dmi.we_i.eq(1)
  95     while True:
  96         ack = yield dmi.ack_o
  97         if ack:
  98             break
  99         yield
 100     yield
 101     yield dmi.req_i.eq(0)
 102     yield dmi.addr_i.eq(0)
 103     yield dmi.din.eq(0)
 104     yield dmi.we_i.eq(0)
 105     yield
 106
 107
 108 def get_dmi(dmi, addr):
 109     yield dmi.req_i.eq(1)
 110     yield dmi.addr_i.eq(addr)
 111     yield dmi.din.eq(0)
 112     yield dmi.we_i.eq(0)
 113     while True:
 114         ack = yield dmi.ack_o
 115         if ack:
 116             break
 117         yield
 118     yield  # wait one
 119     data = yield dmi.dout  # get data after ack valid for 1 cycle
 120     yield dmi.req_i.eq(0)
 121     yield dmi.addr_i.eq(0)
 122     yield dmi.we_i.eq(0)
 123     yield
 124     return data
 125
 126
 127 class SimRunner(StateRunner):
 128     def __init__(self, dut, m, pspec):
 129         self.dut = dut
 130
 131         regreduce_en = pspec.regreduce_en == True
 132         self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
 133         m.submodules.simdec2 = simdec2  # pain in the neck
 134
 135     def prepare_for_test(self, test):
 136         self.test = test
 137
 138     def run_test(self, instructions, gen, insncode):
 139         """run_sim_state - runs an ISACaller simulation
 140         """
 141
 142         dut, test, simdec2 = self.dut, self.test, self.simdec2
 143         sim_states = []
 144
 145         # set up the Simulator (which must track TestIssuer exactly)
 146         sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 147                   test.msr,
 148                   initial_insns=gen, respect_pc=True,
 149                   disassembly=insncode,
 150                   bigendian=bigendian,
 151                   initial_svstate=test.svstate)
 152
 153         # run the loop of the instructions on the current test
 154         index = sim.pc.CIA.value//4
 155         while index < len(instructions):
 156             ins, code = instructions[index]
 157
 158             print("sim instr: 0x{:X}".format(ins & 0xffffffff))
 159             print(index, code)
 160
 161             # set up simulated instruction (in simdec2)
 162             try:
 163                 yield from sim.setup_one()
 164             except KeyError:  # instruction not in imem: stop
 165                 break
 166             yield Settle()
 167
 168             # call simulated operation
 169             print("sim", code)
 170             yield from sim.execute_one()
 171             yield Settle()
 172             index = sim.pc.CIA.value//4
 173
 174             # get sim register and memory TestState, add to list
 175             state = yield from TestState("sim", sim, dut, code)
 176             sim_states.append(state)
 177
 178         return sim_states
 179
 180
 181 class HDLRunner(StateRunner):
 182     def __init__(self, dut, m, pspec, pc_i, svstate_i):
 183         self.dut = dut
 184         self.pc_i = pc_i
 185         self.svstate_i = svstate_i
 186
 187         #hard_reset = Signal(reset_less=True)
 188         self.issuer = TestIssuerInternal(pspec)
 189         # use DMI RESET command instead, this does actually work though
 190         #issuer = ResetInserter({'coresync': hard_reset,
 191         #                        'sync': hard_reset})(issuer)
 192         m.submodules.issuer = self.issuer
 193         self.dmi = self.issuer.dbg.dmi
 194
 195     def prepare_for_test(self, test):
 196         self.test = test
 197
 198         # set up bigendian (TODO: don't do this, use MSR)
 199         yield self.issuer.core_bigendian_i.eq(bigendian)
 200         yield Settle()
 201
 202         yield
 203         yield
 204         yield
 205         yield
 206
 207     def setup_during_test(self):
 208         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 209         yield
 210
 211     def run_test(self, instructions):
 212         """run_hdl_state - runs a TestIssuer nmigen HDL simulation
 213         """
 214
 215         imem = self.issuer.imem._get_memory()
 216         core = self.issuer.core
 217         dmi = self.issuer.dbg.dmi
 218         pdecode2 = self.issuer.pdecode2
 219         l0 = core.l0
 220         hdl_states = []
 221
 222         # establish the TestIssuer context (mem, regs etc)
 223
 224         pc = 0  # start address
 225         counter = 0  # test to pause/start
 226
 227         yield from setup_i_memory(imem, pc, instructions)
 228         #yield from setup_tst_memory(l0, self.test.mem)
 229         yield from setup_regs(pdecode2, core, self.test)
 230
 231         # set PC and SVSTATE
 232         yield self.pc_i.eq(pc)
 233         yield self.issuer.pc_i.ok.eq(1)
 234
 235         # copy initial SVSTATE
 236         initial_svstate = copy(self.test.svstate)
 237         if isinstance(initial_svstate, int):
 238             initial_svstate = SVP64State(initial_svstate)
 239         yield self.svstate_i.eq(initial_svstate.value)
 240         yield self.issuer.svstate_i.ok.eq(1)
 241         yield
 242
 243         print("instructions", instructions)
 244
 245         # run the loop of the instructions on the current test
 246         index = (yield self.issuer.cur_state.pc) // 4
 247         while index < len(instructions):
 248             ins, code = instructions[index]
 249
 250             print("hdl instr: 0x{:X}".format(ins & 0xffffffff))
 251             print(index, code)
 252
 253             if counter == 0:
 254                 # start the core
 255                 yield
 256                 yield from set_dmi(dmi, DBGCore.CTRL,
 257                                 1<<DBGCtrl.START)
 258                 yield self.issuer.pc_i.ok.eq(0) # no change PC after this
 259                 yield self.issuer.svstate_i.ok.eq(0) # ditto
 260                 yield
 261                 yield
 262
 263             counter = counter + 1
 264
 265             # wait until executed
 266             while not (yield self.issuer.insn_done):
 267                 yield
 268
 269             yield Settle()
 270
 271             index = (yield self.issuer.cur_state.pc) // 4
 272
 273             terminated = yield self.issuer.dbg.terminated_o
 274             print("terminated", terminated)
 275
 276             if index < len(instructions):
 277                 # Get HDL mem and state
 278                 state = yield from TestState("hdl", core, self.dut,
 279                                             code)
 280                 hdl_states.append(state)
 281
 282             if index >= len(instructions):
 283                 print ("index over, send dmi stop")
 284                 # stop at end
 285                 yield from set_dmi(dmi, DBGCore.CTRL,
 286                                 1<<DBGCtrl.STOP)
 287                 yield
 288                 yield
 289
 290             terminated = yield self.issuer.dbg.terminated_o
 291             print("terminated(2)", terminated)
 292             if terminated:
 293                 break
 294
 295         return hdl_states
 296
 297     def end_test(self):
 298         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 299         yield
 300         yield
 301
 302         # TODO, here is where the static (expected) results
 303         # can be checked: register check (TODO, memory check)
 304         # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 305         # yield from check_regs(self, sim, core, test, code,
 306         #                       >>>expected_data<<<)
 307
 308         # get CR
 309         cr = yield from get_dmi(self.dmi, DBGCore.CR)
 310         print("after test %s cr value %x" % (self.test.name, cr))
 311
 312         # get XER
 313         xer = yield from get_dmi(self.dmi, DBGCore.XER)
 314         print("after test %s XER value %x" % (self.test.name, xer))
 315
 316         # test of dmi reg get
 317         for int_reg in range(32):
 318             yield from set_dmi(self.dmi, DBGCore.GSPR_IDX, int_reg)
 319             value = yield from get_dmi(self.dmi, DBGCore.GSPR_DATA)
 320
 321             print("after test %s reg %2d value %x" %
 322             (self.test.name, int_reg, value))
 323
 324         # pull a reset
 325         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 326         yield
 327
 328
 329 class TestRunner(FHDLTestCase):
 330     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 331                         svp64=True, run_hdl=True, run_sim=True):
 332         super().__init__("run_all")
 333         self.test_data = tst_data
 334         self.microwatt_mmu = microwatt_mmu
 335         self.rom = rom
 336         self.svp64 = svp64
 337         self.run_hdl = run_hdl
 338         self.run_sim = run_sim
 339
 340     def run_all(self):
 341         m = Module()
 342         comb = m.d.comb
 343         if self.microwatt_mmu:
 344             ldst_ifacetype = 'test_mmu_cache_wb'
 345         else:
 346             ldst_ifacetype = 'test_bare_wb'
 347         imem_ifacetype = 'test_bare_wb'
 348
 349         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 350                              imem_ifacetype=imem_ifacetype,
 351                              addr_wid=48,
 352                              mask_wid=8,
 353                              imem_reg_wid=64,
 354                              # wb_data_width=32,
 355                              use_pll=False,
 356                              nocore=False,
 357                              xics=False,
 358                              gpio=False,
 359                              regreduce=True,
 360                              svp64=self.svp64,
 361                              mmu=self.microwatt_mmu,
 362                              reg_wid=64)
 363
 364         ###### SETUP PHASE #######
 365         # StateRunner.setup_for_test()
 366
 367         if self.run_hdl:
 368             pc_i = Signal(32)
 369             svstate_i = Signal(64)
 370             hdlrun = HDLRunner(self, m, pspec, pc_i, svstate_i)
 371
 372         if self.run_sim:
 373             simrun = SimRunner(self, m, pspec)
 374
 375         # run core clock at same rate as test clock
 376         intclk = ClockSignal("coresync")
 377         comb += intclk.eq(ClockSignal())
 378
 379         if self.run_hdl:
 380             comb += hdlrun.issuer.pc_i.data.eq(pc_i)
 381             comb += hdlrun.issuer.svstate_i.data.eq(svstate_i)
 382
 383         # nmigen Simulation - everything runs around this, so it
 384         # still has to be created.
 385         sim = Simulator(m)
 386         sim.add_clock(1e-6)
 387
 388         def process():
 389
 390             ###### PREPARATION PHASE AT START OF RUNNING #######
 391             # StateRunner.setup_during_test()
 392
 393             if self.run_sim:
 394                 simrun.setup_during_test() # TODO, some arguments?
 395
 396             if self.run_hdl:
 397                 yield from hdlrun.setup_during_test()
 398
 399             # get each test, completely reset the core, and run it
 400
 401             for test in self.test_data:
 402
 403                 with self.subTest(test.name):
 404
 405                     ###### PREPARATION PHASE AT START OF TEST #######
 406                     # StateRunner.prepare_for_test()
 407
 408                     if self.run_sim:
 409                         simrun.prepare_for_test(test)
 410
 411                     if self.run_hdl:
 412                         yield from hdlrun.prepare_for_test(test)
 413
 414                     print(test.name)
 415                     program = test.program
 416                     print("regs", test.regs)
 417                     print("sprs", test.sprs)
 418                     print("cr", test.cr)
 419                     print("mem", test.mem)
 420                     print("msr", test.msr)
 421                     print("assem", program.assembly)
 422                     gen = list(program.generate_instructions())
 423                     insncode = program.assembly.splitlines()
 424                     instructions = list(zip(gen, insncode))
 425
 426                     ###### RUNNING OF EACH TEST #######
 427                     # StateRunner.step_test()
 428
 429                     # Run two tests (TODO, move these to functions)
 430                     # * first the Simulator, collate a batch of results
 431                     # * then the HDL, likewise
 432                     #   (actually, the other way round because running
 433                     #    Simulator somehow modifies the test state!)
 434                     # * finally, compare all the results
 435
 436                     ##########
 437                     # 1. HDL
 438                     ##########
 439                     if self.run_hdl:
 440                         hdl_states = yield from hdlrun.run_test(instructions)
 441
 442                     ##########
 443                     # 2. Simulator
 444                     ##########
 445
 446                     if self.run_sim:
 447                         sim_states = yield from simrun.run_test(
 448                                                           instructions, gen,
 449                                                           insncode)
 450
 451                     ###### COMPARING THE TESTS #######
 452
 453                     ###############
 454                     # 3. Compare
 455                     ###############
 456
 457                     if self.run_sim:
 458                         last_sim = copy(sim_states[-1])
 459                     elif self.run_hdl:
 460                         last_sim = copy(hdl_states[-1])
 461                     else:
 462                         last_sim = None # err what are you doing??
 463
 464                     if self.run_hdl and self.run_sim:
 465                         for simstate, hdlstate in zip(sim_states, hdl_states):
 466                             simstate.compare(hdlstate)     # register check
 467                             simstate.compare_mem(hdlstate) # memory check
 468
 469                     if self.run_hdl:
 470                         print ("hdl_states")
 471                         for state in hdl_states:
 472                             print (state)
 473
 474                     if self.run_sim:
 475                         print ("sim_states")
 476                         for state in sim_states:
 477                             print (state)
 478
 479                     # compare against expected results
 480                     if test.expected is not None:
 481                         # have to put these in manually
 482                         test.expected.to_test = test.expected
 483                         test.expected.dut = self
 484                         test.expected.state_type = "expected"
 485                         test.expected.code = 0
 486                         # do actual comparison, against last item
 487                         last_sim.compare(test.expected)
 488
 489                     if self.run_hdl and self.run_sim:
 490                         self.assertTrue(len(hdl_states) == len(sim_states),
 491                                     "number of instructions run not the same")
 492
 493                 ###### END OF A TEST #######
 494                 # StateRunner.end_test()
 495
 496                 if self.run_sim:
 497                     simrun.end_test() # TODO, some arguments?
 498
 499                 if self.run_hdl:
 500                     yield from hdlrun.end_test()
 501                     """
 502                     yield from set_dmi(hdlrun.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 503                     yield
 504                     yield
 505
 506                     # TODO, here is where the static (expected) results
 507                     # can be checked: register check (TODO, memory check)
 508                     # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 509                     # yield from check_regs(self, sim, core, test, code,
 510                     #                       >>>expected_data<<<)
 511
 512                     # get CR
 513                     cr = yield from get_dmi(hdlrun.dmi, DBGCore.CR)
 514                     print("after test %s cr value %x" % (test.name, cr))
 515
 516                     # get XER
 517                     xer = yield from get_dmi(hdlrun.dmi, DBGCore.XER)
 518                     print("after test %s XER value %x" % (test.name, xer))
 519
 520                     # test of dmi reg get
 521                     for int_reg in range(32):
 522                         yield from set_dmi(hdlrun.dmi, DBGCore.GSPR_IDX, int_reg)
 523                         value = yield from get_dmi(hdlrun.dmi, DBGCore.GSPR_DATA)
 524
 525                         print("after test %s reg %2d value %x" %
 526                               (test.name, int_reg, value))
 527
 528                     # pull a reset
 529                     yield from set_dmi(hdlrun.dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 530                     yield
 531                     """
 532         ###### END OF EVERYTHING (but none needs doing, still call fn) #######
 533         # StateRunner.cleanup()
 534
 535         if self.run_sim:
 536             simrun.cleanup() # TODO, some arguments?
 537
 538         if self.run_hdl:
 539             hdlrun.cleanup()
 540
 541         styles = {
 542             'dec': {'base': 'dec'},
 543             'bin': {'base': 'bin'},
 544             'closed': {'closed': True}
 545         }
 546
 547         traces = [
 548             'clk',
 549             ('state machines', 'closed', [
 550                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 551                 'fetch_fsm_state',
 552                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 553                 'pred_insn_i_valid', 'pred_insn_o_ready',
 554                 'fetch_predicate_state',
 555                 'pred_mask_o_valid', 'pred_mask_i_ready',
 556                 'issue_fsm_state',
 557                 'exec_insn_i_valid', 'exec_insn_o_ready',
 558                 'exec_fsm_state',
 559                 'exec_pc_o_valid', 'exec_pc_i_ready',
 560                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 561                 'is_last', 'dec2.no_out_vec']),
 562             {'comment': 'fetch and decode'},
 563             (None, 'dec', [
 564                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
 565                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 566             'raw_insn_i[31:0]',
 567             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 568             ('svp64 decoding', 'closed', [
 569                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 570                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 571                 'dec2.sv_rm_dec.ptype_in',
 572                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 573                 'dstmask[63:0]', 'srcmask[63:0]',
 574                 'dregread[4:0]', 'dinvert',
 575                 'sregread[4:0]', 'sinvert',
 576                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 577                 'core.int.pred__ren']),
 578             ('register augmentation', 'dec', 'closed', [
 579                 {'comment': 'v3.0b registers'},
 580                 'dec2.dec_o.RT[4:0]',
 581                 'dec2.dec_a.RA[4:0]',
 582                 'dec2.dec_b.RB[4:0]',
 583                 ('Rdest', [
 584                     'dec2.o_svdec.reg_in[4:0]',
 585                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 586                     'dec2.o_svdec.reg_out[6:0]']),
 587                 ('Rsrc1', [
 588                     'dec2.in1_svdec.reg_in[4:0]',
 589                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 590                     'dec2.in1_svdec.reg_out[6:0]']),
 591                 ('Rsrc1', [
 592                     'dec2.in2_svdec.reg_in[4:0]',
 593                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 594                     'dec2.in2_svdec.reg_out[6:0]']),
 595                 {'comment': 'SVP64 registers'},
 596                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 597             ]),
 598             {'comment': 'svp64 context'},
 599             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 600             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 601             'core_core_dststep[6:0]',
 602             {'comment': 'issue and execute'},
 603             'core.core_core_insn_type',
 604             (None, 'dec', [
 605                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 606             'issue_i', 'busy_o',
 607             {'comment': 'dmi'},
 608             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 609             {'comment': 'instruction memory'},
 610             'imem.sram.rdport.memory(0)[63:0]',
 611             {'comment': 'registers'},
 612             # match with soc.regfile.regfiles.IntRegs port names
 613             'core.int.rp_src1.memory(0)[63:0]',
 614             'core.int.rp_src1.memory(1)[63:0]',
 615             'core.int.rp_src1.memory(2)[63:0]',
 616             'core.int.rp_src1.memory(3)[63:0]',
 617             'core.int.rp_src1.memory(4)[63:0]',
 618             'core.int.rp_src1.memory(5)[63:0]',
 619             'core.int.rp_src1.memory(6)[63:0]',
 620             'core.int.rp_src1.memory(7)[63:0]',
 621             'core.int.rp_src1.memory(9)[63:0]',
 622             'core.int.rp_src1.memory(10)[63:0]',
 623             'core.int.rp_src1.memory(13)[63:0]'
 624         ]
 625
 626         # PortInterface module path varies depending on MMU option
 627         if self.microwatt_mmu:
 628             pi_module = 'core.ldst0'
 629         else:
 630             pi_module = 'core.fus.ldst0'
 631
 632         traces += [('ld/st port interface', {'submodule': pi_module}, [
 633             'oper_r__insn_type',
 634             'ldst_port0_is_ld_i',
 635             'ldst_port0_is_st_i',
 636             'ldst_port0_busy_o',
 637             'ldst_port0_addr_i[47:0]',
 638             'ldst_port0_addr_i_ok',
 639             'ldst_port0_addr_ok_o',
 640             'ldst_port0_exc_happened',
 641             'ldst_port0_st_data_i[63:0]',
 642             'ldst_port0_st_data_i_ok',
 643             'ldst_port0_ld_data_o[63:0]',
 644             'ldst_port0_ld_data_o_ok',
 645             'exc_o_happened',
 646             'cancel'
 647         ])]
 648
 649         if self.microwatt_mmu:
 650             traces += [
 651                 {'comment': 'microwatt_mmu'},
 652                 'core.fus.mmu0.alu_mmu0.illegal',
 653                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 654                 'core.fus.mmu0.alu_mmu0.mmu.state',
 655                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 656                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 657                 {'comment': 'wishbone_memory'},
 658                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 659                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 660                 'core.fus.mmu0.alu_mmu0.dcache.we',
 661                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 662                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 663             ]
 664
 665         write_gtkw("issuer_simulator.gtkw",
 666                    "issuer_simulator.vcd",
 667                    traces, styles, module='top.issuer')
 668
 669         # add run of instructions
 670         sim.add_sync_process(process)
 671
 672         # optionally, if a wishbone-based ROM is passed in, run that as an
 673         # extra emulated process
 674         if self.rom is not None:
 675             dcache = core.fus.fus["mmu0"].alu.dcache
 676             default_mem = self.rom
 677             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 678
 679         with sim.write_vcd("issuer_simulator.vcd"):
 680             sim.run()