src/soc/simple/test/test_runner.py

   1 """TestRunner class, runs TestIssuer instructions
   2
   3 related bugs:
   4
   5  * https://bugs.libre-soc.org/show_bug.cgi?id=363
   6  * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
   7 """
   8 from nmigen import Module, Signal, Cat, ClockSignal
   9 from nmigen.hdl.xfrm import ResetInserter
  10 from copy import copy
  11
  12 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
  13 # Also, check out the cxxsim nmigen branch, and latest yosys from git
  14 from nmutil.sim_tmp_alternative import Simulator, Settle
  15
  16 from nmutil.formaltest import FHDLTestCase
  17 from nmutil.gtkw import write_gtkw
  18 from nmigen.cli import rtlil
  19 from openpower.decoder.isa.caller import special_sprs, SVP64State
  20 from openpower.decoder.isa.all import ISA
  21 from openpower.endian import bigendian
  22
  23 from openpower.decoder.power_decoder import create_pdecode
  24 from openpower.decoder.power_decoder2 import PowerDecode2
  25 from soc.regfile.regfiles import StateRegs
  26
  27 from soc.simple.issuer import TestIssuerInternal
  28
  29 from soc.config.test.test_loadstore import TestMemPspec
  30 from soc.simple.test.test_core import (setup_regs, check_regs, check_mem,
  31                                        wait_for_busy_clear,
  32                                        wait_for_busy_hi)
  33 from soc.fu.compunits.test.test_compunit import (setup_tst_memory,
  34                                                  check_sim_memory)
  35 from soc.debug.dmi import DBGCore, DBGCtrl, DBGStat
  36 from nmutil.util import wrap
  37 from soc.experiment.test.test_mmu_dcache import wb_get
  38 from openpower.test.state import TestState, StateRunner
  39
  40
  41 def setup_i_memory(imem, startaddr, instructions):
  42     mem = imem
  43     print("insn before, init mem", mem.depth, mem.width, mem,
  44           len(instructions))
  45     for i in range(mem.depth):
  46         yield mem._array[i].eq(0)
  47     yield Settle()
  48     startaddr //= 4  # instructions are 32-bit
  49     if mem.width == 32:
  50         mask = ((1 << 32)-1)
  51         for ins in instructions:
  52             if isinstance(ins, tuple):
  53                 insn, code = ins
  54             else:
  55                 insn, code = ins, ''
  56             insn = insn & 0xffffffff
  57             yield mem._array[startaddr].eq(insn)
  58             yield Settle()
  59             if insn != 0:
  60                 print("instr: %06x 0x%x %s" % (4*startaddr, insn, code))
  61             startaddr += 1
  62             startaddr = startaddr & mask
  63         return
  64
  65     # 64 bit
  66     mask = ((1 << 64)-1)
  67     for ins in instructions:
  68         if isinstance(ins, tuple):
  69             insn, code = ins
  70         else:
  71             insn, code = ins, ''
  72         insn = insn & 0xffffffff
  73         msbs = (startaddr >> 1) & mask
  74         val = yield mem._array[msbs]
  75         if insn != 0:
  76             print("before set", hex(4*startaddr),
  77                   hex(msbs), hex(val), hex(insn))
  78         lsb = 1 if (startaddr & 1) else 0
  79         val = (val | (insn << (lsb*32)))
  80         val = val & mask
  81         yield mem._array[msbs].eq(val)
  82         yield Settle()
  83         if insn != 0:
  84             print("after  set", hex(4*startaddr), hex(msbs), hex(val))
  85             print("instr: %06x 0x%x %s %08x" % (4*startaddr, insn, code, val))
  86         startaddr += 1
  87         startaddr = startaddr & mask
  88
  89
  90 def set_dmi(dmi, addr, data):
  91     yield dmi.req_i.eq(1)
  92     yield dmi.addr_i.eq(addr)
  93     yield dmi.din.eq(data)
  94     yield dmi.we_i.eq(1)
  95     while True:
  96         ack = yield dmi.ack_o
  97         if ack:
  98             break
  99         yield
 100     yield
 101     yield dmi.req_i.eq(0)
 102     yield dmi.addr_i.eq(0)
 103     yield dmi.din.eq(0)
 104     yield dmi.we_i.eq(0)
 105     yield
 106
 107
 108 def get_dmi(dmi, addr):
 109     yield dmi.req_i.eq(1)
 110     yield dmi.addr_i.eq(addr)
 111     yield dmi.din.eq(0)
 112     yield dmi.we_i.eq(0)
 113     while True:
 114         ack = yield dmi.ack_o
 115         if ack:
 116             break
 117         yield
 118     yield  # wait one
 119     data = yield dmi.dout  # get data after ack valid for 1 cycle
 120     yield dmi.req_i.eq(0)
 121     yield dmi.addr_i.eq(0)
 122     yield dmi.we_i.eq(0)
 123     yield
 124     return data
 125
 126
 127 class SimRunner(StateRunner):
 128     def __init__(self, dut, m, pspec):
 129         self.dut = dut
 130
 131         regreduce_en = pspec.regreduce_en == True
 132         self.simdec2 = simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
 133         m.submodules.simdec2 = simdec2  # pain in the neck
 134
 135     def prepare_for_test(self, test):
 136         self.test = test
 137
 138     def run_test(self, instructions, gen, insncode):
 139         """run_sim_state - runs an ISACaller simulation
 140         """
 141
 142         dut, test, simdec2 = self.dut, self.test, self.simdec2
 143         sim_states = []
 144
 145         # set up the Simulator (which must track TestIssuer exactly)
 146         sim = ISA(simdec2, test.regs, test.sprs, test.cr, test.mem,
 147                   test.msr,
 148                   initial_insns=gen, respect_pc=True,
 149                   disassembly=insncode,
 150                   bigendian=bigendian,
 151                   initial_svstate=test.svstate)
 152
 153         # run the loop of the instructions on the current test
 154         index = sim.pc.CIA.value//4
 155         while index < len(instructions):
 156             ins, code = instructions[index]
 157
 158             print("sim instr: 0x{:X}".format(ins & 0xffffffff))
 159             print(index, code)
 160
 161             # set up simulated instruction (in simdec2)
 162             try:
 163                 yield from sim.setup_one()
 164             except KeyError:  # instruction not in imem: stop
 165                 break
 166             yield Settle()
 167
 168             # call simulated operation
 169             print("sim", code)
 170             yield from sim.execute_one()
 171             yield Settle()
 172             index = sim.pc.CIA.value//4
 173
 174             # get sim register and memory TestState, add to list
 175             state = yield from TestState("sim", sim, dut, code)
 176             sim_states.append(state)
 177
 178         return sim_states
 179
 180
 181 class HDLRunner(StateRunner):
 182     def __init__(self, dut, m, pspec):
 183         self.dut = dut
 184         self.pc_i = Signal(32)
 185         self.svstate_i = Signal(64)
 186
 187         #hard_reset = Signal(reset_less=True)
 188         self.issuer = TestIssuerInternal(pspec)
 189         # use DMI RESET command instead, this does actually work though
 190         #issuer = ResetInserter({'coresync': hard_reset,
 191         #                        'sync': hard_reset})(issuer)
 192         m.submodules.issuer = self.issuer
 193         self.dmi = self.issuer.dbg.dmi
 194
 195         comb = m.d.comb
 196         comb += self.issuer.pc_i.data.eq(self.pc_i)
 197         comb += self.issuer.svstate_i.data.eq(self.svstate_i)
 198
 199     def prepare_for_test(self, test):
 200         self.test = test
 201
 202         # set up bigendian (TODO: don't do this, use MSR)
 203         yield self.issuer.core_bigendian_i.eq(bigendian)
 204         yield Settle()
 205
 206         yield
 207         yield
 208         yield
 209         yield
 210
 211     def setup_during_test(self):
 212         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 213         yield
 214
 215     def run_test(self, instructions):
 216         """run_hdl_state - runs a TestIssuer nmigen HDL simulation
 217         """
 218
 219         imem = self.issuer.imem._get_memory()
 220         core = self.issuer.core
 221         dmi = self.issuer.dbg.dmi
 222         pdecode2 = self.issuer.pdecode2
 223         l0 = core.l0
 224         hdl_states = []
 225
 226         # establish the TestIssuer context (mem, regs etc)
 227
 228         pc = 0  # start address
 229         counter = 0  # test to pause/start
 230
 231         yield from setup_i_memory(imem, pc, instructions)
 232         #yield from setup_tst_memory(l0, self.test.mem)
 233         yield from setup_regs(pdecode2, core, self.test)
 234
 235         # set PC and SVSTATE
 236         yield self.pc_i.eq(pc)
 237         yield self.issuer.pc_i.ok.eq(1)
 238
 239         # copy initial SVSTATE
 240         initial_svstate = copy(self.test.svstate)
 241         if isinstance(initial_svstate, int):
 242             initial_svstate = SVP64State(initial_svstate)
 243         yield self.svstate_i.eq(initial_svstate.value)
 244         yield self.issuer.svstate_i.ok.eq(1)
 245         yield
 246
 247         print("instructions", instructions)
 248
 249         # run the loop of the instructions on the current test
 250         index = (yield self.issuer.cur_state.pc) // 4
 251         while index < len(instructions):
 252             ins, code = instructions[index]
 253
 254             print("hdl instr: 0x{:X}".format(ins & 0xffffffff))
 255             print(index, code)
 256
 257             if counter == 0:
 258                 # start the core
 259                 yield
 260                 yield from set_dmi(dmi, DBGCore.CTRL,
 261                                 1<<DBGCtrl.START)
 262                 yield self.issuer.pc_i.ok.eq(0) # no change PC after this
 263                 yield self.issuer.svstate_i.ok.eq(0) # ditto
 264                 yield
 265                 yield
 266
 267             counter = counter + 1
 268
 269             # wait until executed
 270             while not (yield self.issuer.insn_done):
 271                 yield
 272
 273             yield Settle()
 274
 275             index = (yield self.issuer.cur_state.pc) // 4
 276
 277             terminated = yield self.issuer.dbg.terminated_o
 278             print("terminated", terminated)
 279
 280             if index < len(instructions):
 281                 # Get HDL mem and state
 282                 state = yield from TestState("hdl", core, self.dut,
 283                                             code)
 284                 hdl_states.append(state)
 285
 286             if index >= len(instructions):
 287                 print ("index over, send dmi stop")
 288                 # stop at end
 289                 yield from set_dmi(dmi, DBGCore.CTRL,
 290                                 1<<DBGCtrl.STOP)
 291                 yield
 292                 yield
 293
 294             terminated = yield self.issuer.dbg.terminated_o
 295             print("terminated(2)", terminated)
 296             if terminated:
 297                 break
 298
 299         return hdl_states
 300
 301     def end_test(self):
 302         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.STOP)
 303         yield
 304         yield
 305
 306         # TODO, here is where the static (expected) results
 307         # can be checked: register check (TODO, memory check)
 308         # see https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
 309         # yield from check_regs(self, sim, core, test, code,
 310         #                       >>>expected_data<<<)
 311
 312         # get CR
 313         cr = yield from get_dmi(self.dmi, DBGCore.CR)
 314         print("after test %s cr value %x" % (self.test.name, cr))
 315
 316         # get XER
 317         xer = yield from get_dmi(self.dmi, DBGCore.XER)
 318         print("after test %s XER value %x" % (self.test.name, xer))
 319
 320         # test of dmi reg get
 321         for int_reg in range(32):
 322             yield from set_dmi(self.dmi, DBGCore.GSPR_IDX, int_reg)
 323             value = yield from get_dmi(self.dmi, DBGCore.GSPR_DATA)
 324
 325             print("after test %s reg %2d value %x" %
 326             (self.test.name, int_reg, value))
 327
 328         # pull a reset
 329         yield from set_dmi(self.dmi, DBGCore.CTRL, 1<<DBGCtrl.RESET)
 330         yield
 331
 332
 333 class TestRunner(FHDLTestCase):
 334     def __init__(self, tst_data, microwatt_mmu=False, rom=None,
 335                         svp64=True, run_hdl=True, run_sim=True):
 336         super().__init__("run_all")
 337         self.test_data = tst_data
 338         self.microwatt_mmu = microwatt_mmu
 339         self.rom = rom
 340         self.svp64 = svp64
 341         self.run_hdl = run_hdl
 342         self.run_sim = run_sim
 343
 344     def run_all(self):
 345         m = Module()
 346         comb = m.d.comb
 347         if self.microwatt_mmu:
 348             ldst_ifacetype = 'test_mmu_cache_wb'
 349         else:
 350             ldst_ifacetype = 'test_bare_wb'
 351         imem_ifacetype = 'test_bare_wb'
 352
 353         pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
 354                              imem_ifacetype=imem_ifacetype,
 355                              addr_wid=48,
 356                              mask_wid=8,
 357                              imem_reg_wid=64,
 358                              # wb_data_width=32,
 359                              use_pll=False,
 360                              nocore=False,
 361                              xics=False,
 362                              gpio=False,
 363                              regreduce=True,
 364                              svp64=self.svp64,
 365                              mmu=self.microwatt_mmu,
 366                              reg_wid=64)
 367
 368         ###### SETUP PHASE #######
 369         # StateRunner.setup_for_test()
 370
 371         # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 372         if self.run_hdl:
 373             hdlrun = HDLRunner(self, m, pspec)
 374
 375         if self.run_sim:
 376             simrun = SimRunner(self, m, pspec)
 377
 378         # run core clock at same rate as test clock
 379         intclk = ClockSignal("coresync")
 380         comb += intclk.eq(ClockSignal())
 381
 382         # nmigen Simulation - everything runs around this, so it
 383         # still has to be created.
 384         sim = Simulator(m)
 385         sim.add_clock(1e-6)
 386
 387         def process():
 388
 389             ###### PREPARATION PHASE AT START OF RUNNING #######
 390             # StateRunner.setup_during_test()
 391             # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 392             # but "normalise" the APIs, make openpower-isa StateRunner
 393             # dummy "yield" functions so if they're not provided at least
 394             # there is a fallback which can be "yielded".
 395
 396             if self.run_sim:
 397                 yield from simrun.setup_during_test() # TODO, some arguments?
 398
 399             if self.run_hdl:
 400                 yield from hdlrun.setup_during_test()
 401
 402             # get each test, completely reset the core, and run it
 403
 404             for test in self.test_data:
 405
 406                 with self.subTest(test.name):
 407
 408                     ###### PREPARATION PHASE AT START OF TEST #######
 409                     # StateRunner.prepare_for_test()
 410                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 411
 412                     if self.run_sim:
 413                         yield from simrun.prepare_for_test(test)
 414
 415                     if self.run_hdl:
 416                         yield from hdlrun.prepare_for_test(test)
 417
 418                     print(test.name)
 419                     program = test.program
 420                     print("regs", test.regs)
 421                     print("sprs", test.sprs)
 422                     print("cr", test.cr)
 423                     print("mem", test.mem)
 424                     print("msr", test.msr)
 425                     print("assem", program.assembly)
 426                     gen = list(program.generate_instructions())
 427                     insncode = program.assembly.splitlines()
 428                     instructions = list(zip(gen, insncode))
 429
 430                     ###### RUNNING OF EACH TEST #######
 431                     # StateRunner.step_test()
 432
 433                     # Run two tests (TODO, move these to functions)
 434                     # * first the Simulator, collate a batch of results
 435                     # * then the HDL, likewise
 436                     #   (actually, the other way round because running
 437                     #    Simulator somehow modifies the test state!)
 438                     # * finally, compare all the results
 439
 440                     # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 441
 442                     ##########
 443                     # 1. HDL
 444                     ##########
 445                     if self.run_hdl:
 446                         hdl_states = yield from hdlrun.run_test(instructions)
 447
 448                     ##########
 449                     # 2. Simulator
 450                     ##########
 451
 452                     if self.run_sim:
 453                         sim_states = yield from simrun.run_test(
 454                                                           instructions, gen,
 455                                                           insncode)
 456
 457                     ###### COMPARING THE TESTS #######
 458
 459                     ###############
 460                     # 3. Compare
 461                     ###############
 462
 463                     if self.run_sim:
 464                         last_sim = copy(sim_states[-1])
 465                     elif self.run_hdl:
 466                         last_sim = copy(hdl_states[-1])
 467                     else:
 468                         last_sim = None # err what are you doing??
 469
 470                     if self.run_hdl and self.run_sim:
 471                         for simstate, hdlstate in zip(sim_states, hdl_states):
 472                             simstate.compare(hdlstate)     # register check
 473                             simstate.compare_mem(hdlstate) # memory check
 474
 475                     if self.run_hdl:
 476                         print ("hdl_states")
 477                         for state in hdl_states:
 478                             print (state)
 479
 480                     if self.run_sim:
 481                         print ("sim_states")
 482                         for state in sim_states:
 483                             print (state)
 484
 485                     # compare against expected results
 486                     if test.expected is not None:
 487                         # have to put these in manually
 488                         test.expected.to_test = test.expected
 489                         test.expected.dut = self
 490                         test.expected.state_type = "expected"
 491                         test.expected.code = 0
 492                         # do actual comparison, against last item
 493                         last_sim.compare(test.expected)
 494
 495                     if self.run_hdl and self.run_sim:
 496                         self.assertTrue(len(hdl_states) == len(sim_states),
 497                                     "number of instructions run not the same")
 498
 499                 ###### END OF A TEST #######
 500                 # StateRunner.end_test()
 501                 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 502
 503                 if self.run_sim:
 504                     yield from simrun.end_test() # TODO, some arguments?
 505
 506                 if self.run_hdl:
 507                     yield from hdlrun.end_test()
 508
 509             ###### END OF EVERYTHING (but none needs doing, still call fn) ####
 510             # StateRunner.cleanup()
 511             # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
 512
 513             if self.run_sim:
 514                 yield from simrun.cleanup() # TODO, some arguments?
 515
 516             if self.run_hdl:
 517                 yield from hdlrun.cleanup()
 518
 519         styles = {
 520             'dec': {'base': 'dec'},
 521             'bin': {'base': 'bin'},
 522             'closed': {'closed': True}
 523         }
 524
 525         traces = [
 526             'clk',
 527             ('state machines', 'closed', [
 528                 'fetch_pc_i_valid', 'fetch_pc_o_ready',
 529                 'fetch_fsm_state',
 530                 'fetch_insn_o_valid', 'fetch_insn_i_ready',
 531                 'pred_insn_i_valid', 'pred_insn_o_ready',
 532                 'fetch_predicate_state',
 533                 'pred_mask_o_valid', 'pred_mask_i_ready',
 534                 'issue_fsm_state',
 535                 'exec_insn_i_valid', 'exec_insn_o_ready',
 536                 'exec_fsm_state',
 537                 'exec_pc_o_valid', 'exec_pc_i_ready',
 538                 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
 539                 'is_last', 'dec2.no_out_vec']),
 540             {'comment': 'fetch and decode'},
 541             (None, 'dec', [
 542                 'cia[63:0]', 'nia[63:0]', 'pc[63:0]',
 543                 'cur_pc[63:0]', 'core_core_cia[63:0]']),
 544             'raw_insn_i[31:0]',
 545             'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
 546             ('svp64 decoding', 'closed', [
 547                 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
 548                 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
 549                 'dec2.sv_rm_dec.ptype_in',
 550                 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
 551                 'dstmask[63:0]', 'srcmask[63:0]',
 552                 'dregread[4:0]', 'dinvert',
 553                 'sregread[4:0]', 'sinvert',
 554                 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
 555                 'core.int.pred__ren']),
 556             ('register augmentation', 'dec', 'closed', [
 557                 {'comment': 'v3.0b registers'},
 558                 'dec2.dec_o.RT[4:0]',
 559                 'dec2.dec_a.RA[4:0]',
 560                 'dec2.dec_b.RB[4:0]',
 561                 ('Rdest', [
 562                     'dec2.o_svdec.reg_in[4:0]',
 563                     ('dec2.o_svdec.spec[2:0]', 'bin'),
 564                     'dec2.o_svdec.reg_out[6:0]']),
 565                 ('Rsrc1', [
 566                     'dec2.in1_svdec.reg_in[4:0]',
 567                     ('dec2.in1_svdec.spec[2:0]', 'bin'),
 568                     'dec2.in1_svdec.reg_out[6:0]']),
 569                 ('Rsrc1', [
 570                     'dec2.in2_svdec.reg_in[4:0]',
 571                     ('dec2.in2_svdec.spec[2:0]', 'bin'),
 572                     'dec2.in2_svdec.reg_out[6:0]']),
 573                 {'comment': 'SVP64 registers'},
 574                 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
 575             ]),
 576             {'comment': 'svp64 context'},
 577             'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
 578             'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
 579             'core_core_dststep[6:0]',
 580             {'comment': 'issue and execute'},
 581             'core.core_core_insn_type',
 582             (None, 'dec', [
 583                 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
 584             'issue_i', 'busy_o',
 585             {'comment': 'dmi'},
 586             'dbg.dmi_req_i', 'dbg.dmi_ack_o',
 587             {'comment': 'instruction memory'},
 588             'imem.sram.rdport.memory(0)[63:0]',
 589             {'comment': 'registers'},
 590             # match with soc.regfile.regfiles.IntRegs port names
 591             'core.int.rp_src1.memory(0)[63:0]',
 592             'core.int.rp_src1.memory(1)[63:0]',
 593             'core.int.rp_src1.memory(2)[63:0]',
 594             'core.int.rp_src1.memory(3)[63:0]',
 595             'core.int.rp_src1.memory(4)[63:0]',
 596             'core.int.rp_src1.memory(5)[63:0]',
 597             'core.int.rp_src1.memory(6)[63:0]',
 598             'core.int.rp_src1.memory(7)[63:0]',
 599             'core.int.rp_src1.memory(9)[63:0]',
 600             'core.int.rp_src1.memory(10)[63:0]',
 601             'core.int.rp_src1.memory(13)[63:0]'
 602         ]
 603
 604         # PortInterface module path varies depending on MMU option
 605         if self.microwatt_mmu:
 606             pi_module = 'core.ldst0'
 607         else:
 608             pi_module = 'core.fus.ldst0'
 609
 610         traces += [('ld/st port interface', {'submodule': pi_module}, [
 611             'oper_r__insn_type',
 612             'ldst_port0_is_ld_i',
 613             'ldst_port0_is_st_i',
 614             'ldst_port0_busy_o',
 615             'ldst_port0_addr_i[47:0]',
 616             'ldst_port0_addr_i_ok',
 617             'ldst_port0_addr_ok_o',
 618             'ldst_port0_exc_happened',
 619             'ldst_port0_st_data_i[63:0]',
 620             'ldst_port0_st_data_i_ok',
 621             'ldst_port0_ld_data_o[63:0]',
 622             'ldst_port0_ld_data_o_ok',
 623             'exc_o_happened',
 624             'cancel'
 625         ])]
 626
 627         if self.microwatt_mmu:
 628             traces += [
 629                 {'comment': 'microwatt_mmu'},
 630                 'core.fus.mmu0.alu_mmu0.illegal',
 631                 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
 632                 'core.fus.mmu0.alu_mmu0.mmu.state',
 633                 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
 634                 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
 635                 {'comment': 'wishbone_memory'},
 636                 'core.fus.mmu0.alu_mmu0.dcache.stb',
 637                 'core.fus.mmu0.alu_mmu0.dcache.cyc',
 638                 'core.fus.mmu0.alu_mmu0.dcache.we',
 639                 'core.fus.mmu0.alu_mmu0.dcache.ack',
 640                 'core.fus.mmu0.alu_mmu0.dcache.stall,'
 641             ]
 642
 643         write_gtkw("issuer_simulator.gtkw",
 644                    "issuer_simulator.vcd",
 645                    traces, styles, module='top.issuer')
 646
 647         # add run of instructions
 648         sim.add_sync_process(process)
 649
 650         # optionally, if a wishbone-based ROM is passed in, run that as an
 651         # extra emulated process
 652         if self.rom is not None:
 653             dcache = core.fus.fus["mmu0"].alu.dcache
 654             default_mem = self.rom
 655             sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
 656
 657         with sim.write_vcd("issuer_simulator.vcd"):
 658             sim.run()