f95370d0c984f68f77de51d5bfc5e11b60b6a892
3 This module implements the creation, inspection and comparison
4 of test states for TestIssuer HDL
8 from openpower
.decoder
.power_enums
import XER_bits
9 from openpower
.util
import log
10 from openpower
.test
.state
import (State
, state_add
, state_factory
,
12 from soc
.fu
.compunits
.test
.test_compunit
import get_l0_mem
14 class HDLState(State
):
15 """HDLState: Obtains registers and memory from an nmigen simulator
16 object by implementing State class methods.
18 def __init__(self
, core
):
27 def get_intregs(self
):
30 if self
.core
.regs
.int.unary
:
31 rval
= yield self
.core
.regs
.int.regs
[i
].reg
33 rval
= yield self
.core
.regs
.int.memory
._array
[i
]
34 self
.intregs
.append(rval
)
35 log("class hdl int regs", list(map(hex, self
.intregs
)))
40 rval
= yield self
.core
.regs
.cr
.regs
[7-i
].reg
41 self
.crregs
.append(rval
)
42 log("class hdl cr regs", list(map(hex, self
.crregs
)))
46 self
.xr
= self
.core
.regs
.xer
47 self
.so
= yield self
.xr
.regs
[self
.xr
.SO
].reg
48 self
.ov
= yield self
.xr
.regs
[self
.xr
.OV
].reg
49 self
.ca
= yield self
.xr
.regs
[self
.xr
.CA
].reg
50 self
.xregs
.extend((self
.so
, self
.ov
, self
.ca
))
51 log("class hdl xregs", list(map(hex, self
.xregs
)))
55 self
.state
= self
.core
.regs
.state
56 # relies on the state.r_port being permanently held as PC
57 self
.pc
= yield self
.state
.r_ports
['cia'].o_data
58 self
.pcl
.append(self
.pc
)
59 log("class hdl pc", hex(self
.pc
))
63 # get the underlying HDL-simulated memory from the L0CacheBuffer
64 if hasattr(self
.core
, "icache"):
65 # err temporarily ignore memory
66 return # XXX have to work out how to deal with wb_get
67 hdlmem
= get_l0_mem(self
.core
.l0
)
68 for i
in range(hdlmem
.depth
):
69 value
= yield hdlmem
._array
[i
] # should not really do this
73 # add to State Factory
74 state_add('hdl', HDLState
)