src/soc/simulator/test_sim.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay
   3 from nmigen.test.utils import FHDLTestCase
   4 import unittest
   5 from soc.simulator.internalop_sim import InternalOpSimulator
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_enums import (Function, InternalOp,
   8                                      In1Sel, In2Sel, In3Sel,
   9                                      OutSel, RC, LdstLen, CryIn,
  10                                      single_bit_flags, Form, SPR,
  11                                      get_signal_name, get_csv)
  12 from soc.decoder.power_decoder2 import (PowerDecode2)
  13 from soc.simulator.gas import get_assembled_instruction
  14
  15
  16 class Register:
  17     def __init__(self, num):
  18         self.num = num
  19
  20
  21 class InstrList:
  22     def __init__(self, lst):
  23         self.instrs = [x + "\n" for x in lst]
  24
  25     def generate_instructions(self):
  26         return iter(self.instrs)
  27
  28
  29 class DecoderTestCase(FHDLTestCase):
  30
  31     def run_tst(self, generator, simulator):
  32         m = Module()
  33         comb = m.d.comb
  34         instruction = Signal(32)
  35
  36         pdecode = create_pdecode()
  37
  38         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
  39         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
  40         sim = Simulator(m)
  41         gen = generator.generate_instructions()
  42
  43         def process():
  44             for ins in gen:
  45                 print("instr", ins.strip())
  46
  47                 # turn the instruction into binary data (endian'd)
  48                 ibin = get_assembled_instruction(ins, 0)
  49
  50                 # ask the decoder to decode this binary data (endian'd)
  51                 yield pdecode2.dec.bigendian.eq(0)  # little / big?
  52                 yield instruction.eq(ibin)          # raw binary instr.
  53                 yield Delay(1e-6)
  54                 yield from simulator.execute_op(pdecode2)
  55
  56         sim.add_process(process)
  57         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
  58                            traces=[pdecode2.ports()]):
  59             sim.run()
  60
  61     def test_example(self):
  62         lst = ["addi 1, 0, 0x1234",
  63                "addi 2, 0, 0x5678",
  64                "add  3, 1, 2",
  65                "and  4, 1, 2"]
  66         gen = InstrList(lst)
  67
  68         simulator = InternalOpSimulator()
  69
  70         self.run_tst(gen, simulator)
  71         simulator.regfile.assert_gprs(
  72             {1: 0x1234,
  73              2: 0x5678,
  74              3: 0x68ac,
  75              4: 0x1230})
  76
  77     def test_ldst(self):
  78         lst = ["addi 1, 0, 0x1234",
  79                "addi 2, 0, 0x5678",
  80                "stw  1, 0(2)",
  81                "lwz  3, 0(2)"]
  82         gen = InstrList(lst)
  83
  84         simulator = InternalOpSimulator()
  85
  86         self.run_tst(gen, simulator)
  87         simulator.regfile.assert_gprs(
  88             {1: 0x1234,
  89              2: 0x5678,
  90              3: 0x1234})
  91
  92     def test_ldst_extended(self):
  93         lst = ["addi 1, 0, 0x1234",
  94                "addi 2, 0, 0x5678",
  95                "addi 4, 0, 0x40",
  96                "stw  1, 0x40(2)",
  97                "lwzx  3, 4, 2"]
  98         gen = InstrList(lst)
  99
 100         simulator = InternalOpSimulator()
 101
 102         self.run_tst(gen, simulator)
 103         simulator.regfile.assert_gprs(
 104             {1: 0x1234,
 105              2: 0x5678,
 106              3: 0x1234})
 107     def test_ldst_widths(self):
 108         lst = [" lis 1, 0xdead",
 109                "ori 1, 1, 0xbeef",
 110                "addi 2, 0, 0x1000",
 111                "std 1, 0(2)",
 112                "lbz 1, 5(2)",
 113                "lhz 3, 4(2)",
 114                "lwz 4, 4(2)",
 115                "ori 5, 0, 0x12",
 116                "stb 5, 5(2)",
 117                "ld  5, 0(2)"]
 118         gen = InstrList(lst)
 119         simulator = InternalOpSimulator()
 120         self.run_tst(gen, simulator)
 121         simulator.regfile.assert_gprs({
 122             1: 0xad,
 123             3: 0xdead,
 124             4: 0xdeadbeef,
 125             5: 0xffffffffde12beef})  # checked with qemu
 126
 127
 128 if __name__ == "__main__":
 129     unittest.main()