dfb4faa277281f67018da30e3460f82d5175abc6
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import (create_pdecode
)
6 from soc
.decoder
.power_enums
import (Function
, InternalOp
,
7 In1Sel
, In2Sel
, In3Sel
,
8 OutSel
, RC
, LdstLen
, CryIn
,
9 single_bit_flags
, Form
, SPR
,
10 get_signal_name
, get_csv
)
11 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
12 from soc
.simulator
.program
import Program
13 from soc
.simulator
.qemu
import run_program
14 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import TestCase
16 from soc
.simulator
.test_sim
import DecoderBase
17 from soc
.config
.endian
import bigendian
20 class TrapSimTestCases(FHDLTestCase
):
23 def __init__(self
, name
="div"):
24 super().__init
__(name
)
27 def test_0_not_twi(self
):
28 lst
= ["addi 1, 0, 0x5678",
31 with
Program(lst
, bigendian
) as program
:
32 self
.run_tst_program(program
, [1])
34 def test_1_twi_eq(self
):
35 lst
= ["addi 1, 0, 0x5678",
38 with
Program(lst
, bigendian
) as program
:
39 self
.run_tst_program(program
, [1])
41 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
43 initial_regs
= [0] * 32
44 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
46 self
.test_data
.append(tc
)
49 class TrapDecoderTestCase(DecoderBase
, TrapSimTestCases
):
53 if __name__
== "__main__":